CN114649278A - Electronic package and manufacturing method thereof - Google Patents

Abstract

The invention relates to an electronic package and a method for making the same, comprising arranging electronic components in a die placement area of a carrier and electrically connecting the carrier, and arranging a bonding layer outside the die placement area of the carrier to surround the carrier For the electronic component, the heat sink is combined with the bonding layer to be disposed on the carrier and cover the electronic component, so that the electronic component can be deflected relative to the die placement area on the carrier, so that the outline of the electronic component is not aligned. The boundary of the die area should be placed to balance the stress distribution of the electronic package and avoid delamination between the heat sink and the electronic component.

Description

Electronic package and method of making the same

technical field

The present invention relates to a semiconductor device, in particular to an electronic package with a heat sink and a manufacturing method thereof.

Background technique

With the improvement of the function and processing speed of electronic products, the semiconductor chip, which is the core component of the electronic product, needs to have higher-density electronic components and electronic circuits. In order to quickly dissipate the heat energy to the atmosphere, a heat sink (HeatSink or Heat Spreader) is usually arranged in the semiconductor package structure. heat generated.

As shown in FIG. 1A , in a conventional method for manufacturing a heat dissipation type semiconductor package 1 , a semiconductor chip 11 and its active surface 11 a are firstly mounted on a package by flip-chip bonding (ie, through conductive bumps 110 and underfill 111 ). On the die placement area A of the substrate 10 (as shown in FIG. 1A ′), a heat sink 13 and its top sheet 130 are bonded to the non-active surface 11 b of the semiconductor chip 11 via the thermal conductive layer 12 , and the heat sink 13 The supporting feet 131 are mounted on the package substrate 10 via the adhesive layer 14 . Next, an encapsulation molding operation is performed so that an encapsulation compound (not shown) covers the semiconductor chip 11 and the heat sink 13, and the top sheet 130 of the heat sink 13 is exposed to the encapsulation compound to directly contact the atmosphere.

During operation, the heat energy generated by the semiconductor chip 11 is conducted to the heat dissipation member 13 through the non-active surface 11 b and the thermal conductive layer 12 to dissipate heat to the outside of the semiconductor package 1 .

However, in the conventional semiconductor package 1 , the contour of the semiconductor chip 11 after placement corresponds to the boundary of the placement die area A (as shown in FIG. 1A ′), so that both the heat sink 13 and the semiconductor chip 11 are related to each other. The thermally conductive layer 12 has a great difference in the coefficient of thermal expansion (CTE Mismatch) and the generated stress cannot be dispersed, causing the semiconductor package 1 to deform (ie warp), as shown in FIG. 1B , causing the heat sink 13 Delamination (gap t as shown in FIG. 1B ) easily occurs between the top sheet 130 and the deformed thermal conductive layer 12 ′ (or with the semiconductor chip 11 ), which not only causes the thermal conductivity to decrease, but also reduces the semiconductor package 1 's reliability.

Therefore, how to overcome the above-mentioned various problems of the prior art has actually become a difficult problem to be overcome in the current industry.

SUMMARY OF THE INVENTION

In view of the above-mentioned defects of the prior art, the present invention provides an electronic package and a manufacturing method thereof to avoid delamination between the heat sink and the electronic component.

The electronic package of the present invention includes: a carrier, which defines a die placement area; an electronic component, which is arranged in the die placement area of the carrier and is electrically connected to the carrier, wherein the electronic component is arranged on the carrier The contour on the component does not correspond to the boundary of the die placement area; the bonding layer is provided on the carrier and located outside the die placement area to surround the electronic component; and the heat sink is combined with the bonding layer to be provided on the on the carrier and cover the electronic component.

The present invention also provides a method for manufacturing an electronic package, comprising: providing a carrier defining a die placement area; arranging an electronic component in the die placement area of the carrier and electrically connecting the carrier, and combining the The layer is arranged outside the chip placement area of the carrier and surrounds the electronic component, wherein the outline of the electronic component disposed on the carrier does not correspond to the boundary of the die placement area; and the heat sink is combined with the bonding layer to make The heat sink is arranged on the carrier and covers the electronic component.

In the aforementioned electronic package and its manufacturing method, the die placement area is rectangular, and the electronic component has a quadrangular outline, so that the corners of the electronic component are located on the edge of the die placement area. For example, the corners of the electronic component are aligned with the bonding layer.

In the aforementioned electronic package and its manufacturing method, the bonding layer is a ring body with a plurality of notches, wherein the positions of the plurality of notches are aligned or not aligned with each other. For example, the electronic component has a rectangular profile with corners that are not aligned with the notch. Alternatively, the ring body is rectangular, and the plurality of notches are respectively located on different ring sides of the ring body. Preferably, the size of the notches on a single ring side of the ring body is 1/10 of the size of the ring side .

In the aforementioned electronic package and its manufacturing method, the bonding layer includes a first segment and a second segment separated from each other, so as to form a plurality of gaps between the first segment and the second segment, and the The shape of the first section is not the same as the shape of the second section. For example, the area of the carrier for contacting and combining with the first section is the same as the area of the carrier for contacting and combining with the second section.

As can be seen from the above, in the electronic package and the manufacturing method thereof of the present invention, the outline of the electronic component disposed on the carrier does not correspond to the boundary of the die placement area, so that the carrier can effectively balance the stress on the carrier Therefore, compared with the prior art, the electronic package can maintain the distance between the heat sink and the carrier, so as to avoid delamination between the heat sink and the electronic element, thereby improving the electronic package. 's reliability.

In addition, the present invention can improve the coverage and flatness of the heat sink through the design that the position of the notch does not face the corner of the electronic component, thereby effectively reducing the degree of warpage of the electronic package.

In addition, in the present invention, the size of the notch on the single ring edge of the bonding layer is 1/10 of the size of the ring edge, so as to help the carrier to balance the stress distribution thereon, thereby effectively reducing the electronic package. degree of warpage.

In addition, in the present invention, the outline of the electronic component disposed on the carrier does not correspond to the boundary of the die area, so that the circuit layout of the carrier can be effectively matched with the specially designed electronic component, thereby enhancing the electronic component. computing power.

Description of drawings

FIG. 1A is a schematic cross-sectional view of a conventional semiconductor package.

Fig. 1A' is a schematic top plan view of Fig. 1A.

FIG. 1B is a schematic cross-sectional view of a defective state of a conventional semiconductor package.

2A to 2B are schematic cross-sectional views of the manufacturing method of the electronic package of the present invention.

FIG. 3A is a schematic top plan view of FIG. 2A .

3B and 3C are schematic top plan views of different aspects of FIG. 3A .

Description of reference numerals

1: Semiconductor package

10: Package substrate

11: Semiconductor chip

11a, 21a: Action surface

11b, 21b: Non-active surfaces

110,210: Conductive bumps

111,211: Primer

12, 12', 22: Thermally conductive layer

13,23: Heat sink

130: Top sheet

131, 231: Support feet

14: Adhesive layer

2: Electronic packages

20: Carrier

21: Electronic Components

230: heat sink

24,34: Bonding Layer

24a, 24b, 24c, 24d: Ring edge

240,340: Notch

341: First Section

342: Second Section

A: Crystal placement area

D, R: area

L: sideline

t: gap

X1, X2: Diagonal

Y: axis.

Detailed ways

The embodiments of the present invention are described below through specific embodiments, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

It should be noted that the structures, proportions, sizes, etc. shown in the drawings of this specification are only used to cooperate with the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the conditions for the implementation of the present invention. , therefore does not have technical substantive significance, any structural modification, proportional relationship change or size adjustment, without affecting the effect that the present invention can produce and the purpose that can be achieved, should still fall within the scope of the present invention. The technical content must be able to cover the scope. At the same time, the terms such as "above", "first", "second", "one", etc. quoted in this specification are only for the convenience of description and clarity, and are not used to limit the scope of the present invention. Changes or adjustments of their relative relationships, without substantial changes to the technical content, should also be regarded as the scope of the present invention.

2A to 2B are schematic cross-sectional views of the manufacturing method of the electronic package 2 of the present invention.

As shown in FIG. 2A , at least one electronic element 21 is disposed on a carrier 20 and a bonding layer 24 is formed, so that the electronic element 21 is electrically connected to the carrier 20 , wherein the carrier 20 defines at least one for The die placement area A of the electronic component 21 is provided (as shown in FIG. 3A ), and the outline of the electronic component 21 after being placed on the carrier 20 does not correspond to the boundary of the die placement area A.

In this embodiment, the carrier 20 is, for example, a package substrate with a core layer and a circuit structure or a circuit structure without a core layer, which forms a circuit layer on a dielectric material, such as a fanout. ) type redistribution layer (redistribution layer, referred to as RDL). For example, the die placement area A of the carrier 20 is defined as a rectangle, such as a square as shown in FIG. 3A . It should be understood that the carrier 20 can also be other carrier structures capable of carrying electronic components such as chips, such as a lead frame or a silicon interposer, which is not limited to the above.

In addition, the electronic element 21 is an active element, a passive element, or a combination of the two, etc., and it is in the form of a rectangular quadrilateral sheet (the square sheet as shown in FIG. 3A ), so that the electronic element 21 is opposite to the die placement area. A deflected configuration, such as turning a 90-degree angle, makes the corner of the electronic element 21 located on the edge L of the die placement area A and not correspondingly located at the corner of the die placement area A, wherein the active element is, for example, a semiconductor chip, and the passive components are, for example, resistors, capacitors and inductors. For example, the electronic device 21 has an opposing active surface 21a and a non-active surface 21b, and the active surface 21a is provided with a plurality of conductive bumps 210, so that the electronic device 21 is combined with the conductive bumps 210 in a flip-chip manner. The carrier 20 is electrically connected, and the conductive bumps 210 can be covered with a primer 211 . However, there are many ways of connecting the electronic component 21 to the carrier 20 , such as wire bonding and packaging, and are not limited to the above.

In addition, a thermal conductive layer 22 such as a thermal interface material (Thermal Interface Material, TIM for short) or a general thermal conductive adhesive may be formed on the non-active surface 21 b of the electronic component 21 .

In addition, the bonding layer 24 is an adhesive layer such as glue, which is located at the edge of the carrier 20 to surround the periphery of the electronic component 21, so that the bonding layer 24 presents a rectangular ring body with a plurality of notches 240, and The plurality of notches 240 are formed on two of the four ring edges 24a, 24b, 24c, 24d, as shown in FIG. 3A and FIG. 3B . For example, the notches 240 are formed on the two opposite ring edges 24a, 24b, and the positions of the notches 240 may be aligned with each other (as shown in FIG. 3A on the same axis Y) or not aligned (as shown in FIG. 3B ), The corners of the electronic element 21 are aligned with the bonding layer 24 but not aligned with the notches 240 , that is, the diagonal lines X1 and X2 of the electronic element 21 do not extend through the notches 240 . Preferably, in one of the two ring edges 24a, 24b of the bonding layer 24 having the notches 240, as shown in FIG. 3B, the carrier 20 corresponds to the area (length) R exposed to the notches 240 It is 1/10 of the area (length) D of the carrier 20 for contacting and combining the ring edge 24a.

As shown in FIG. 2B , a heat sink 23 is combined with the bonding layer 24 to be disposed on the carrier 20 , and the heat sink 23 is disposed on the electronic element 21 through the thermal conductive layer 22 to cover the electronic element 21 .

In this embodiment, the heat sink 23 has a heat sink 230 and a plurality of support pins 231 disposed on the lower side of the heat sink 230 . The feet 231 are bonded to the bonding layer 24 with their ends. For example, the heat sink 23 is disposed on the carrier 20 by pressing, and the pressing temperature (ie, the heat-resistant temperature of the carrier 20 ) is at least 120°C, preferably 125°C.

In addition, the heat dissipation body 230 and the support legs 231 are integrally formed; in other embodiments, the heat dissipation body 230 and the support legs 231 may be separately formed instead of integrally formed. It should be understood that there are many types of the heat dissipation member, which are not limited to the above.

In addition, the layout area of the bonding layer 24 can be designed according to requirements. For example, the bonding layer 34 may include a first segment 341 and a second segment 342 separated from each other, as shown in FIG. 3C , between the end of the first segment 341 and the end of the second segment 342 A plurality of notches 340 are formed, and the shape of the first section 341 is different from the shape of the second section 342 . Preferably, the area of the carrier 20 for contacting and combining with the first section 341 is the same as the area of the carrier 20 for contacting and combining with the second section 342 .

In the manufacturing method of the present invention, the electronic component 21 is deflected relative to the die placement area A, so that the outline of the electronic component 21 after being placed on the carrier 20 does not correspond to the boundary of the die placement area A, so that the carrier Compared with the prior art, the electronic package 2 can maintain the distance between the heat sink 230 (or the heat sink 23 ) and the carrier 20 to avoid the heat dissipation Delamination occurs between the body 230 (or the heat sink 23 ) and the thermally conductive layer 22 (or the electronic component 21 ), thereby improving the reliability of the electronic package 2 . It should be understood that the outline of the electronic component 21 can also be changed so that the outline of the electronic component 21 after being disposed on the carrier 20 does not correspond to the boundary of the placement die area A, such as a rhombus quadrilateral chip body.

In addition, through the design that the positions of the gaps 240 and 340 do not face the corners of the electronic component 21, it is beneficial to improve the coverage and flatness of the heat sink 230 (or the heat sink 23), thereby effectively reducing the electronic package. 2 degree of warpage.

In addition, the size (such as area R or length) of the gap 240 on the single ring edge 24a of the bonding layer 24 is designed to be 1/10 of the size (such as area D or length) of the ring edge 24a, so as to facilitate the bearing The component 20 balances the stress distribution thereon, thereby effectively reducing the degree of warpage of the electronic package 2 .

In addition, the contour of the electronic component 21 disposed on the carrier 20 does not correspond to the design of the boundary of the die placement area A, so that the circuit layout of the carrier 20 can be effectively matched with the specially designed electronic component 21, so that it can be The computing power of the electronic component 21 is enhanced.

The present invention also provides an electronic package 2 , comprising: a carrier 20 , at least one electronic component 21 , a bonding layer 24 , 34 and a heat sink 23 .

The carrier 20 has at least one die placement area A. As shown in FIG.

The electronic component 21 is disposed on the carrier 20 and is located in the die placement area A and is electrically connected to the carrier 20, wherein the outline of the electronic component 21 after being disposed on the carrier 20 does not correspond to the Set the boundary of the crystal region A.

The bonding layers 24 and 34 are formed on the carrier 20 and located outside the die placement area A to surround the electronic device 21 .

The heat sink 23 is combined with the bonding layers 24 and 34 to be disposed on the carrier 20 and cover the electronic element 21 .

In one embodiment, the die placement area A is rectangular, and the electronic device 21 has a quadrangular outline, so that the corner of the electronic device 21 is located on the edge L of the die placement area A. As shown in FIG. For example, the corners of the electronic component 21 are aligned with the bonding layers 24 , 34 .

In one embodiment, the bonding layers 24, 34 are rings having a plurality of notches 240, 340, and the positions of the plurality of notches 240, 340 are aligned or not aligned with each other. For example, the electronic component 21 has a rectangular profile, the corners of which are not aligned with the notches 240,340. Alternatively, the ring body is rectangular, and the plurality of notches 240 are respectively located on different ring sides 24a and 24b of the ring body. Preferably, the size of the notches 240 on a single ring side 24a of the ring body is the size of the ring side 1/10 the size of 24a.

In one embodiment, the bonding layer 34 includes a first segment 341 and a second segment 342 that are separated from each other to form a plurality of segments between the end of the first segment 341 and the end of the second segment 342 . The notch 340 is formed, and the shape of the first section 341 is different from the shape of the second section 342 . For example, the area of the carrier 20 for contacting and combining with the first section 341 is the same as the area of the carrier 20 for contacting and combining with the second section 342 .

To sum up, in the electronic package and the manufacturing method thereof of the present invention, the outline of the electronic device after being disposed on the carrier does not correspond to the boundary of the placement die, so as to balance the overall stress distribution of the electronic package, so The electronic package can maintain the distance between the heat sink and the carrier, so as to avoid delamination between the heat sink and the electronic element, thereby improving the reliability of the electronic package.

In addition, since the position of the notch does not face the corner of the electronic component, the coverage and flatness of the heat sink can be improved, thereby effectively reducing the degree of warpage of the electronic package.

In addition, the size of the notch on the single ring edge through the bonding layer is designed to be 1/10 of the size of the ring edge, so as to balance the stress distribution on the carrier, thereby effectively reducing the warpage of the electronic package. degree.

The above embodiments are used to illustrate the principles and effects of the present invention, but not to limit the present invention. Any person skilled in the art can make modifications to the above embodiments without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be as listed in the claims.

Claims (20)

1. An electronic package, characterized in that, comprising: a carrier, which defines a crystal placement area; an electronic component, which is arranged in the die placement area of the carrier and is electrically connected to the carrier, wherein the outline of the electronic component arranged on the carrier does not correspond to the boundary of the die placement area; a bonding layer disposed on the carrier and outside the die placement area to surround the electronic component; and The heat sink is combined with the bonding layer to be disposed on the carrier and cover the electronic element. 2 . The electronic package of claim 1 , wherein the die placement area is rectangular, and the electronic component has a quadrangular outline, so that corners of the electronic component are located on the edge of the die placement area. 3 . 3 . The electronic package of claim 2 , wherein corners of the electronic component are aligned with the bonding layer. 4 . 4 . The electronic package of claim 1 , wherein the bonding layer is a ring body with a plurality of notches. 5 . 5 . The electronic package of claim 4 , wherein the positions of the plurality of notches are aligned or not aligned with each other. 6 . 6 . The electronic package of claim 4 , wherein the electronic component has a rectangular outline, and the corners thereof are not aligned with the notch. 7 . 7 . The electronic package of claim 4 , wherein the ring body is rectangular, and the plurality of notches are respectively located on different ring edges of the ring body. 8 . 8 . The electronic package of claim 7 , wherein the size of the notch on the single ring edge of the ring body is 1/10 of the size of the ring edge. 9 . 9 . The electronic package of claim 1 , wherein the bonding layer comprises a first segment and a second segment separated from each other so as to be formed between the first segment and the second segment. 10 . A plurality of notches, and the shape of the first section is different from the shape of the second section. 10 . The electronic package of claim 9 , wherein an area of the carrier for contacting and bonding with the first section is the same as an area of the carrier for contacting and bonding with the second section. 11 . 11. A method for making an electronic package, comprising: providing a carrier defining a die placement region; The electronic component is arranged in the die placement area of the carrier and electrically connected to the carrier, and the bonding layer is arranged outside the die placement area of the carrier and surrounds the electronic component, wherein the electronic component is arranged in the carrier The contours on the part do not correspond to the boundaries of the placement region; and The heat sink is combined with the bonding layer, so that the heat sink is arranged on the carrier and covers the electronic component. 12 . The method of claim 11 , wherein the die placement area is rectangular, and the electronic component has a quadrangular outline, so that corners of the electronic component are located on the edge of the die placement area. 13 . . 13 . The method of claim 12 , wherein a corner of the electronic component is aligned with the bonding layer. 14 . 14 . The method of claim 11 , wherein the bonding layer is a ring body with a plurality of notches. 15 . 15 . The method of claim 14 , wherein the positions of the plurality of notches are aligned or not aligned with each other. 16 . 16 . The method of claim 14 , wherein the electronic component has a rectangular outline, and the corners thereof are not aligned with the notch. 17 . 17 . The method of claim 14 , wherein the ring body is rectangular, and the plurality of notches are respectively located on different ring edges of the ring body. 18 . 18 . The method of claim 17 , wherein the size of the notch on the single ring edge of the ring body is 1/10 of the size of the ring edge. 19 . 19. The method of claim 11, wherein the bonding layer comprises a first segment and a second segment separated from each other, so that the first segment and the second segment A plurality of gaps are formed therebetween, and the shape of the first section is different from the shape of the second section. 20. The method of claim 19, wherein an area of the carrier for contacting and bonding with the first section is the same as an area of the carrier for contacting and bonding with the second section .

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