CN114647272A - Trimming fuse reading circuit - Google Patents

Abstract

The invention discloses a trimming fuse reading circuit, which comprises: the trimming fuse state reading unit comprises a first branch and a second branch, wherein the first branch is connected with a power supply end through a first resistor, the second branch is connected with the power supply end through a trimming fuse, and the trimming fuse state reading unit also receives a fuse reading signal and is used for judging the fusing state of the trimming fuse based on the first resistor when the fuse reading signal is effective; and the bias current generating unit is used for providing bias current for the trimming fuse state reading unit. The trimming fuse reading circuit can ensure normal reading even in the state that the trimming fuse is not completely blown, and the reading of the blown state of the trimming fuse is less influenced by the power supply voltage.

Description

Trim the fuse read circuit

technical field

The invention relates to the technical field of chip trimming, in particular to a trimming fuse reading circuit.

Background technique

As the requirements for high performance indicators of integrated circuits are getting higher and higher, the requirements for high precision in chip design are becoming more and more obvious, especially for the design of high-speed and high-precision digital-to-analog converters, analog-to-digital converters, and high-precision reference source circuits. Due to unavoidable factors such as process errors, the capacitance and resistance values of the chips produced by the process factory have certain process errors, and these errors will directly affect the performance and even function of the circuit. In order to solve this kind of process error problem, before the chip is used normally, it is necessary to use a trimming technology to correct it, so that the circuit parameters are more accurate and consistent.

The fuse blowing trim adjustment is usually to use a voltage source (or current source) to blow the fuse, and change the fuse resistance value to achieve the purpose of trimming. Then, when the chip is powered on, the resistance value of the fuse is detected to determine whether the fuse is blown, and then the chip parameters are set within the specified range.

The existing read circuit for judging whether the trimming fuse is blown when the chip is powered on is shown in FIG. 1 , wherein Read is a fuse reading signal, which is usually valid when a high pulse is used. When the chip is powered on, the fuse read signal Read generates a high pulse. If the trimming fuse Fuse is not blown, the resistance value of the trimming fuse Fuse is very small. At this time, the voltage of the input terminal A of the inverter U0 is almost VDD, and the output of the output terminal OUT is always kept at a low level. When the trimming fuse Fuse is blown, its resistance is very large. When the high pulse of the fuse read signal Read comes, the voltage at point A is instantly low, and the output terminal OUT of the inverter U0 outputs a high pulse. , the chip latches the high pulse to determine that the fuse is blown.

However, with the upgrading of the process, when the trimming fuse is blown, it is often not completely blown, and the resistance of the trimming fuse that is not completely blown is in the order of several kΩ to several hundreds of kΩ. In the above circuit, if the driving ability of the NMOS transistor M0 is small, there may be a misjudgment that the trimming fuse Fuse is not blown; and if the driving ability of the NMOS transistor M0 is large, the excessive current may affect the power supply VDD, and the The power supply VDD is pulled low. In addition, the reading of the trim fuse Fuse is greatly affected by the voltage of the power supply VDD.

Therefore, it is necessary to provide an improved technical solution to overcome the above technical problems existing in the prior art.

SUMMARY OF THE INVENTION

In order to solve the above technical problems, the present invention provides a trimming fuse reading circuit, which can read the blown state based on the change of the resistance value of the trimming fuse relative to the fixed resistance value, ensuring the Normal reading can be performed even when the trim fuse is not completely blown, and the reading of the blown state of the trim fuse is less affected by the power supply voltage.

A trimming fuse reading circuit provided according to the present disclosure includes: a trimming fuse state reading unit, including a first branch and a second branch, the first branch is connected to a power terminal through a first resistor The second branch is connected to the power supply terminal through a trim fuse, and the trim fuse state reading unit also receives a fuse read signal, which is used to base on the fuse read signal when the fuse read signal is valid. The first resistor judges the blown state of the trimming fuse;

The bias current generating unit is connected to the trim fuse state reading unit, and is used for providing a bias current to the trim fuse state reading unit.

Optionally, the resistance value of the first resistor is greater than the resistance value of the trim fuse when it is not blown, and the resistance value of the first resistor is smaller than the resistance value of the trim fuse when the trim fuse is not completely blown.

Optionally, the bias current is less than a preset threshold.

Optionally, the trimming fuse state reading unit includes:

a first transistor, located on the first branch, with a source connected to the first resistor;

a second transistor, located on the second branch, and the source is connected to the trim fuse;

a first inverter, the input terminal is connected to the drain of the second transistor, and the output terminal outputs a state signal representing the blown state of the trimming fuse,

Wherein, the first transistor and the second transistor form a current mirror, and the first transistor, the second transistor and the third transistor are all PMOS transistors.

Optionally, a proportional relationship between the width-to-length ratio of the first transistor and the width-to-length ratio of the second transistor is n:1, where n is a positive number.

Optionally, the trimming fuse state reading unit further includes:

a third transistor, the source is connected to the power supply terminal, the gate of the third transistor receives the fuse read signal, the drain of the third transistor is connected to the drain of the second transistor,

Wherein, the third transistor is a PMOS transistor.

Optionally, the bias current generating unit includes:

The second inverter, the input terminal receives the fuse read signal;

a fourth transistor, the source of which is connected to the power supply terminal, and the gate of the fourth transistor is connected to the output terminal of the second inverter;

a fifth transistor, the drain of the fifth transistor is connected to the drain of the fourth transistor through the second resistor, the source of the fifth transistor is connected to the reference ground, and the gate of the fifth transistor is connected to the the output end of the second inverter is connected;

a sixth transistor, the drain of the sixth transistor is connected to the drain of the fifth transistor, the gate of the sixth transistor is connected to the drain of the sixth transistor, and the source of the sixth transistor connected to the reference ground;

a seventh transistor, the drain of the seventh transistor is connected to the drain of the first transistor, and the source of the seventh transistor is connected to the reference ground;

an eighth transistor, the drain of the eighth transistor is connected to the drain of the second transistor, the source of the eighth transistor is connected to the reference ground,

Wherein, the sixth transistor and the seventh transistor form a current mirror, and the sixth transistor and the eighth transistor form a current mirror, and the fourth transistor is a PMOS transistor, the fifth transistor, the The sixth transistor, the seventh transistor and the eighth transistor are all NMOS transistors.

Optionally, a proportional relationship between the width-to-length ratio of the seventh transistor and the width-to-length ratio of the eighth transistor is n:1.

Optionally, the bias current generating unit includes:

a first current source, connected between the drain of the first transistor and the reference ground, for providing a first bias current to the first branch;

The second current source is connected between the drain of the second transistor and the reference ground, and is used for providing a second bias current to the second branch.

Optionally, a proportional relationship between the first bias current and the second bias current is n:1.

Optionally, both the first bias current and the second bias current are smaller than a preset threshold.

Optionally, n is equal to one.

The beneficial effects of the present invention are: the trimming fuse reading circuit involved in the present disclosure judges the blown state of the trimming fuse based on the first resistance when the fuse reading signal is valid, that is, based on the resistance of the trimming fuse The fuse state can be read according to the change of the value relative to the fixed resistance value of the first resistor. Therefore, only by setting a reasonable resistance value of the first resistor, it can be realized when the resistance value of the trim fuse changes. The reading of its blown state avoids the influence of the driving ability of the transistor on the reading result, ensures that the normal reading can be performed even when the trimming fuse is not completely blown, and also reduces the power supply voltage. The effect of reading the blown state of the fuse.

On the other hand, the bias current in the trimming fuse reading circuit is set to be smaller than a preset threshold, which is also a safety threshold, and a bias current smaller than the safety threshold can avoid excessive current caused by The supply voltage is pulled low.

It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not intended to limit the invention.

Description of drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings.

1 shows a schematic diagram of a circuit structure of an existing trimming fuse reading circuit;

FIG. 2 shows a structural block diagram of a trimming fuse reading circuit provided according to an embodiment of the present disclosure;

FIG. 3 shows a schematic diagram of a circuit structure of a trim fuse reading circuit provided according to an embodiment of the present disclosure.

Detailed ways

In order to facilitate understanding of the present invention, the present invention will be described more fully hereinafter with reference to the related drawings. Preferred embodiments of the invention are shown in the accompanying drawings. However, the present invention may be embodied in different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that a thorough and complete understanding of the present disclosure is provided.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terms used herein in the description of the present invention are for the purpose of describing specific embodiments only, and are not intended to limit the present invention.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 shows a structural block diagram of a trim fuse read circuit provided according to an embodiment of the present disclosure.

As shown in FIG. 2 , in the present disclosure, the trim fuse reading circuit includes: a trim fuse state reading unit 100 and a bias current generating unit 200 .

Wherein, the trim fuse state reading unit 100 includes a first branch and a second branch. The first branch is connected to the power supply terminal VDD through the first resistor R1, and the second branch is connected to the power supply terminal VDD through the trimming fuse Fuse. The trimming fuse state reading unit 100 also receives the fuse reading signal. Read is used for judging and adjusting the blown state of the trim fuse Fuse based on the first resistor R1 when the fuse read signal Read is valid (for example, valid when it is a high pulse).

The bias current generating unit 200 is connected to the trim fuse state reading unit 100 for providing a bias current to the trim fuse state reading unit 100 .

In the present disclosure, the trimming fuse state reading unit 100 is specifically performed in the case that the fuse read signal Read is a high pulse period and the resistance value of the trimming fuse Fuse is smaller than the resistance value of the first resistor R1. The output terminal OUT outputs a state signal with a first level state (such as a high level state) indicating that the blown state of the trim fuse Fuse is not blown; or during the high pulse period of the fuse read signal Read, and When the resistance value of the trim fuse Fuse is greater than the resistance value of the first resistor R1 , the output terminal OUT outputs a state signal with a second level state indicating that the blown state of the trim fuse Fuse is blown.

That is to say, in the present disclosure, the resistance value of the first resistor R1 is set to be greater than the resistance value when the trimming fuse Fuse is not blown, and smaller than the resistance value when the trimming fuse Fuse is not completely blown, so that the When the resistance value of the trimming fuse Fuse changes, the blown state of the trimming fuse can be read, ensuring that the trimming fuse Fuse can be read normally even when the trimming fuse is not completely blown.

In order to further ensure the accuracy of the reading results, the difference between the resistance value of the first resistor R1 and the resistance value of the trimming fuse Fuse when it is not blown can also be set to be greater than the first threshold value, and the trimming fuse Fuse is not blown. The difference between the resistance value of the complete fuse and the resistance value of the first resistor R1 is greater than the second threshold value.

In the present disclosure, the bias current provided by the bias current generating unit 200 is smaller than a preset threshold. In this way, the operating current of the trimming fuse reading circuit can be set to a small current, so as to prevent the power supply voltage from being pulled down due to excessive current, and also reduce the influence of the power supply voltage on the reading of the blown state of the trimming fuse.

Optionally, the bias current generation unit 200 may also receive the fuse read signal Read, and then the bias current generation unit 200 is controlled by the fuse read signal Read to trim the fuse only when the fuse read signal Read is valid. The state reading unit 100 provides a bias current, thereby reducing the overall power consumption of the circuit and achieving the purpose of saving power consumption.

Referring to FIG. 3 , FIG. 3 shows a schematic diagram of a circuit structure of a trimming fuse reading circuit provided according to an embodiment of the present disclosure.

As shown in FIG. 3 , in the embodiment of the present disclosure, the trim fuse state reading unit 100 includes: a first transistor MP2 , a second transistor MP3 and a first inverter U2 .

The first transistor MP2 is located on the first branch of the trim fuse state reading unit 100, and the source of the first transistor MP2 is connected to the power terminal VDD through the first resistor R1. The second transistor MP3 is located on the second branch of the trim fuse state reading unit 100 , and the source of the second transistor MP3 is connected to the power terminal VDD through the trim fuse Fuse. The input end of the first inverter U2 is connected to the drain of the second transistor MP3, and the output end OUT of the first inverter U2 outputs a state signal representing the blown state of the trim fuse Fuse. The first transistor MP2 and the second transistor MP3 form a current mirror, that is, the drain of the first transistor MP2 is connected to the gate of the first transistor MP2, and the gate of the second transistor MP3 is connected to the gate of the first transistor MP2 pole connection.

Further, the ratio of the width to length ratio of the first transistor MP2 and the width to length ratio of the second transistor MP3 is n:1, where n is a positive number.

Optionally, in this embodiment, the first transistor MP2 and the second transistor MP3 are both PMOS transistors.

And, in the embodiment of the present disclosure, the bias current generating unit 200 includes: a second inverter U1, a fourth transistor MP0, a fifth transistor MN0, a sixth transistor MN1, a seventh transistor MN2, and an eighth transistor MN3.

The input terminal of the second inverter U1 receives the fuse read signal Read. The source of the fourth transistor MP0 is connected to the power supply terminal VDD, and the gate of the fourth transistor MP0 is connected to the output terminal of the second inverter U1. The drain of the fifth transistor MN0 is connected to the drain of the fourth transistor MP0 through the second resistor R0, the source of the fifth transistor MN0 is connected to the reference ground, and the gate of the fifth transistor MN0 is connected to the gate of the second inverter U1. output connection. The drain of the sixth transistor MN1 is connected to the drain of the fifth transistor MN0, the gate of the sixth transistor MN1 is connected to the drain of the sixth transistor MN1, and the source of the sixth transistor MN1 is connected to the reference ground. The drain of the seventh transistor MN2 is connected to the drain of the first transistor MP2, and the source of the seventh transistor MN2 is connected to the reference ground. The drain of the eighth transistor MN3 is connected to the drain of the second transistor MP3, and the source of the eighth transistor MN3 is connected to the reference ground. The sixth transistor MN1 and the seventh transistor MN2 form a current mirror, and the sixth transistor MN1 and the eighth transistor MN3 also form a current mirror.

Further, in this embodiment, the ratio between the width-length ratio of the sixth transistor MN1, the width-length ratio of the seventh transistor MN2, and the width-length ratio of the eighth transistor MN3 is m:n:1, where m is positive number.

Optionally, in this embodiment, the fourth transistor MP0 is a PMOS transistor. The fifth transistor MN0, the sixth transistor MN1, the seventh transistor MN2 and the eighth transistor MN3 are all NMOS transistors.

The specific working principle is as follows:

(1) When the fuse read signal Read is in the active state of the high pulse, the output end of the second inverter U1 generates a low pulse signal, and then controls the fourth transistor MP0 to turn on, and controls the fifth transistor MN0 to turn off, In turn, a current flowing through the sixth transistor MN1 is generated. At the same time, due to the current mirror relationship between the sixth transistor MN1 and the seventh transistor MN2 and the eighth transistor MN3, a corresponding proportion of the mirror current is generated in the drain of the seventh transistor MN2 and the drain of the eighth transistor MN3 respectively, as the trim fuse Bias currents of the first branch and the second branch of the wire state reading unit 100 . On the first branch of the trimming fuse state reading unit 100, based on the series relationship between the first resistor R1, the first transistor MP2 and the seventh transistor MN2, a drain with the seventh transistor MN2 will be generated on the first transistor MP2. The terminal currents are equal to each other, and based on the mirror relationship between the first transistor MP2 and the second transistor MP3, a corresponding mirror current is generated at the drain terminal of the second transistor MP3.

Based on the proportional relationship between the width-to-length ratio of the seventh transistor MN2 and the width-to-length ratio of the eighth transistor MN3, and the proportional relationship between the width-to-length ratio of the first transistor MP2 and the width-to-length ratio of the second transistor MP3, for ease of understanding, here n=1 is taken as an example for description, but it can be understood that the technical solutions of the present disclosure are also applicable to other values of n.

① In the case where the resistance of the first resistor R1 is equal to the resistance of the trim fuse Fuse, the current flowing through the second transistor MP3 on the second branch of the trim fuse state reading unit 100 affects the current of the circuit node B. The driving ability is the same as the driving ability of the current flowing through the eighth transistor MN3 to the circuit node B, so that the node B is in a balanced state.

② In the case where the resistance value of the trim fuse Fuse is smaller than the resistance value of the first resistor R1, the current flowing through the second transistor MP3 on the second branch of the trim fuse state reading unit 100 is adjusted to the circuit node B. The driving ability will be greater than the driving ability of the current flowing through the eighth transistor MN3 to the circuit node B, and then the voltage on the node B is pulled up to a high level state, so that the output terminal OUT of the first inverter U2 outputs a low level. , indicating that the trimming fuse Fuse is not blown at this time.

3. In the case where the resistance value of the trimming fuse Fuse is greater than the resistance value of the first resistor R1, the current flowing through the second transistor MP3 on the second branch of the trimming fuse state reading unit 100 is affected by the current flowing through the second transistor MP3 to the circuit node B. The driving capability will be smaller than the driving capability of the current flowing through the eighth transistor MN3 to the circuit node B, so that the voltage on the node B is pulled down to a low level state, so that the output terminal OUT of the first inverter U2 outputs a high level Pulse, indicating that the trim fuse Fuse is not completely blown or is blown at this time. After that, the chip can interpret that the trimming fuse Fuse is blown by latching the high-level pulse.

In other words, the first transistor MP2, the second transistor MP3, the seventh transistor MN2, and the eighth transistor MN3 in the present disclosure are configured to function as comparators, wherein the source of the first transistor MP2 and the source of the second transistor MP3 are respectively Corresponding to the two input terminals of the comparator, and based on the different resistance relationship between the first resistor R1 and the trimming fuse Fuse, different level signals can be generated at the drain of the second transistor MP3, that is, the output terminal of the corresponding comparator. That is to say, as long as a reasonable resistance value of the first resistor R1 is set in this embodiment, normal reading can be ensured even when the trimming fuse is not completely blown, and the power supply voltage is also reduced. The effect of trimming the blown state reading of fuses.

At the same time, (2) when the fuse read signal Read is in an invalid state of a low level, the output end of the second inverter U1 generates a high level signal, thereby controlling the fourth transistor MP0 to turn off and controlling the fifth transistor MN0 is turned on, and no bias current is generated at the drain of the seventh transistor MN2 and the drain of the eighth transistor MN3, so that the branches where MN1, MN, and MN3 are located do not consume current, and the static power consumption of the entire circuit is 0 . At this time, the trim fuse state reading unit 100 does not work, that is, the blown state reading of the trim fuse Fuse is not performed. In this way, the circuit can only read the blown state of the trim fuse Fuse when the fuse read signal Read is valid, thereby reducing the power consumption of the circuit.

It should be noted that, in general, the fuse read signal Read is only in the enabled state of the high pulse during a specific time when the chip is powered on, and is locked when the chip is not powered on or when the fuse state of the fuse is adjusted. After saving, the fuse read signal Read will remain in a low level state.

Based on the above description, the trimming fuse reading circuit involved in the present disclosure can output a low level state or a high pulse state based on different states of the trimming fuse Fuse when the fuse read signal Read is valid, and then through the high pulse state The latch function of the pulse state can quickly and effectively realize the state reading of the trimming fuse Fuse, which can ensure the accuracy of the reading result.

Further, in another embodiment of the present disclosure, the trim fuse state reading unit 100 further includes: a third transistor MP1. The source of the third transistor MP1 is connected to the power supply terminal VDD, the gate of the third transistor MP1 receives the fuse read signal Read, and the drain of the third transistor MP1 is connected to the drain of the second transistor MP3. The third transistor MP1 can also be controlled according to the fuse read signal Read to realize the circuit to read the blown state of the trim fuse Fuse only when the fuse read signal Read is valid.

On this basis, the bias current generating unit 200 can also be constructed by using the first current source and the second current source. Specifically, in order to connect the first current source between the drain of the first transistor MP2 and the reference ground, the first current source provides the first bias current to the first branch of the trim fuse state reading unit 100 . The second current source is connected between the drain of the second transistor MP3 and the reference ground, and the second current source provides a second bias current to the second branch of the trim fuse state reading unit 100 . Wherein, in this embodiment, the proportional relationship between the first bias current and the second bias current is n:1.

Then, based on the same principle as the trimming fuse state reading unit 100 in the foregoing embodiment, it can be realized that as long as a reasonable resistance value of the first resistor R1 is set, it can be ensured that the trimming fuse is not completely blown. Normal reading can be performed, and at the same time, reading can be performed only when the fuse read signal Read is valid.

Furthermore, in this embodiment, the first bias current and the second bias current are both smaller than the preset threshold.

In the present disclosure, the value of the above n may preferably be set to 1.

At the same time, it can be easily understood that, in other embodiments of the present disclosure, the solution of the trim fuse read unit 100 including the third transistor MP1 can also be simultaneously used in the trim fuse read circuit, and the solution based on the trim fuse read unit 100 can also be used in the trim fuse read circuit. The wire read signal Read further provides the bias current generating unit 200 scheme of the bias current, so as to realize the basic functions of the circuit, further reduce the power consumption of the circuit, and improve the stability and reliability of the circuit.

To sum up, the trimming fuse reading circuit involved in the present disclosure determines the blown state of the trimming fuse based on the first resistance when the fuse reading signal is valid, that is, based on the resistance value of the trimming fuse relative to the first resistance. The change of the fixed resistance value of a resistor can be used to read the fuse state. Therefore, only by setting a reasonable resistance value of the first resistor, the fuse state can be realized when the resistance value of the trim fuse changes. It avoids the influence of the driving ability of the transistor on the reading result, ensures normal reading even when the trim fuse is not completely blown, and also reduces the power supply voltage to the trim fuse. Impact of blown status read.

On the other hand, the bias current in the trimming fuse reading circuit is set to be smaller than a preset threshold, which is also a safety threshold, and a bias current smaller than the safety threshold can avoid excessive current caused by The supply voltage is pulled low.

It should be noted that the inclusion of the terms "comprising", "comprising" or any other variation thereof herein is intended to encompass non-exclusive inclusion, such that a process, method, article or apparatus comprising a series of elements includes not only those elements, but also other elements not expressly listed or inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element.

Finally, it should be noted that: obviously, the above-mentioned embodiments are only examples for clearly illustrating the present invention, and are not intended to limit the implementation manner. For those of ordinary skill in the art, changes or modifications in other different forms can also be made on the basis of the above description. There is no need and cannot be exhaustive of all implementations here. However, the obvious changes or changes derived from this are still within the protection scope of the present invention.

Claims (12)

1. A trimming fuse reading circuit, comprising: The trimming fuse state reading unit includes a first branch and a second branch, the first branch is connected to the power supply terminal through a first resistor, and the second branch is connected to the power supply terminal through the trimming fuse , the trimming fuse state reading unit further receives a fuse reading signal, for judging the blown state of the trimming fuse based on the first resistance when the fuse reading signal is valid; The bias current generating unit is connected to the trim fuse state reading unit, and is used for providing a bias current to the trim fuse state reading unit. 2 . The trim fuse reading circuit according to claim 1 , wherein the resistance value of the first resistor is greater than the resistance value of the trim fuse when the trim fuse is not blown, and the resistance value of the first resistor It is less than the resistance value when the trim fuse is not completely blown. 3. The trim fuse read circuit of claim 1, wherein the bias current is less than a preset threshold. 4. The trim fuse reading circuit according to claim 1, wherein the trim fuse state reading unit comprises: a first transistor, located on the first branch, with a source connected to the first resistor; a second transistor, located on the second branch, and the source is connected to the trim fuse; a first inverter, the input terminal is connected to the drain of the second transistor, and the output terminal outputs a state signal representing the blown state of the trimming fuse, Wherein, the first transistor and the second transistor form a current mirror, and the first transistor, the second transistor and the third transistor are all PMOS transistors. 5. The trimming fuse reading circuit according to claim 4, wherein the ratio of the width to length ratio of the first transistor to the width to length ratio of the second transistor is n:1, and n is a positive number . 6. The trim fuse reading circuit according to claim 5, wherein the trim fuse state reading unit further comprises: a third transistor, the source is connected to the power supply terminal, the gate of the third transistor receives the fuse read signal, the drain of the third transistor is connected to the drain of the second transistor, Wherein, the third transistor is a PMOS transistor. 7. The trim fuse reading circuit of claim 5, wherein the bias current generating unit comprises: The second inverter, the input terminal receives the fuse read signal; a fourth transistor, the source of which is connected to the power supply terminal, and the gate of the fourth transistor is connected to the output terminal of the second inverter; a fifth transistor, the drain of the fifth transistor is connected to the drain of the fourth transistor through the second resistor, the source of the fifth transistor is connected to the reference ground, and the gate of the fifth transistor is connected to the the output end of the second inverter is connected; a sixth transistor, the drain of the sixth transistor is connected to the drain of the fifth transistor, the gate of the sixth transistor is connected to the drain of the sixth transistor, and the source of the sixth transistor connected to the reference ground; a seventh transistor, the drain of the seventh transistor is connected to the drain of the first transistor, and the source of the seventh transistor is connected to the reference ground; an eighth transistor, the drain of the eighth transistor is connected to the drain of the second transistor, the source of the eighth transistor is connected to the reference ground, Wherein, the sixth transistor and the seventh transistor form a current mirror, and the sixth transistor and the eighth transistor form a current mirror, and the fourth transistor is a PMOS transistor, the fifth transistor, the The sixth transistor, the seventh transistor and the eighth transistor are all NMOS transistors. 8 . The trim fuse reading circuit according to claim 7 , wherein the ratio of the width to length ratio of the seventh transistor to the width to length ratio of the eighth transistor is n:1. 9 . 9. The trim fuse reading circuit of claim 6, wherein the bias current generating unit comprises: a first current source, connected between the drain of the first transistor and the reference ground, for providing a first bias current to the first branch; The second current source is connected between the drain of the second transistor and the reference ground, and is used for providing a second bias current to the second branch. 10 . The trim fuse reading circuit of claim 9 , wherein a ratio of the first bias current to the second bias current is n:1. 11 . 11. The trim fuse reading circuit of claim 9, wherein the first bias current and the second bias current are both smaller than a preset threshold. 12. The trim fuse read circuit of any one of claims 5, 8 and 10, wherein n is equal to one.

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