CN114646638A - Chip failure analysis and positioning method, device, equipment and storage medium - Google Patents

Abstract

The application provides a chip failure analysis positioning method, a device, equipment and a storage medium, wherein the chip failure analysis positioning method comprises the following steps: acquiring a structural image of a chip layer of a product to be analyzed, wherein the product to be analyzed comprises at least two layers of cores; constructing a three-dimensional image of the product to be analyzed according to the structural image of the chip layer; and carrying out failure positioning analysis on the product to be analyzed based on the three-dimensional image of the product to be analyzed. According to the method and the device, the three-dimensional image can be formed, so that the failure analysis can be efficiently performed on the whole chip based on the three-dimensional image.

Description

Chip failure analysis and positioning method, device, equipment and storage medium

technical field

The present application relates to the field of chip testing, and in particular, to a chip failure analysis and positioning method, apparatus, device, and storage medium.

Background technique

With the rapid development of semiconductor technology, integrated circuits are still one of the cores of communication, multimedia and computer technology. At present, the direction of the integrated circuit is towards the multi-layer connection structure, so there is a need for a method that can analyze and locate the failure of the chip with the multi-layer connection structure.

SUMMARY OF THE INVENTION

The purpose of the embodiments of the present application is to provide a chip failure analysis and positioning method, apparatus, device, and storage medium, which are used for failure analysis and positioning of a chip with a multi-layer structure.

To this end, a first aspect of the present application discloses a chip failure analysis and positioning method, the method comprising:

acquiring a structural image of a chip layer of a product to be analyzed, the product to be analyzed includes at least two chip layers;

Constructing a three-dimensional image of the product to be analyzed according to the structural image of the chip layer;

The failure location analysis is performed on the product to be analyzed based on the three-dimensional image of the product to be analyzed.

The chip failure analysis and positioning method of the present application obtains the structural image of the chip layer of the product to be analyzed, and then can construct a three-dimensional image of the product to be analyzed according to the structural image of the chip layer, so that the product to be analyzed can be analyzed based on the three-dimensional image of the product to be analyzed. Location analysis. Compared with the prior art, the embodiment of the present application can perform failure analysis and positioning of the entire chip through three-dimensional images, while the prior art can only perform partial analysis on each chip part cut by the focused ion beam one by one. This method has the advantages of failure analysis. The disadvantage of low positioning efficiency.

In the first aspect of the present application, as an optional implementation manner, the acquiring a structural image of the chip layer of the product to be analyzed includes:

Obtain a first image generated by a metallographic microscope or a scanning microscope after the product to be analyzed is unsealed by a laser;

Acquiring a second image generated by the metallographic microscope or the scanning microscope after each through-hole layer of the product to be analyzed is exposed.

In this optional embodiment, a first image generated after the product to be analyzed is unsealed by laser and a second image generated by exposure of each through-hole layer of the product to be analyzed can be obtained through a metallographic microscope or a scanning microscope .

In the first aspect of the present application, as an optional implementation manner, before the acquiring the first image generated by the metallographic microscope or the scanning microscope after the product to be analyzed is unsealed by the laser, the method further includes:

Cutting the ceramic shell of the product to be analyzed until the product to be analyzed has a chip part and the encapsulation epoxy glue disposed around the chip part;

Based on preset laser unsealing conditions, laser unsealing is performed on the encapsulated epoxy glue around the chip part until the unsealing reaches the bonding wire position of the product to be analyzed.

In this optional embodiment, by cutting the ceramic shell of the product to be analyzed, the product to be analyzed can be left with a chip part and the encapsulation epoxy glue disposed around the chip part, so as to The encapsulated epoxy adhesive around the chip part can be laser unsealed based on preset laser unsealing conditions until the unsealing reaches the bonding wire position of the product to be analyzed.

In the first aspect of the present application, as an optional implementation manner, the preset laser unsealing condition is that the power of the unsealing machine is 10-30 KV.

In the first aspect of the present application, as an optional implementation manner, before the cutting the ceramic shell of the product to be analyzed, the method further includes:

grinding the product to be analyzed until the metal cover of the product to be analyzed is opened;

After the metal cover of the product to be analyzed is opened, the product to be analyzed is encapsulated based on the encapsulating epoxy glue.

In this optional embodiment, by grinding the product to be analyzed, the metal cover of the product to be analyzed can be opened, so that the product to be analyzed can be encapsulated based on the encapsulation epoxy glue.

In the first aspect of the present application, as an optional implementation manner, after the product to be analyzed is encapsulated based on the encapsulation epoxy glue, and before the ceramic shell of the product to be analyzed is cut , the method also includes:

The product to be analyzed that has been encapsulated with the epoxy glue is put into an oven for baking and hardening, wherein the baking temperature is 80-200°, and the baking time is 4 hours.

In the first aspect of the present application, as an optional implementation manner, the product to be analyzed is a chip with 12 layers.

A second aspect of the present application discloses a chip failure analysis and positioning device, the device comprising:

The acquisition module is used to acquire the structural image of the chip layer of the product to be analyzed;

a three-dimensional building module for constructing a three-dimensional image of the product to be analyzed according to the structural image of the chip layer;

An analysis module, configured to perform failure location analysis on the product to be analyzed based on the three-dimensional image of the product to be analyzed.

The chip failure analysis and positioning device of the present application obtains the structural image of the chip layer of the product to be analyzed, and then can construct a three-dimensional image of the product to be analyzed according to the structural image of the chip layer, so that the product to be analyzed can be analyzed based on the three-dimensional image of the product to be analyzed. Location analysis. Compared with the prior art, the embodiment of the present application can perform failure analysis and positioning of the entire chip through three-dimensional images, while the prior art can only perform partial analysis on each chip part cut by the focused ion beam one by one. This method has the advantages of failure analysis. The disadvantage of low positioning efficiency.

A third aspect of the present application discloses a chip failure analysis and positioning device, which stores a memory with executable program codes;

a processor coupled to the memory;

The processor invokes the executable program code stored in the memory to execute the chip failure analysis and positioning method disclosed in the first aspect of the present application.

The chip failure analysis and positioning device of the present application obtains the structural image of the chip layer of the product to be analyzed, and then can construct a three-dimensional image of the product to be analyzed according to the structural image of the chip layer, so that the product to be analyzed can fail based on the three-dimensional image of the product to be analyzed. Location analysis. Compared with the prior art, the embodiment of the present application can perform failure analysis and positioning of the entire chip through three-dimensional images, while the prior art can only perform partial analysis on each chip part cut by the focused ion beam one by one. This method has the advantages of failure analysis. The disadvantage of low positioning efficiency.

A fourth aspect of the present application discloses a storage medium, wherein the storage medium stores computer instructions, and when the computer instructions are invoked, the computer instructions are used to execute the method for analyzing and locating the failure of an industrial chip according to the first aspect of the present application.

The storage medium of the present application obtains the structural image of the chip layer of the product to be analyzed, and then can construct a three-dimensional image of the product to be analyzed according to the structural image of the chip layer, so that failure location analysis of the product to be analyzed can be performed based on the three-dimensional image of the product to be analyzed. Compared with the prior art, the embodiment of the present application can perform failure analysis and positioning of the entire chip through three-dimensional images, while the prior art can only perform partial analysis on each chip part cut by the focused ion beam one by one. This method has the advantages of failure analysis. The disadvantage of low positioning efficiency.

Description of drawings

In order to explain the technical solutions of the embodiments of the present application more clearly, the following briefly introduces the accompanying drawings that need to be used in the embodiments of the present application. It should be understood that the following drawings only show some embodiments of the present application, therefore It should not be regarded as a limitation of the scope. For those of ordinary skill in the art, other related drawings can also be obtained from these drawings without any creative effort.

1 is a schematic flowchart of a chip failure analysis and positioning method disclosed in an embodiment of the present application;

2 is a schematic structural diagram of a chip failure analysis and positioning device disclosed in an embodiment of the present application;

FIG. 3 is a schematic structural diagram of a chip failure analysis and positioning device disclosed in an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application.

Example 1

Please refer to FIG. 1. FIG. 1 is a schematic flowchart of a chip failure analysis and positioning method disclosed in an embodiment of the present application. As shown in FIG. 1 , a chip failure analysis and positioning method disclosed in an embodiment of the present application includes the following steps:

101. Acquire a structural image of a chip layer of a product to be analyzed, where the product to be analyzed includes at least two chip layers;

102. Construct a three-dimensional image of the product to be analyzed according to the structural image of the chip layer;

103. Perform failure location analysis on the product to be analyzed based on the three-dimensional image of the product to be analyzed.

In the embodiment of the present application, optionally, the product to be analyzed includes three chip layers.

In the embodiment of the present application, the three-dimensional image of the product to be analyzed can fully reflect the structure and circuit direction of each chip layer of the product to be analyzed.

In the embodiment of the present application, the failure location analysis for the product to be analyzed includes analysis of the failure of the solder joints of the product to be analyzed.

To sum up, in the embodiment of the present application, by acquiring the structural image of the chip layer of the product to be analyzed, a three-dimensional image of the product to be analyzed can be constructed according to the structural image of the chip layer, so that the product to be analyzed can be invalidated based on the three-dimensional image of the product to be analyzed. Location analysis. Compared with the prior art, the embodiment of the present application can perform failure analysis and positioning of the entire chip through three-dimensional images, while the prior art can only perform partial analysis on each chip part cut by the focused ion beam one by one. This method has the advantages of failure analysis. The disadvantage of low positioning efficiency.

In this embodiment of the present application, as an optional implementation manner, step 101: obtaining a structural image of a chip layer of a product to be analyzed, including the following steps:

Obtain the first image generated by a metallographic microscope or scanning microscope after the product to be analyzed is opened by a laser;

Acquire a second image from a metallographic microscope or scanning microscope after each via layer of the product to be analyzed is exposed.

In this optional embodiment, a metallographic microscope or a scanning microscope can obtain a first image after the product to be analyzed is unsealed by laser, and a second image after each through-hole layer of the product to be analyzed is exposed .

In this optional embodiment, the first layer refers to the image of the metallographic microscope or scanning microscope when the product to be analyzed is opened by laser, and the second layer refers to the image of the product to be analyzed by the metallographic microscope or scanning microscope The imaging of each layer of the through-hole layer when exposed, wherein, in some scenarios, the first image and the second image generated by the metallographic microscope or the scanning microscope can also be enlarged, and then the enlarged first image and the second image can be enlarged. The images are captured to obtain the final first and second images.

In this optional embodiment, when the plate area of the product to be analyzed is larger than the observation range of the metallographic microscope or scanning microscope, the product to be analyzed can be observed multiple times through the metallographic microscope or scanning microscope, and the multiple observation results can be stitched together Layer the complete first image and second image.

In this optional embodiment, in order to expose the through-hole layer of the product to be analyzed, the surface of the product to be analyzed can be bombarded by the focused ion beam, so that the metal layer, dielectric layer, oxide layer and other materials in the product to be analyzed are bombarded by the focused ion beam. The removal is carried out, ultimately exposing the via layer of the product to be analyzed.

In the embodiment of the present application, as an optional implementation manner, before the step of obtaining the first image generated by the metallographic microscope or the scanning microscope after the product to be analyzed is unsealed by the laser, the method of the embodiment of the present application further includes the following steps :

Cutting the ceramic shell of the product to be analyzed, until the product to be analyzed has the chip part and the encapsulating epoxy glue arranged around the chip part;

Based on the preset laser unsealing conditions, laser unsealing is performed on the encapsulating epoxy glue around the chip part until the unsealing reaches the bonding wire position of the product to be analyzed.

In this optional embodiment, by cutting the ceramic shell of the product to be analyzed, the chip part of the product to be analyzed and the encapsulation epoxy glue disposed around the chip part can be left, and then the chip part can be sealed based on preset laser unsealing conditions. The encapsulating epoxy glue around the perimeter is laser unsealed until it reaches the bonding wire position of the product to be analyzed.

In this optional embodiment, optionally, the preset laser unsealing condition is that the power of the unsealing machine is 10-30 KV.

In the embodiment of the present application, as an optional implementation manner, before the step of cutting the ceramic shell of the product to be analyzed, the method of the embodiment of the present application further includes the following steps:

Grind the product to be analyzed until the metal cover of the product to be analyzed is opened;

When the metal cover of the product to be analyzed is opened, the product to be analyzed is encapsulated based on the encapsulating epoxy glue.

In the embodiment of the present application, by encapsulating the product to be analyzed, the structures in the chip can be protected during the process of cutting the chip.

In the embodiment of the present application, optionally, in order to grind the product to be analyzed, a grinder may be used to grind the product to be analyzed. For example, a grinding instruction is sent to the grinder, so that the grinder grinds the grinder according to the parameters carried by the grinding instruction. , until the metal cover of the product to be analyzed is opened.

In the embodiment of the present application, as an optional implementation manner, after the step of encapsulating the product to be analyzed based on the encapsulation epoxy glue, the step: before cutting the ceramic shell of the product to be analyzed, the method of the embodiment of the present application Also includes the following steps:

The product to be analyzed that has been encapsulated with the epoxy glue is placed in an oven to bake and harden, wherein the baking temperature is 80-200°, and the baking time is 4 hours.

In the embodiment of the present application, as an optional implementation manner, the product to be analyzed is a chip with 12 layers.

Embodiment 2

Please refer to FIG. 2 . FIG. 2 is a schematic structural diagram of a chip failure analysis and positioning device disclosed in an embodiment of the present application. As shown in FIG. 2 , a chip failure analysis and positioning device disclosed in an embodiment of the present application includes the following functional modules:

an acquisition module 201, configured to acquire a structural image of the chip layer of the product to be analyzed;

A three-dimensional construction module 202, configured to construct a three-dimensional image of the product to be analyzed according to the structural image of the chip layer;

The analysis module 203 is configured to analyze the failure location of the product to be analyzed based on the three-dimensional image of the product to be analyzed.

By acquiring the structural image of the chip layer of the product to be analyzed, the device of the embodiment of the present application can construct a three-dimensional image of the product to be analyzed according to the structural image of the chip layer, so as to perform failure location analysis on the product to be analyzed based on the three-dimensional image of the product to be analyzed. . Compared with the prior art, the embodiment of the present application can perform failure analysis and positioning of the entire chip through three-dimensional images, while the prior art can only perform partial analysis on each chip part cut by the focused ion beam one by one. This method has the advantages of failure analysis. The disadvantage of low positioning efficiency.

Embodiment 3

Please refer to FIG. 3 . FIG. 3 is a schematic structural diagram of a chip failure analysis and positioning device disclosed in an embodiment of the present application. As shown in FIG. 3 , a chip failure analysis and positioning device disclosed in an embodiment of the present application includes a memory 301 storing executable program codes;

a processor 302 coupled to the memory 301;

The processor 302 invokes the executable program code stored in the memory 301 to execute the chip failure analysis and positioning method disclosed in the first embodiment of the present application.

The chip failure analysis and positioning device according to the embodiment of the present application acquires the structural image of the chip layer of the product to be analyzed, and then can construct a three-dimensional image of the product to be analyzed according to the structural image of the chip layer, so that the product to be analyzed can be analyzed based on the three-dimensional image of the product to be analyzed. Perform failure location analysis. Compared with the prior art, the embodiment of the present application can perform failure analysis and positioning of the entire chip through three-dimensional images, while the prior art can only perform partial analysis on each chip part cut by the focused ion beam one by one. This method has the advantages of failure analysis. The disadvantage of low positioning efficiency.

Embodiment 4

The embodiment of the present application discloses a storage medium, where the storage medium stores computer instructions, and when the computer instructions are invoked, it is used to execute the method for analyzing and locating the failure of the industrial chip according to the first embodiment of the present application.

The storage medium of the embodiment of the present application obtains the structural image of the chip layer of the product to be analyzed, and then can construct a three-dimensional image of the product to be analyzed according to the structural image of the chip layer, so that the failure location of the product to be analyzed can be performed based on the three-dimensional image of the product to be analyzed. analyze. Compared with the prior art, the embodiment of the present application can perform failure analysis and positioning of the entire chip through three-dimensional images, while the prior art can only perform partial analysis on each chip part cut by the focused ion beam one by one. This method has the advantages of failure analysis. The disadvantage of low positioning efficiency.

In the embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The apparatus embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented. On the other hand, the shown or discussed mutual coupling or direct coupling or communication connection may be through some communication interfaces, indirect coupling or communication connection of devices or units, which may be in electrical, mechanical or other forms.

In addition, units described as separate components may or may not be physically separated, and components shown as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

Furthermore, each functional module in each embodiment of the present application may be integrated together to form an independent part, or each module may exist alone, or two or more modules may be integrated to form an independent part.

It should be noted that, if the functions are implemented in the form of software function modules and sold or used as independent products, they may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be embodied in the form of a software product in essence, or the part that contributes to the prior art or the part of the technical solution, and the computer software product is stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: U disk, removable hard disk, read-only memory (Read-Only Memory, ROM) random access memory (Random Access Memory, RAM), magnetic disk or optical disk and other media that can store program codes.

In this document, relational terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such existence between these entities or operations. The actual relationship or sequence.

The above descriptions are merely examples of the present application, and are not intended to limit the protection scope of the present application. For those skilled in the art, various modifications and changes may be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application shall be included within the protection scope of this application.

Claims (10)

1. A chip failure analysis positioning method is characterized by comprising the following steps:

acquiring a structural image of a chip layer of a product to be analyzed, wherein the product to be analyzed comprises at least two layers of cores;

constructing a three-dimensional image of the product to be analyzed according to the structural image of the chip layer;

and carrying out failure positioning analysis on the product to be analyzed based on the three-dimensional image of the product to be analyzed.

2. The method of claim 1, wherein said obtaining a structural image of a chip layer of a product to be analyzed comprises:

acquiring a first image generated by a metallographic microscope or a scanning microscope after the product to be analyzed is unsealed by laser;

and acquiring a second image generated by the metallographic microscope or the scanning microscope after each through hole layer of the product to be analyzed is exposed.

3. The method of claim 2, wherein prior to said obtaining a first image generated by a metallographic microscope or a scanning microscope after said product to be analyzed is laser unsealed, said method further comprises:

cutting the ceramic shell of the product to be analyzed until a chip part of the product to be analyzed is left and the encapsulating epoxy glue arranged around the chip part;

and laser unsealing the encapsulated epoxy glue around the chip part based on preset laser unsealing conditions until the encapsulated epoxy glue is unsealed to the bonding wire position of the product to be analyzed.

4. The method of claim 3, wherein the predetermined laser unsealing condition is. The power of the unsealing machine is 10-30 KV.

5. The method of claim 1, wherein prior to said cutting the ceramic shell of the product to be analyzed, the method further comprises:

grinding the product to be analyzed until a metal cover of the product to be analyzed is opened;

and when the metal cover of the product to be analyzed is opened, encapsulating the product to be analyzed based on the encapsulating epoxy glue.

6. The method of claim 1, wherein after the encapsulating the product to be analyzed based on the encapsulating epoxy glue and before the cutting the ceramic shell of the product to be analyzed, the method further comprises:

and placing the product to be analyzed, which is encapsulated with the epoxy glue, into an oven for baking and hardening, wherein the baking temperature is 80-200 degrees, and the baking time is 4 hours.

7. The method of claim 1, wherein the product to be analyzed is a chip having 12 layers.

8. A chip failure analysis positioning apparatus, the apparatus comprising:

the system comprises an acquisition module, a display module and a processing module, wherein the acquisition module is used for acquiring a structural image of a chip layer of a product to be analyzed, and the product to be analyzed comprises at least two layers of cores;

the three-dimensional construction module is used for constructing a three-dimensional image of the product to be analyzed according to the structural image of the chip layer;

and the analysis module is used for carrying out failure positioning analysis on the product to be analyzed based on the three-dimensional image of the product to be analyzed.

9. A chip failure analysis positioning apparatus, characterized by a memory storing executable program code;

a processor coupled with the memory;

the processor calls the executable program code stored in the memory to execute the chip failure analysis positioning method according to any one of claims 1 to 7.

10. A storage medium storing computer instructions which, when invoked, perform the method of any one of claims 1 to 7.

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