CN114639742B - A two-junction solar cell and a method for preparing the same - Google Patents
A two-junction solar cell and a method for preparing the same Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/30—Coatings
- H10F77/306—Coatings for devices having potential barriers
- H10F77/311—Coatings for devices having potential barriers for photovoltaic cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F10/00—Individual photovoltaic cells, e.g. solar cells
- H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
- H10F10/14—Photovoltaic cells having only PN homojunction potential barriers
- H10F10/142—Photovoltaic cells having only PN homojunction potential barriers comprising multiple PN homojunctions, e.g. tandem cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F71/00—Manufacture or treatment of devices covered by this subclass
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F71/00—Manufacture or treatment of devices covered by this subclass
- H10F71/129—Passivating
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- H—ELECTRICITY
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- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F71/00—Manufacture or treatment of devices covered by this subclass
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/20—Electrodes
- H10F77/206—Electrodes for devices having potential barriers
- H10F77/211—Electrodes for devices having potential barriers for photovoltaic cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/544—Solar cells from Group III-V materials
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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Abstract
本发明实施例提供了一种两结太阳能电池及其制备方法，该电池基于N型晶硅衬底制备而成，在正面上由内向外依次制备有包括扩散P型层、第一隧穿薄膜层、第一P型半导体层、第一钝化层、第一透明导电膜层的晶硅太阳能电池单元，还包括由第一N型半导体层、第二隧穿薄膜层、第二P型半导体层和第二透明导电膜层构成的薄膜太阳能电池单元，两种太阳能电池单元通过第一金属电极串联，且整体太阳能电池通过第二金属电极和第三金属电极实现与外电路连接。由于薄膜太阳能电池单元能够将晶硅太阳能电池不能吸收的太阳光予以利用，因此两者结合能够有效提高整体太阳能转换效率，从而解决了采用单结隧穿氧化层钝化金属结构的太阳能电池的转换效率较低的问题。
The embodiment of the present invention provides a two-junction solar cell and a preparation method thereof. The cell is prepared based on an N-type crystalline silicon substrate, and a crystalline silicon solar cell unit including a diffused P-type layer, a first tunneling thin film layer, a first P-type semiconductor layer, a first passivation layer, and a first transparent conductive film layer is prepared on the front side in sequence from the inside to the outside. It also includes a thin-film solar cell unit composed of a first N-type semiconductor layer, a second tunneling thin film layer, a second P-type semiconductor layer, and a second transparent conductive film layer. The two solar cell units are connected in series through a first metal electrode, and the entire solar cell is connected to an external circuit through a second metal electrode and a third metal electrode. Since the thin-film solar cell unit can utilize sunlight that cannot be absorbed by the crystalline silicon solar cell, the combination of the two can effectively improve the overall solar energy conversion efficiency, thereby solving the problem of low conversion efficiency of solar cells using a single-junction tunneling oxide layer passivated metal structure.
Description
Technical Field
The invention relates to the technical field of photovoltaics, in particular to a two-junction solar cell and a preparation method thereof.
Background
Crystalline silicon solar cells are the most technically mature, most widely used solar cells, with a proportion of more than 90% in the photovoltaic market, and will dominate for a considerable time in the future. Meanwhile, since the crystalline silicon solar cell is only sensitive to light in the visible 300-1100nm wave band, photo-generated current can be generated and output to an external circuit, which indicates that the crystalline silicon solar cell cannot be utilized for light in the wave band smaller than 300nm or larger than 1100nm, so that the conversion efficiency of the solar cell adopting the single-junction tunneling oxide passivation metal structure is lower at present.
Disclosure of Invention
In view of the above, the present invention provides a two-junction solar cell and a method for manufacturing the same, which solves the problem of low conversion efficiency of a solar cell employing a single-junction tunnel oxide passivation metal structure.
In order to solve the problems, the invention discloses a two-junction solar cell, which comprises an N-type crystalline silicon substrate, wherein the crystalline silicon substrate comprises a front surface and a back surface, and the two-junction solar cell comprises:
a diffusion P-type layer, a first tunneling thin film layer, a first P-type semiconductor layer, a first passivation layer, a first transparent conductive film layer, a first N-type semiconductor layer, a second tunneling thin film layer, a second P-type semiconductor layer, a second transparent conductive film layer and a first anti-reflection layer are sequentially prepared on the front surface from inside to outside;
A first metal electrode is prepared between the first P-type semiconductor layer and the first transparent conductive film layer, a second metal electrode is prepared on the second transparent conductive film layer, and the second metal electrode penetrates through the first anti-reflection layer outwards;
the back surface is sequentially provided with a third tunneling film layer, a second N-type semiconductor layer, a second passivation layer and a second anti-reflection layer from inside to outside;
And a third metal electrode connected with the second N-type semiconductor layer is prepared on the second N-type semiconductor layer, and the third metal electrode penetrates through the second passivation layer and the second anti-reflection layer outwards.
Optionally, the dopant of the diffusion P-type layer is boron, the highest doping concentration of the dopant is 10 18~1020cm-3, and the diffusion junction depth at the position where the boron concentration is 10 17cm-3 is 0.2-0.8 μm.
Optionally, the first tunneling film layer is a mixture film, an oxide film, a nitride film or an oxynitride film of group IVA element, or is a metal oxide film;
The thickness of the first tunneling film layer is 1-5 nm.
Optionally, the first P-type semiconductor layer and the second P-type semiconductor layer are polycrystalline boron-doped films or amorphous boron-doped films of group IVA elements or compound strongly conductive polar P-type semiconductor films of group IIA elements or group VIA elements;
The thickness of the first P-type semiconductor layer or the second P-type semiconductor layer is 15-150 nm.
Optionally, the first passivation layer comprises a lamination of one or more film layers of an alumina film, a silica film, an intrinsic film and a mixture film of P-type heavily doped amorphous IVA group element;
The thickness of the first passivation layer is 3-5nm.
Optionally, the first N-type semiconductor layer and the second N-type semiconductor layer are polycrystalline doped films or amorphous phosphorus doped films based on group IVA element mixtures, or are strong-conductivity polar N-type semiconductor films of group IIA elements or group VIA elements;
The thickness of the first N-type semiconductor layer and the second N-type semiconductor layer is 15-150 nm.
Optionally, the second passivation layer comprises a silicon nitride film layer, a silicon oxide film, an intrinsic film and a single-layer film material or a lamination of multiple film layers in the N-type heavily doped amorphous IVA group element film;
the thickness of the second passivation layer is 3-15 nm.
Optionally, the thicknesses of the first transparent conductive film layer and the second transparent conductive film layer are 60-100 nm.
Also provided is a method for preparing the two-junction solar cell, the index method comprising the steps of:
Cleaning and texturing two sides of the N-type crystalline silicon substrate;
performing boron diffusion treatment on the front surface of the N-type crystalline silicon substrate to form the diffusion P-type layer;
carrying out back-side coiling and expanding treatment on borosilicate glass on the front side and the back side of the N-type crystalline silicon substrate;
Respectively carrying out tunneling layer growth operation on the front side and the back side of the N-type crystalline silicon substrate to obtain the first tunneling film layer and the third tunneling film layer;
preparing the first P-type semiconductor layer on the first tunneling film layer, and preparing the second N-type semiconductor layer on the third tunneling film layer;
Depositing and annealing the N-type crystalline silicon substrate to obtain the first passivation layer and the second passivation layer;
Preparing a second anti-reflection layer on the second passivation layer;
preparing the first transparent conductive film layer on the first passivation layer;
preparing the first metal electrode and the second metal electrode on the first transparent conductive grinding layer in a screen printing mode, and preparing the third metal electrode on the second anti-reflection layer, wherein the first metal electrode penetrates through the first passivation layer and then is in deep contact with the first P-type semiconductor layer;
and sequentially preparing the first N-type semiconductor layer, the second tunneling film layer, the second P-type semiconductor layer, the second transparent conductive film layer and the first anti-reflection layer on the first transparent conductive film layer.
According to the technical scheme, the invention provides a two-junction solar cell and a preparation method thereof, the solar cell is prepared based on an N-type crystalline silicon substrate, crystalline silicon solar cells comprising a diffusion P-type layer, a first tunneling thin film layer, a first P-type semiconductor layer, a first passivation layer and a first transparent conductive film layer are sequentially prepared from inside to outside on the front surface, the solar cell also comprises a thin film solar cell consisting of the first N-type semiconductor layer, a second tunneling thin film layer, a second P-type semiconductor layer and a second transparent conductive film layer, the two solar cells are connected in series through a first metal electrode, and the whole solar cell is connected with an external circuit through a second metal electrode and a third metal electrode. The thin film solar cell unit can utilize sunlight which cannot be absorbed by the crystalline silicon solar cell, so that the solar cell unit and the crystalline silicon solar cell unit can be combined to effectively improve the overall solar energy conversion efficiency, and the problem that the conversion efficiency of the solar cell adopting the single-junction tunneling oxide passivation metal structure is lower is solved.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a cross-sectional view of a two-junction solar cell according to an embodiment of the present application;
FIG. 2 is a flow chart of a method of preparation according to an embodiment of the present application;
FIG. 2a is a cross-sectional view of a two-junction solar cell according to an embodiment of the present application during the fabrication process;
FIG. 2b is a cross-sectional view of a two-junction solar cell according to an embodiment of the present application during fabrication;
FIG. 2c is a cross-sectional view of a two-junction solar cell according to an embodiment of the present application during fabrication;
FIG. 2d is a cross-sectional view of a two-junction solar cell according to an embodiment of the present application during the fabrication process;
FIG. 2e is a cross-sectional view of a two-junction solar cell according to an embodiment of the present application during fabrication;
FIG. 2f is a cross-sectional view of a two-junction solar cell according to an embodiment of the present application during fabrication;
FIG. 2g is a cross-sectional view of a two-junction solar cell according to an embodiment of the present application during fabrication;
FIG. 2h is a cross-sectional view of a two-junction solar cell according to an embodiment of the present application during the fabrication process;
FIG. 2i is a cross-sectional view of a two-junction solar cell according to an embodiment of the present application during the fabrication process;
FIG. 2j is a cross-sectional view of a two-junction solar cell according to an embodiment of the present application during fabrication;
FIG. 2k is a cross-sectional view of a two-junction solar cell according to an embodiment of the present application during fabrication;
FIG. 2l is a cross-sectional view of a two-junction solar cell according to an embodiment of the present application during fabrication;
FIG. 2m is a cross-sectional view of a two-junction solar cell according to an embodiment of the present application during fabrication;
FIG. 2n is a cross-sectional view of a two-junction solar cell according to an embodiment of the present application during fabrication;
fig. 2o is a cross-sectional view of a two-junction solar cell according to an embodiment of the application during the fabrication process.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
Fig. 1 is a cross-sectional view of a two-junction solar cell according to an embodiment of the application.
Referring to fig. 1, the two-junction solar cell provided in this embodiment is a power generating element of a solar module, and is manufactured based on an N-type crystalline silicon substrate 1, which includes a front surface and a back surface, wherein the front surface and the back surface are relative concepts, i.e., one surface facing sunlight is the front surface of the crystalline silicon substrate, and the other surface is the back surface.
A diffusion P-type layer 1', a first tunneling film layer 2, a first P-type semiconductor layer 3, a first passivation layer 5, a first transparent conductive film layer 9, a first N-type semiconductor layer 10, a second tunneling film layer 11, a second P-type semiconductor layer 12, a second transparent conductive film layer 13 and a first anti-reflection layer 14 are sequentially prepared from inside to outside on the front surface of the N-type crystalline silicon substrate.
A first metal electrode 7 is prepared between the first P-type semiconductor layer 3 and the first transparent conductive film layer 9, and a second metal electrode 14 is prepared on the second transparent conductive film layer, the second metal electrode penetrating the first anti-reflective layer outwards.
A third tunneling thin film layer 2', a second N-type semiconductor layer 4, a second passivation layer 6 and a second anti-reflection layer 15 are sequentially prepared from inside to outside on the back surface of the N-type crystalline silicon substrate. A third metal electrode 8 connected to the second N-type semiconductor layer is prepared on the second N-type semiconductor layer, the third metal electrode penetrating the second passivation layer and the second anti-reflection layer outwards.
The second metal electrode and the third metal electrode form an external electrode of the battery and are used for connecting an external circuit so as to output a circuit generated by the solar battery to the external circuit. Or the solar cells are connected through the second metal electrode and the third metal electrode when being connected in series-parallel.
Wherein the dopant of the diffusion P-type layer is boron, the highest doping concentration of the dopant is 1018-1020 cm < -3 >, and the diffusion junction depth at the position of 1017cm < -3 > is 0.2-0.8 mu m.
The first tunneling film layer is a film of IVA group element, an oxide film, a nitride film or an oxynitride film, or a mixture film of various IVA group elements, and can also be a metal oxide film; the thickness of the first tunneling film layer is 1-5 nm.
The first P-type semiconductor layer and the second P-type semiconductor layer are polycrystalline boron-doped films or amorphous boron-doped films of IVA group elements or compound strong-conductivity polar P-type semiconductor films of IIA group elements or VIA group elements; the thickness of the first P-type semiconductor layer or the second P-type semiconductor layer is 15-150 nm. The thicknesses of the first P-type semiconductor layer and the second P-type semiconductor layer may be the same or different.
The first passivation layer is an alumina film, a silicon oxide film, an intrinsic film, a mixture film of P-type heavily doped amorphous IVA group elements, or a laminated film formed by laminating one or more film layers. The thickness of the first passivation layer is 3-5 nm.
The first N-type semiconductor layer and the second N-type semiconductor layer are polycrystalline doped films or amorphous phosphorus doped films based on IVA group element mixtures or compound strong-conductivity polar N-type semiconductor films of IIA group elements or VIA group elements; the thickness of the first N-type semiconductor layer and the second N-type semiconductor layer is 15-150 nm. The thickness of the two N-type semiconductor layers may be the same or different.
The second passivation layer is a silicon nitride film layer, a silicon oxide film, an intrinsic film or an N-type heavily doped amorphous group IVA element film, and can also be a laminated film comprising the above films. The thickness of the second passivation layer is 3-15 nm. The thickness of the first transparent conductive film layer and the second transparent conductive film layer is 60-100 nm.
According to the technical scheme, the two-junction solar cell is prepared based on an N-type crystalline silicon substrate, crystalline silicon solar cells comprising a diffusion P-type layer, a first tunneling thin film layer, a first P-type semiconductor layer, a first passivation layer and a first transparent conductive film layer are sequentially prepared from inside to outside on the front surface, the two-junction solar cell further comprises a thin film solar cell comprising a first N-type semiconductor layer, a second tunneling thin film layer, a second P-type semiconductor layer and a second transparent conductive film layer, the two solar cells are connected in series through a first metal electrode, and the whole solar cell is connected with an external circuit through a second metal electrode and a third metal electrode. The thin film solar cell unit can utilize sunlight which cannot be absorbed by the crystalline silicon solar cell, so that the solar cell unit and the crystalline silicon solar cell unit can be combined to effectively improve the overall solar energy conversion efficiency, and the problem that the conversion efficiency of the solar cell adopting the single-junction tunneling oxide passivation metal structure is lower is solved.
Example two
FIG. 2 is a flow chart of a method of making an embodiment of the present application.
Referring to fig. 1, the present embodiment provides a preparation method for preparing the two-junction solar cell provided in the above embodiment, which specifically includes the following steps:
S1, cleaning and texturing two sides of an N-type crystalline silicon substrate.
The selected N-type crystalline silicon substrate 1 has the resistivity of 0.5-3 omega cm and the size of 158.78 x 158.75mm 2 monocrystalline silicon wafer, and the two sides of the monocrystalline silicon wafer are cleaned, the damaged layer is removed, and the texture is formed, and a random pyramid structure is formed on the front side and the back side of the monocrystalline silicon wafer, as shown in figure 2 a.
S2, performing boron diffusion treatment on the front surface of the N-type crystalline silicon substrate to form a diffusion P-type layer.
And (3) performing boron diffusion on the front surface of the N-type crystalline silicon substrate subjected to the texturing by using a boron diffusion furnace to form a P-type layer 1', thereby obtaining a pn junction, wherein the highest doping concentration of the P-type layer is 10 20cm-3, and the diffusion junction depth at the position of 10 17cm-3 of boron concentration is 0.5 mu m as shown in figure 2 b.
S3, carrying out back-side winding and expanding treatment on borosilicate glass on the front side and the back side of the N-type crystalline silicon substrate.
Borosilicate glass on two sides of the N-type crystalline silicon substrate is removed through a cleaning machine, and back surface winding and expanding treatment is carried out, wherein the effect is shown in figure 2 c.
S4, preparing a first tunneling film layer and a third tunneling film layer.
The ultraviolet ozone treatment on the front and back surfaces of the silicon wafer is realized by using a turnover mechanism in the blanking section of the cleaning machine table, the growth of an ultrathin tunneling oxide layer is realized, a first tunneling film layer 2 is obtained on the front surface, and a third tunneling film layer 2' is obtained on the back surface, and the thickness of the two tunneling film layers is 1-3nm as shown in fig. 2 d. In fact, the two tunneling thin film layers are continuous at the edge of the crystalline silicon substrate.
S5, preparing a first P-type semiconductor layer and a second N-type semiconductor layer.
Preparing a first tunneling film layer and a third tunneling film layer, depositing boron-doped amorphous silicon on the front surface of the first tunneling film layer and the third tunneling film layer by using anti-winding plating carrier plate type reaction magnetron sputtering equipment, and depositing phosphorus-doped amorphous silicon on the back surface of the first tunneling film layer, wherein the thickness of the first tunneling film layer and the third tunneling film layer is 70nm and the thickness of the third tunneling film layer are 120nm respectively, and the doping concentration of the third tunneling film layer is 6 respectively10 20/cm3 And 10 21/cm3; and then, carrying out high-temperature annealing treatment for 20min at 890 ℃ on the battery piece through a tubular annealing furnace, so that a first P-type semiconductor layer 3is formed on the first tunneling film layer doped on the front surface, and a second N-type semiconductor layer 4 is formed on the third tunneling film layer on the back surface, wherein the structure of the second N-type semiconductor layer is shown in figure 2 e.
And S6, carrying out deposition and annealing to obtain a first passivation layer and a second passivation layer.
After the preparation of the first P-type semiconductor layer and the second N-type semiconductor layer is completed, a 3nm aluminum oxide film is deposited on the front surface of the first P-type semiconductor layer and the second N-type semiconductor layer by an atomic layer deposition device to form a first passivation layer 5, and a 3nm silicon oxide film is deposited on the back surface of the first P-type semiconductor layer and the second passivation layer 6, wherein the structure of the second passivation layer is shown in fig. 2 f.
S7, preparing a second anti-reflection layer on the second passivation layer.
After the preparation of the passivation layer is completed, a laminated film of silicon nitride and silicon oxide is deposited on the back surface of the material through a tube PECVC, so as to form a second anti-reflection layer 15, the thickness of which can be actually regulated according to the characteristics of a single-sided or double-sided battery, and the structure of which is shown in fig. 2 g.
S8, preparing a first transparent conductive film layer on the first passivation layer.
An 80nm indium tin titanium oxide (ITO) transparent conductive film is deposited on the first passivation layer through a winding-proof plating carrier plate type reaction magnetron sputtering device to serve as a first transparent conductive film layer 9, the structure of the first transparent conductive film layer is shown in fig. 2h, and the sheet resistance of the first transparent conductive film layer is 20 omega/square.
S9, preparing a first metal electrode and a third metal electrode.
Preparing the first metal electrode 7 and the third metal electrode 8 on the first transparent conductive grinding layer by screen printing, as shown in fig. 2 i; the first metal electrode needs to ensure that the ITO film layer 9 and the aluminum oxide film layer 5 can be burnt out, the first metal electrode is in contact with the surface of the boron-doped polysilicon 3 at a certain depth, the height of a grid line exposed out of the ITO film layer 9 is less than 5nm, and the exposed electrode is a silver electrode.
S10, sequentially preparing a first N-type semiconductor layer, the second tunneling film layer, a second P-type semiconductor layer, the second transparent conductive film layer and the first anti-reflection layer.
A first N-type semiconductor layer 10 is formed by depositing a phosphorus doped hydrogenated amorphous silicon film on the front surface of a battery piece by using an anti-winding plating carrier plate type plasma enhanced chemical vapor deposition device, and the thickness of the first N-type semiconductor layer is 20nm, and the phosphorus doping concentration is 3 as shown in figure 2j10 21/cm3, The deposition temperature is 200-220 ℃.
Depositing an intrinsic hydrogenated amorphous silicon film on the front surface of the battery piece by using anti-winding plating carrier plate type plasma enhanced chemical vapor deposition equipment to form a second tunneling film layer 11, wherein the thickness of the second tunneling film layer is 5nm, and the deposition temperature is 200-220 ℃ as shown in fig. 2 k;
Depositing a boron doped amorphous silicon film on the front surface of the battery piece by using anti-winding plating carrier plate type plasma enhanced chemical vapor deposition equipment to form a second P type semiconductor layer 12, wherein the thickness of the second P type semiconductor layer is 20nm, and the boron doping concentration is 8 as shown in figure 2l 10 20/cm3, Wherein the deposition temperature is 200-220 ℃;
And (3) depositing an ITO film, namely a second transparent conductive film layer 13 on the front surface of the battery piece by using anti-winding plating carrier plate type reaction magnetron sputtering equipment, wherein the thickness of the second transparent conductive film layer is 100nm, the sheet resistance is 40 omega/square, and the deposition temperature is room temperature as shown in figure 2 m.
Finally, the front surface of the battery piece is subjected to low-temperature silver paste printing electrode by using a screen printing mode, so as to obtain a second metal electrode 14, and the curing temperature is lower than 180 ℃ as shown in fig. 2 o.
The back edge of the battery piece can be cut by a laser scanning mode (as shown in fig. 2 n) so as to expose the bare silicon piece, and the process can be an optional process according to actual conditions.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
It will be apparent to those skilled in the art that embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the invention may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or terminal device that comprises the element.
The foregoing has outlined rather broadly the more detailed description of the invention in order that the detailed description of the invention that follows may be better understood, and in order that the present principles and embodiments may be better understood; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
Claims (7)
1. A two-junction solar cell comprising an N-type crystalline silicon substrate comprising a front side and a back side, wherein:
a diffusion P-type layer, a first tunneling thin film layer, a first P-type semiconductor layer, a first passivation layer, a first transparent conductive film layer, a first N-type semiconductor layer, a second tunneling thin film layer, a second P-type semiconductor layer, a second transparent conductive film layer and a first anti-reflection layer are sequentially prepared on the front surface from inside to outside;
A first metal electrode is prepared between the first P-type semiconductor layer and the first transparent conductive film layer, a second metal electrode is prepared on the second transparent conductive film layer, and the second metal electrode penetrates through the first anti-reflection layer outwards;
A third tunneling film layer, a second N-type semiconductor layer, a second passivation layer and a second anti-reflection layer are sequentially prepared on the back surface from inside to outside;
A third metal electrode connected with the second N-type semiconductor layer is prepared on the second N-type semiconductor layer, and the third metal electrode penetrates through the second passivation layer and the second anti-reflection layer outwards;
the first tunneling film layer is a mixed film, an oxide film, a nitride film or an oxynitride film of IVA group elements or is a metal oxide film;
the thickness of the first tunneling film layer is 1-5 nm;
The first P-type semiconductor layer and the second P-type semiconductor layer are polycrystalline boron-doped films or amorphous boron-doped films of IVA group elements or compound strong-conductivity polar P-type semiconductor films of IIA group elements or VIA group elements;
The thickness of the first P-type semiconductor layer or the second P-type semiconductor layer is 15-150 nm.
2. The two-junction solar cell according to claim 1, wherein the dopant of the diffusion P-type layer is boron, the highest doping concentration of the dopant is 1018-10200 cm "3, and the diffusion junction depth at 1017 cm" 3 is 0.2-0.8 μm.
3. The two-junction solar cell of claim 1, wherein the first passivation layer comprises a stack of one or more film layers of a mixture of an aluminum oxide film, a silicon oxide film, an intrinsic film, and a P-type heavily doped amorphous group IVA element;
The thickness of the first passivation layer is 3-5nm.
4. The two-junction solar cell according to claim 1, wherein the first N-type semiconductor layer and the second N-type semiconductor layer are polycrystalline doped thin films or amorphous phosphorus doped thin films based on group IVA element mixtures or compound strongly conductive polar N-type semiconductor thin films of group IIA elements or group VIA elements;
The thickness of the first N-type semiconductor layer and the second N-type semiconductor layer is 15-150 nm.
5. The two-junction solar cell according to claim 1, wherein the second passivation layer comprises a single layer film or a stack of multiple layers of film materials of silicon nitride film, silicon oxide film, intrinsic film and N-type heavily doped amorphous group IVA element film;
the thickness of the second passivation layer is 3-15 nm.
6. The two-junction solar cell according to claim 1, wherein the thickness of the first transparent conductive film layer and the second transparent conductive film layer is 60-100 nm.
7. A method for preparing the two-junction solar cell according to any one of claims 1 to 6, comprising the steps of:
Cleaning and texturing two sides of the N-type crystalline silicon substrate;
performing boron diffusion treatment on the front surface of the N-type crystalline silicon substrate to form the diffusion P-type layer;
carrying out back-side coiling and expanding treatment on borosilicate glass on the front side and the back side of the N-type crystalline silicon substrate;
Respectively carrying out tunneling layer growth operation on the front side and the back side of the N-type crystalline silicon substrate to obtain the first tunneling film layer and the third tunneling film layer;
preparing the first P-type semiconductor layer on the first tunneling film layer, and preparing the second N-type semiconductor layer on the third tunneling film layer;
Depositing and annealing the N-type crystalline silicon substrate to obtain the first passivation layer and the second passivation layer;
Preparing a second anti-reflection layer on the second passivation layer;
preparing the first transparent conductive film layer on the first passivation layer;
preparing the first metal electrode and the second metal electrode on the first transparent conductive grinding layer in a screen printing mode, and preparing the third metal electrode on the second anti-reflection layer, wherein the first metal electrode penetrates through the first passivation layer and then is in deep contact with the first P-type semiconductor layer;
and sequentially preparing the first N-type semiconductor layer, the second tunneling film layer, the second P-type semiconductor layer, the second transparent conductive film layer and the first anti-reflection layer on the first transparent conductive film layer.
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