CN114639361B

CN114639361B - Gate driving circuit and display panel

Info

Publication number: CN114639361B
Application number: CN202210447001.5A
Authority: CN
Inventors: 卢昭阳; 康报虹
Original assignee: HKC Co Ltd; Changsha HKC Optoelectronics Co Ltd
Current assignee: HKC Co Ltd; Changsha HKC Optoelectronics Co Ltd
Priority date: 2022-04-26
Filing date: 2022-04-26
Publication date: 2023-04-28
Anticipated expiration: 2042-04-26
Also published as: CN114639361A

Abstract

The application provides a gate drive circuit and display panel, gate drive circuit is including arranging in proper order and the M level gate drive unit that the cascade set up, M level gate drive unit and M group pixel unit one-to-one. Each stage of grid driving unit comprises (N+1) sub driving units, M is more than or equal to 1, and N is more than or equal to 2. The (n+1) sub-driving units comprise a main driving unit and N sub-driving units, the main driving unit corresponds to the first row of pixel units of the corresponding group of pixel units, and the main driving unit is used for responding to the trigger signal corresponding to the gate driving unit where the main driving unit is positioned and the first clock signal corresponding to the gate driving unit to output corresponding scanning signals. The auxiliary driving units are used for responding to the corresponding clock signals and outputting corresponding scanning signals, and at least 2 auxiliary driving units are directly and electrically connected with the main control nodes of the main driving units. Because a plurality of sub-driving units share one trigger signal, the circuit structure can be simplified, and the ultra-narrow frame design is facilitated.

Description

Gate driving circuit and display panel

Technical Field

The application relates to the technical field of display, in particular to a gate driving circuit and a display panel.

Background

Currently, an LCD (Liquid Crystal Display ) is a mainstream display widely used in various industries, and the LCD has advantages of thin profile, light weight, and the like.

In order to reduce the production cost, the conventional liquid crystal display panel part adopts a GDL (Gate Driver less) circuit driving technology, that is, a Gate driving circuit of a horizontal scanning line is manufactured at the periphery of a display area of the display panel through an original array process, so that the display area replaces an external integrated circuit board (Integrated Circuit, IC) to realize driving of the horizontal scanning line.

However, the conventional GDL driving circuit in the liquid crystal display panel generally adopts an 8T2C circuit structure, that is, the gate driving circuit of each horizontal scanning line includes 8 thin film transistors and 2 capacitors, which results in a large number of thin film transistors in the GDL driving circuit and a large occupied area, so that the frame of the display panel is wider, and the ultra-narrow frame design cannot be realized.

Disclosure of Invention

Accordingly, the main purpose of the present application is to provide a gate driving circuit and a display panel, which aims to solve the problems of the existing gate driving circuit that the number of thin film transistors is large, the occupied area is large, the frame is wide, and the ultra-narrow frame design cannot be realized.

In order to achieve the above objective, the present application provides a gate driving circuit, where the gate driving circuit includes M-level gate driving units sequentially arranged and cascade-arranged, and the M-level gate driving units are in one-to-one correspondence with M-sets of pixel units sequentially arranged. Each group of pixel units comprises (N+1) rows of pixel units which are sequentially arranged, wherein M is more than or equal to 1, and N is more than or equal to 2. Each stage of gate driving unit comprises an (n+1) sub driving unit, and the (n+1) sub driving unit corresponds to the (n+1) row of pixel units of the corresponding group of pixel units one by one. The (n+1) sub-driving units sequentially output (n+1) scanning signals according to a preset scanning sequence, so that the (n+1) rows of pixel units corresponding to the (n+1) sub-driving units are sequentially started. The (n+1) sub-driving units comprise a main driving unit and N sub-driving units, wherein the main driving unit corresponds to a first row of pixel units of a corresponding group of pixel units, and the main driving unit is used for responding to a trigger signal corresponding to a gate driving unit where the main driving unit is positioned and a first clock signal corresponding to the gate driving unit to output a corresponding scanning signal so as to start the first row of pixel units. The trigger signal is used for triggering the corresponding grid driving unit to work. The auxiliary driving unit is used for responding to the corresponding clock signals and outputting corresponding scanning signals so as to turn on the corresponding row of pixel units. The main driving unit comprises a main control node, and at least 2 auxiliary driving units in the N auxiliary driving units are directly and electrically connected with the main control node.

Optionally, the main driving unit includes a main control node, and a pull-up control module and a main output module electrically connected to the main control node, respectively. The pull-up control module is used for receiving a trigger signal corresponding to the gate driving unit where the pull-up control module is located and pulling up the potential of the main control node to a first level when the trigger signal is received. The main output module is used for outputting a first scanning signal when receiving a corresponding first clock signal and the potential of the main control node is a first level so as to start the first row of pixel units.

Optionally, at least a first auxiliary driving unit and a second auxiliary driving unit are included in the N auxiliary driving units, and the first auxiliary driving unit includes a first auxiliary control node, and a first separation module and a first auxiliary output module electrically connected to the first auxiliary control node respectively. The first separation module is electrically connected between the main control node and the first auxiliary control node, the first separation module is used for accessing the voltage of the main control node to pull up the potential of the first auxiliary control node to a first level, and the first auxiliary output module is used for outputting a second scanning signal when receiving a second clock signal corresponding to the first separation module and the potential of the first auxiliary control node is the first level so as to start the row pixel units corresponding to the first auxiliary output module. The second auxiliary driving unit comprises a second auxiliary control node, a second separation module and a second auxiliary output module which are respectively and electrically connected with the second auxiliary control node; the second separation module is electrically connected between the main control node and the second auxiliary control node, and is used for accessing the voltage of the main control node to pull up the potential of the second auxiliary control node to a first level, and the second auxiliary output module is used for outputting a third scanning signal when receiving a third clock signal corresponding to the second auxiliary output module and the potential of the second auxiliary control node is the first level so as to start the row pixel units corresponding to the second auxiliary output module.

Optionally, the main driving unit further includes a main pull-down module electrically connected to the main control node, where the main pull-down module is configured to pull down the potential of the main control node to a second level when receiving a main pull-down signal, and the main output module pauses outputting the first scan signal when not receiving the first clock signal or when the potential of the main control node is the second level. The main pull-down signal is a second scanning signal output by the first auxiliary output module. The first auxiliary driving unit further comprises a first auxiliary pull-down module electrically connected to the first auxiliary control node, the first auxiliary pull-down module is used for pulling down the potential of the first auxiliary control node to a second level when receiving a first auxiliary pull-down signal, and the first auxiliary output module pauses outputting the second scanning signal when not receiving the second clock signal or when the potential of the first auxiliary control node is the second level. The second sub-driving unit further includes a second sub-pull-down module electrically connected to the second sub-control node, the second sub-pull-down module is configured to pull down a potential of the second sub-control node to a second level when receiving a second sub-pull-down signal, and the second sub-output module is configured to suspend outputting the third scan signal when not receiving the third clock signal or when the potential of the second sub-control node is the second level.

Optionally, the x-th secondary driving unit in the N secondary driving units includes an x-th secondary control node, and an x-th separation module, an x-th secondary pull-down module and an x-th secondary output module electrically connected to the x-th secondary control node. Wherein N is more than or equal to x is more than or equal to 3. The x separation module is electrically connected between the main control node and the x secondary control node, and is used for accessing the voltage of the main control node to pull up the potential of the x secondary control node to a first level. Or, the xth separation module is electrically connected between a secondary control node included in another secondary driving unit and the xth secondary control node, and the xth separation module is used for accessing the voltage of the other secondary driving unit to pull up the potential of the xth secondary control node to a first level. The x-th sub output module is used for outputting an (x+1) -th scanning signal when an (x+1) -th clock signal is received and the x-th sub control node is at a first level. The x-th auxiliary pull-down module is used for pulling down the potential of the x-th auxiliary control node to a second level when receiving an x-th auxiliary pull-down signal, and the x-th auxiliary output module pauses outputting the (x+1) -th scanning signal when not receiving the (x+1) -th clock signal or when the potential of the x-th auxiliary control node is the second level. The (x-1) th auxiliary pull-down signal is the (x+1) th scanning signal output by the x-th auxiliary output module.

Optionally, the main driving unit further includes a cascade module, a control end of the cascade module is electrically connected to the main control node, and the cascade module is configured to output a cascade signal when the first clock signal is received and a potential of the main control node is a first level. The level transmission module is used for suspending outputting the level transmission signal when the first clock signal is not received or the potential of the main control node is at a second level.

Optionally, the pull-up control module includes a first switching tube, a control end of the first switching tube is electrically connected with a first connection end of the first switching tube, the control end of the first switching tube is used for receiving the trigger signal, and a second connection end of the first switching tube is electrically connected with the main control node. The control end of a first switching tube in the (m+1) th stage gate driving unit is electrically connected with the level transmission module of the m th stage gate driving unit, and the trigger signal received by the (m+1) th stage gate driving unit is a level transmission signal output by the level transmission module of the m th stage gate driving unit. Wherein M is more than or equal to M is more than or equal to 1.

Optionally, for any one of the main output module and the N auxiliary output modules, the output module includes a second switching tube and a capacitor, a control end of the second switching tube is electrically connected with a corresponding control node, a first connection end of the second switching tube is used for receiving a corresponding clock signal, and a second connection end of the second switching tube is used for outputting a corresponding scanning signal. The first end of the capacitor is electrically connected with the control end of the second switching tube, and the second end of the capacitor is electrically connected with the second connecting end of the second switching tube.

Optionally, the main driving unit further includes a scan signal pull-down module electrically connected to the second connection end of the second switching tube, where the scan signal pull-down module is configured to pull down the potential of the second connection end of the second switching tube to a second level when the second scan signal is received.

The application also provides a display panel, the display panel comprises a display area and a non-display area, the display area comprises a plurality of rows of pixel units, the non-display area is provided with the gate driving circuit, and the gate driving circuit is used for providing a plurality of scanning signals to drive the plurality of rows of pixel units to display.

In the gate driving circuit provided by the application, the primary gate driving unit comprises the (n+1) sub driving unit, the (n+1) sub driving unit comprises the main driving unit and N auxiliary driving units, and the (n+1) pixel unit can be driven, and as the (n+1) sub driving unit shares one trigger signal, only the pull-up control module, the pull-down maintaining module, the level transmission module and the level signal pull-down module are required to be arranged in the main driving unit 1, and compared with the circuit structure of 8T2C in the existing gate driving circuit, the primary gate driving unit can reduce a plurality of switching tubes and a plurality of capacitors. Therefore, the area of the driving circuit can be reduced, and the ultra-narrow frame design is facilitated.

Drawings

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present application, where the display panel includes a gate driving unit.

Fig. 2 is a schematic diagram of a structure of the gate driving unit shown in fig. 1.

Fig. 3 is another structural schematic diagram of the gate driving unit shown in fig. 1.

Fig. 4 is a schematic diagram of still another structure of the gate driving unit shown in fig. 1.

Fig. 5 is an operation timing diagram of the gate driving unit shown in fig. 2.

Fig. 6a is a circuit schematic of the gate driving unit shown in fig. 2 at a stage t 1.

Fig. 6b is a circuit schematic of the gate driving unit shown in fig. 2 at a section t2 to t 3.

Fig. 6c is a circuit schematic of the gate driving unit shown in fig. 2 at a stage t 4.

Fig. 6d is a circuit schematic of the gate driving unit shown in fig. 2 at a stage t 5.

Fig. 6e is a circuit schematic of the gate driving unit shown in fig. 2 at a stage t 6.

Description of main reference numerals:

display panel 1000

Gate drive circuit 1011

Non-display area 101

Display area 102

Gate drive unit 100

Scanning line 110

Main drive unit 1

A first auxiliary drive unit 2

A second sub-driving unit 3

Third auxiliary drive unit 4

Main control node Q1

First secondary control node Q2

Second sub control node Q3

Third auxiliary control node Q4

Pull-up control module 10

Main output Module 20

Main pulldown module 30

Pull-down maintenance module 40

Level transmission module 50

Stage signaling pull-down module 60

Scan signal pull-

down module

70, 80

First switching tube T1

Second switching tubes T2, T21, T22, T23

Third switching tubes T3, T31, T32 and T33

Switching tubes T4, T5, T6, T7, T8, T11, T12, T13

First separation module 21

Second separation module 31

Third separation module 41

First auxiliary output module 22

Second sub output module 32

Third sub output module 42

First sub-pulldown module 23

Second sub-pull-down module 33

Third sub-pulldown module 43

Capacitors C1, C2, C3, C4, C5

First power supply line VDD

Second power supply line VSS

The following detailed description will further illustrate the application in conjunction with the above-described figures.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without undue burden, are within the scope of the present application.

In the description of the present application, it should be noted that the azimuth or positional relationship indicated by the terms "upper", "lower", "left", "right", etc. are based on the azimuth or positional relationship shown in the drawings, and are merely for convenience of description of the present application and simplification of the description, and do not indicate or imply that the apparatus or element in question must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

Referring to fig. 1, the present application provides a display panel 1000, where the display panel 1000 includes a display area 102 and a non-display area 101 disposed around the display area 102. The display area 102 includes a plurality of scanning lines 110 and a plurality of rows of pixel units, where each scanning line 110 is electrically connected to each pixel unit P in the corresponding row of pixel units. A gate driving circuit 1011 is disposed in the non-display area 101, and the gate driving circuit 1011 is configured to provide a plurality of scanning signals to drive the plurality of rows of pixel units for display. In the embodiment of the present application, the gate driving circuit 1011 includes a GDL (gate driver less technology) driving circuit.

Specifically, the gate driving circuit 1011 includes M stages of gate driving units 100 sequentially arranged and cascade-arranged, and the M stages of gate driving units 100 are in one-to-one correspondence with M groups of pixel units sequentially arranged. In this embodiment of the present application, each group of pixel units includes (n+1) rows of pixel units sequentially arranged, and each stage of gate driving unit 100 includes (n+1) sub-driving units, where the (n+1) sub-driving units are in one-to-one correspondence with the (n+1) rows of pixel units of the corresponding group of pixel units. The (n+1) sub-driving units sequentially output (n+1) scanning signals according to a preset scanning sequence (for example, from the first row of pixel units to the last row of pixel units), so that the (n+1) row of pixel units corresponding to the (n+1) sub-driving units are sequentially started. Wherein M is more than or equal to 1, and N is more than or equal to 2. Taking n=3 and m=270 as an example, the display panel 1000 includes 1080 rows of pixel units and 270 stages of gate driving units 100, where each stage of gate driving unit 100 includes 4 sub-driving units, and each sub-driving unit is electrically connected to one scanning line 110 to scan a corresponding row of pixel units.

Referring to fig. 2, the (n+1) sub-driving units include a main driving unit 1 and N sub-driving units, wherein the main driving unit 1 corresponds to a first row of pixel units of a corresponding group of pixel units, and the main driving unit 1 is configured to output a corresponding scan signal in response to a trigger signal corresponding to a gate driving unit 100 where the main driving unit 1 is located and a first clock signal corresponding to the trigger signal, so as to turn on the first row of pixel units. The trigger signal is used to trigger the corresponding gate driving unit 100 to operate. The auxiliary driving unit is used for responding to the corresponding clock signals and outputting corresponding scanning signals so as to turn on the corresponding row of pixel units. In this embodiment, the main driving unit 1 includes a main control node Q1, and at least a first sub driving unit 2 and a second sub driving unit 3, which are all directly and electrically connected to the main control node Q1, are included in the N sub driving units. In this embodiment, the direct electrical connection between the first auxiliary driving unit 2 and the main control node Q1 means that no switching tube and other functional devices are disposed between the first auxiliary driving unit 2 and the main control node Q1.

In fig. 2, taking n=3 as an example, the circuit structure and the working principle of the gate driving unit 100 in the mth stage are described in detail, where m+.gtoreq.m+.gtoreq.1. Of course, N may be other positive integers in other embodiments, for example, n=2 as shown in fig. 3, i.e. the gate driving unit 100 includes a main driving unit 1, a first sub driving unit 2, and a second sub driving unit 3.

As shown in fig. 2, in the present embodiment, the main driving unit 1 in the mth stage gate driving unit 100 is configured to output a first scanning signal Gout (n) to scan the nth row of pixel units, the first sub driving unit 2 in the mth stage gate driving unit 100 is configured to output a second scanning signal Gout (n+1) to scan the (n+1) th row of pixel units, and the second sub driving unit 3 in the mth stage gate driving unit 100 is configured to output a third scanning signal Gout (n+2) to scan the (n+2) th row of pixel units. Wherein n= (m-1) ×n+1) +1, and the nth row of pixel units is the first row of pixel units in the mth group of pixel units.

Specifically, the main driving unit 1 includes a main control node Q1, a pull-up control module 10, a main output module 20, a main pull-down module 30, and a scan signal pull-down module 80.

The pull-up control module 10 is configured to receive a trigger signal corresponding to the gate driving unit 100 (i.e., the mth stage gate driving unit 100) where the pull-up control module is located, and pull up the potential of the main control node Q1 to a first level when the trigger signal is received. In this embodiment of the present application, the pull-up control module 10 includes a first switching tube T1, a control end of the first switching tube T1 is electrically connected to a first connection end thereof, the control end of the first switching tube T1 is configured to receive the trigger signal, and a second connection end of the first switching tube T1 is electrically connected to the main control node Q1. In this embodiment, the trigger signal is a high level signal, the first switch tube T1 is a high level conductive transistor, and the first switch tube T1 is turned on when the control end thereof receives the trigger signal, so as to pull up the potential of the main control node Q1 to a first level. It should be noted that, in the embodiments of the present application, the voltage (for example, 20V, 21V, 25V, etc.) that can control the high-level on transistor to be turned on is referred to as the first level.

The main output module 20 is electrically connected to the main control node Q1, and outputs the first scan signal Gout (n) when receiving the corresponding first clock signal Ck (n) and the potential of the main control node Q1 is the first level, so as to turn on the first row of pixel units (i.e. turn on the nth row of pixel units in all rows of pixel units). In this embodiment of the present application, the main output module 20 includes a second switching tube T2 and a capacitor C1, a control end of the second switching tube T2 is electrically connected to the main control node Q1, a first connection end of the second switching tube T2 is configured to receive the first clock signal Ck (n), and a second connection end of the second switching tube T2 is configured to output the first scanning signal Gout (n). The capacitor C1 is electrically connected between the control end of the second switching tube T2 and the second connection end of the second switching tube T2, the capacitor C1 is charged during the on period of T1, and the voltage holding function is performed on the main control node Q1 during the off period of T1. In this embodiment, the first clock signal Ck (n) is a high level signal, the second switching tube T2 is a high level conductive transistor, and the second switching tube T2 is turned on when the potential of the control end thereof (i.e., the potential of the main control node Q1) is a first level. During the on period of the second switching tube T2, when the first connection end of the second switching tube T2 receives the first clock signal Ck (n), the second connection end of the second switching tube T2 is connected to the first connection end of the second switching tube T2 and receives a high level signal. At this time, it can be understood that the second connection terminal of the second switching tube T2 outputs the first scan signal Gout (n). The first scan signal Gout (n) and the first clock signal Ck (n) are high-level signals.

The scan signal pull-down module 80 is configured to pull down the potential of the second connection terminal of the second switching tube T2 to a second level. Specifically, the scan signal pull-down module 80 includes a switch tube T7, where the switch tube T7 is electrically connected between the second connection end of the second switch tube T2 in the main output module 20 and the second power line VSS, a control end of the switch tube T7 is electrically connected to the first auxiliary driving unit 2, and a control end of the switch tube T7 is configured to receive the second scan signal Gout (n+1) output by the first auxiliary driving unit 2. The switching tube T7 is a high-level turn-on transistor, and the switching tube T7 is turned on when the control end thereof receives the second scanning signal Gout (n+1), so as to turn on the electrical connection between the second connection end of the second switching tube T2 and the second power line VSS, so as to pull down the potential of the second connection end of the second switching tube T2 to a second level, i.e., a low level, for example, 0V. At this time, it can be understood that the second connection terminal of the second switching tube T2 pauses outputting the first scan signal Gout (n).

The main pull-down module 30 is configured to pull down the potential of the main control node Q1 to a second level when the first sub driving unit 2 outputs the second scan signal Gout (n+1), and the main output module 20 pauses outputting the first scan signal Gout (n) when the first clock signal Ck (n) is not received or the potential of the main control node Q1 is the second level. In this embodiment, the main pull-down module 30 includes a third switch tube T3, a control end of the third switch tube T3 is electrically connected to the first auxiliary driving unit 2, a first connection end of the third switch tube T3 is electrically connected to the main control node Q1, and a second connection end of the third switch tube T3 is electrically connected to a second power line VSS, where the second power line VSS is configured to receive a voltage of a second level. The third switching transistor T3 is a high-level turn-on transistor, and the third switching transistor T3 is turned on when the control end thereof receives the second scan signal Gout (n+1), so as to turn on the electrical connection between the main control node Q1 and the second power line VSS, so as to pull down the potential of the main control node Q1 to the second level. The second switching tube T2 is turned off when the potential of the control terminal thereof is the second level. At this time, it can be understood that the pixel cells of the (n+1) th row are ready to be scanned after the pixel cells of the nth row are scanned, and thus, it is necessary to suspend the output of the first scan signal Gout (n). Wherein the second scan signal Gout (n+1) is a high level signal.

In the embodiment of the present application, the main driving unit 1 further includes a pull-down maintaining module 40 and a scan signal pull-down module 70. The pull-down maintaining module 40 is configured to output a pull-down maintaining signal to the scan signal pull-down module 70, and the scan signal pull-down module 70 is configured to pull down the potential of the second connection end of the second switching tube T2 to the second level in response to the pull-down maintaining signal.

Specifically, the pull-down maintaining module 40 includes a switch tube T4 and a capacitor C2, the control end of the switch tube T4 is electrically connected to the main control node Q1, the first connection end of the switch tube T4 is electrically connected to the first end of the capacitor C2, and the second connection end of the switch tube T4 is electrically connected to the second power line VSS. The second terminal of the capacitor C2 is further configured to receive the second clock signal Ck (n+1). The switching tube T4 is a high-level conduction transistor, the switching tube T4 is conducted when the main control node Q1 is at a first level, and the switching tube T4 is disconnected when the voltage of the main control node Q1 is at a second level. During the off period of the switching transistor T4, the capacitor C2 outputs the pull-down sustain signal through its first terminal when receiving the second clock signal Ck (n+1).

The scan signal pull-down module 70 includes a switch tube T6, the switch tube T6 is electrically connected between the second connection end of the second switch tube T2 in the main output module 20 and the second power line VSS, and the control end of the switch tube T6 is electrically connected with the first end of the capacitor C2. The switch tube T6 is configured to be turned on when receiving the pull-down maintaining signal, thereby turning on an electrical connection between the second connection terminal of the second switch tube T2 and the second power line VSS, and pull down the potential of the second connection terminal of the second switch tube T2 to a second level, that is, suspending outputting the first scanning signal Gout (n). When the capacitor C2 receives the second clock signal Ck (n+1), it indicates that the pixel cells in the n-th row have been scanned, and thus, it is necessary to suspend outputting the first scan signal Gout (n). Wherein the pull-down maintaining signal is a high level signal.

It should be noted that, the present application sets up two scan signal pull-down modules (i.e. 70, 80), which can accelerate the pull-down speed, prevent the pixel unit from being charged by mistake, and improve the tailing phenomenon. In other embodiments, only one scan signal pull-down module may be provided, which is not limited herein.

In the embodiment of the present application, the main driving unit 1 further includes a stage transmission module 50 and a stage transmission signal pull-down module 60.

The stage transmission module 50 is configured to output a stage transmission signal Carry (n) to trigger the (m+1) -th stage gate driving unit 100 to operate. The control end of the level transmission module 50 is electrically connected to the main control node Q1, and the level transmission module 50 is configured to output a level signal Carry (n) when the first clock signal Ck (n) is received and the potential of the main control node Q1 is at the first level. The cascade module 50 is configured to suspend outputting the cascade signal Carry (n) when the first clock signal Ck (n) or the potential of the main control node Q1 is not received at the second level. Note that, the trigger signal received by the control terminal of the first switching tube T1 in the first stage gate driving unit 100 is the frame start signal STV. The control end of the first switching tube T1 in the (m+1) -th stage gate driving unit 100 is electrically connected to the cascade module 50 of the m-th stage gate driving unit, and the trigger signal received by the (m+1) -th stage gate driving unit is a cascade signal (e.g., the cascade signal Carry (n-4) in fig. 2) output by the cascade module 50 of the m-th stage gate driving unit. In this embodiment of the present application, the cascade module 50 includes a switch tube T8, a control end of the switch tube T8 is electrically connected to the main control node Q1, a first connection end of the switch tube T8 is configured to receive the first clock signal Ck (n), and a second connection end of the switch tube T8 is configured to output the cascade signal Carry (n). The switching tube T8 is a transistor with a high-level conduction, and the switching tube T8 is turned on when the potential of the control end thereof (i.e., the potential of the main control node Q1) is the first level. During the on period of the second switching tube T8, when the first connection terminal of the switching tube T8 receives the first clock signal Ck (n), the second connection terminal of the switching tube T8 is connected to the first connection terminal of the switching tube T8 and receives a high level signal. It is understood that the second connection of the switching tube T8 outputs the stage signal Carry (n). Wherein the level signal Carry (n) is a high level signal.

The stage signal pull-down module 60 is configured to cause the stage signal module 50 to suspend outputting the stage signal Carry (n) when receiving the pull-down maintenance signal. The stage signal pull-down module 60 includes a switch tube T5, the switch tube T5 is electrically connected between the second connection end of the switch tube T8 in the stage signal pull-down module 50 and the second power line VSS, and the control end of the switch tube T5 is electrically connected with the first end of the capacitor C2. The switching tube T5 is a high-level conducting transistor, and the switching tube T5 is configured to conduct when receiving the pull-down maintaining signal, so as to conduct an electrical connection between the second connection end of the switching tube T8 and the second power line VSS, pull down the stage signaling signal Carry (n) to a second level, so as to pull down the potential of the second connection end of the switching tube T8 to the second level, i.e., to a low level, where it may be understood that the second connection end of the switching tube T8 pauses outputting the stage signaling signal Carry (n).

The first sub driving unit 2 includes a first sub control node Q2, a first separation module 21 and a first sub output module 22 electrically connected to the first sub control node Q2, respectively. The first separation module 21 is electrically connected between the main control node Q1 and the first sub control node Q2, and the first separation module 21 is configured to switch in the voltage of the main control node Q1 to pull up the potential of the first sub control node Q2 to a first level. The first sub-output module 22 is configured to output a second scan signal Gout (n+1) when receiving a corresponding second clock signal Ck (n+1) and the potential of the first sub-control node Q2 is at a first level, so as to turn on a row of pixel units corresponding to the first sub-output module 22. In this embodiment of the present application, the first separation module 21 includes a switch tube T11, a control end (i.e., a gate G) of the switch tube T11 is electrically connected to a first power line VDD, a first connection end (i.e., a source S) of the switch tube T11 is electrically connected to the main control node Q1, and a second connection end (i.e., a drain D) of the switch tube T11 is electrically connected to the first auxiliary control node Q2, where the first power line VDD is configured to receive a high level voltage. The switching transistor T11 is turned on when its gate-source voltage Vgs is greater than its threshold voltage Vth11 to pull up the potential of the first sub control node Q2 to a first level. The circuit structure of the first auxiliary output module 22 is the same as that of the main output module 20, and specifically includes a second switching tube T21 and a capacitor C3. The first connection end of the second switching tube T21 is configured to receive the second clock signal Ck (n+1), and the second connection end of the second switching tube T21 is configured to output the second scan signal Gout (n+1). The switch tube T11 is further configured to prevent the first auxiliary control node Q2 from transmitting power to the main control node Q1 in a reverse direction, so that mutual interference between different sub-driving units can be avoided.

The first auxiliary driving unit 2 further includes a first auxiliary pull-down module 23 electrically connected to the first auxiliary control node Q2, where the first auxiliary pull-down module 23 is configured to pull down the potential of the first auxiliary control node Q2 to a second level when receiving a first auxiliary pull-down signal, and the first auxiliary output module 22 pauses outputting the second scan signal Gout (n+1) when not receiving the second clock signal Ck (n+1) or the potential of the first auxiliary control node Q2 is the second level. In this embodiment, the circuit structure of the first auxiliary pull-down module 23 is the same as the circuit structure of the main pull-down module 20, and will not be described again.

In the embodiment of the present application, the second auxiliary driving unit 3 includes a second auxiliary control node Q3, and a second separation module 31 and a second auxiliary output module 32 electrically connected to the second auxiliary control node Q3, respectively; the second separation module 31 is electrically connected between the main control node Q1 and the second auxiliary control node Q3, the second separation module 31 is configured to switch in the voltage of the main control node Q1 to pull up the potential of the second auxiliary control node Q3 to a first level, and the second auxiliary output module 32 is configured to output a third scan signal Gout (n+2) when receiving a third clock signal Ck (n+2) corresponding to the second sub output module and the potential of the second auxiliary control node Q3 is the first level, so as to turn on the row of pixel units corresponding to the second auxiliary output module 32, i.e. the (n+2) th row of pixel units.

Further, the second sub driving unit 3 further includes a second sub pull-down module 33 electrically connected to the second sub control node Q3, the second sub pull-down module 33 is configured to pull down the potential of the second sub control node Q3 to a second level when receiving a second sub pull-down signal, and the second sub output module 32 pauses outputting the third scan signal Gout (n+2) when the third clock signal Ck (n+2) is not received or the potential of the second sub control node Q3 is the second level. In this embodiment, the circuit structure of the second auxiliary pull-down module 33 is the same as the circuit structure of the main pull-down module 20, and will not be described again.

In the embodiment of the present application, the mth stage gate driving unit 100 further includes a third sub driving unit 4, and the third sub driving unit 4 is configured to output a fourth scan signal Gout (n+3) to drive the (n+3) th row of pixel units. In this application, the circuit structure of the third auxiliary driving unit 4 is the same as the circuit structure of the first auxiliary driving unit 2, that is, the x-th auxiliary driving unit in the N auxiliary driving units includes an x-th auxiliary control node, and an x-th separation module, an x-th auxiliary pull-down module and an x-th auxiliary output module electrically connected to the x-th auxiliary control node, where N is greater than or equal to x is greater than or equal to 3.

In this embodiment of the present application, the y-th separation module is electrically connected between the main control node Q1 and the y-th secondary control node (i.e. the switching tubes T11, T12, T13 are connected in parallel to the main control node Q1), and the y-th separation module is used for accessing the voltage of the main control node Q1 to pull up the potential of the y-th secondary control node to a first level, where N is greater than or equal to y and greater than or equal to 1. Because the circuit structures of the N auxiliary driving units are the same, and the N auxiliary driving units are directly connected with the main control node Q1 (can be regarded as parallel connection and electric connection of the auxiliary driving units), the voltages of the auxiliary control nodes Q2-Q4 are almost equal, the consistency of scanning signals can be well maintained, the auxiliary driving units are orderly arranged, the structure is simple, and the occupied area is small.

In other embodiments, the xth separation module may be electrically connected between a secondary control node included in another secondary driving unit and the xth secondary control node, where the xth separation module is configured to access a voltage of the other secondary control node to pull up a potential of the xth secondary control node to a first level. For example, the third separation module 41 may be electrically connected between the second sub-control node Q3 and the third sub-control node Q4 (not shown in the figure), so that the third sub-driving unit 4 is not directly electrically connected to the main control node Q1, i.e., is electrically connected to the main control node Q1 through the switching tube T12.

Referring to fig. 4, in the present embodiment, the xth separation module is electrically connected to the (x-1) th secondary control node included in the (x-1) th secondary driving unit (i.e. the switching transistors T11, T12, T13 are sequentially connected in series to the primary control node Q1), and the xth separation module is configured to access the voltage of the (x-1) th secondary control node to pull up the potential of the xth secondary control node to the first level. It should be noted that, in the embodiment shown in fig. 4, since there is a voltage drop when the switching tube is turned on, the voltages of the sub control nodes Q2, Q3, Q4 are sequentially decreased after being pulled up to the first level, so that the parallel connection of the sub driving units is more beneficial to maintaining the voltage consistency of the scanning signals, and the circuit arrangement is simpler and the occupied area is smaller. In the embodiment of the application, 2N is less than or equal to 5, so that too many elements connected to the main control node Q1 can be avoided, thereby affecting the driving capability of the GDL circuit. The comparison of the voltage simulation results of the control nodes in the two connection modes can be referred to in table 1.

TABLE 1

	Q1	Q2	Q3	Q4
					Parallel connection	25V	24.5V	24.5V	24.5V
Series connection of	24V	23.2V	22.4V	21.6V

Referring to fig. 2 again, in the embodiment of the present application, the x-th sub output module is configured to output the (x+1) -th scan signal when the (x+1) -th clock signal is received and the x-th sub control node is at the first level. Wherein the xth clock signal is advanced in timing by a predetermined interval length μ from the (x+1) th clock signal.

In this embodiment of the present application, the x-th sub-pull-down module is configured to pull down, when receiving the x-th sub-pull-down signal, the potential of the x-th sub-control node to a second level, and the x-th sub-output module pauses outputting the (x+1) -th scan signal when not receiving the (x+1) -th clock signal or when the potential of the x-th sub-control node is the second level. The (x-1) th auxiliary pull-down signal is the (x+1) th scanning signal output by the x-th auxiliary output module. It should be noted that, in other embodiments, the cascade module 50 may also be disposed in the x-th auxiliary driving unit, that is, the control end of the switch tube T8 is electrically connected to the x-th auxiliary control node, the first connection end of the switch tube T8 is used for receiving the (x+1) -th clock signal, and the second connection end of the switch tube T8 is used for outputting the stage signal Carry (n+x+1), which is not limited herein.

In other embodiments, the scan signal pull-down module 80 may be disposed in each sub-driving unit, that is, a switching tube T7 may be disposed between the output module of the driving unit and the second power line VSS, where the switching tube T7 controls the driving unit to output the pause output scan signal by using the scan signal output by the next sub-driving unit, which is not limited herein.

The switching transistors T1 to T8, T11 to T13, T21 to T23, and T31 to T33 in the present application may be amorphous silicon thin film transistors (a-Si TFTs), low temperature polysilicon thin film transistors (LTPS TFTs), or Oxide semiconductor thin film transistors (Oxide TFTs). Among them, an active layer of the Oxide semiconductor thin film transistor employs an Oxide semiconductor (Oxide), such as indium gallium zinc Oxide (Indium Gallium Zinc Oxide, IGZO). Note that, since IGZO has high electron mobility, low power consumption, and high touch performance, the TFT can be made smaller by using IGZO as an active layer. When each switch tube in the application adopts the IGZO-TFT, the design of a narrow frame is more facilitated.

In this embodiment of the present application, the primary gate driving unit 100 includes 4 sub-driving units, and may provide 4 scan signals, and the control nodes in the 4 sub-driving units share the pull-up voltage by setting 3 separation modules, so that only the pull-up control module 10, the pull-down maintaining module 40, the level transmission module 50 and the level signal pull-down module 60 need to be set in the main driving unit 1, and compared with the circuit structure of 8T2C in the existing gate driving circuit, the primary gate driving unit 100 may reduce 9 switching tubes and 3 capacitors. In addition, the scan signal pull-

down modules

70, 80 are provided only in the main driving unit 1, and 6 switching transistors can be further reduced. Therefore, the circuit area of the GDL driving circuit can be reduced by 50-60%, and the ultra-narrow frame design is facilitated. It is understood that the larger the number of sub-driving units included in the first-stage gate driving unit 100, the larger the reduced circuit area, and the narrower the frame.

For a clearer description of the operation of the gate driving unit 100, please refer to fig. 5, 6 a-6 e together.

As shown in fig. 5, the gate driving unit 100 sequentially operates in six phases within one frame scanning period:

as shown in fig. 6a, in the stage T1, the first switching tube T1 receives the trigger signal Carry (n-4) and is turned on, and the main control node Q1 is pulled up to the first level (the voltage value is VGH), so that the second switching tube T2, the switching tube T4 and the switching tube T8 are all turned on. In this stage, the switching transistor T11 is turned on and the voltage of the main control node Q1 is applied to pull up the potential of the first sub control node Q2 to the first level until the gate-source voltage Vgs of the switching transistor T11 is equal to the threshold voltage Vth11 thereof to enter the critical off state. The second switching transistor T21 is turned on in response to the potential of the first sub control node Q2 being the first level. Similarly, the potentials of the second sub control node Q3 and the third sub control node Q4 are pulled up to the first level (the voltage value is VGH), and the second switching transistor T22 and the second switching transistor T23 are both turned on. The second connection terminal of the second switching tube T2 outputs a low voltage signal (the voltage value is VGL), and at this time, it can be understood that the first scan signal Gout (n) is not output.

As shown in fig. 6b, in the stage T2, the first switching tube T1 is turned off without receiving the trigger signal Carry (n-4), and at this time, since the capacitors C1, C3 to C5 all have the voltage holding function, the potentials of the main control node Q1 and the auxiliary control nodes Q2 to Q4 do not rapidly drop to the low level, so that the second switching tubes T2, T21 to T23 and the switching tubes T4, T8 can still keep continuously turned on.

In the period T3, the second switching tube T2 receives the first clock signal Ck (n) and outputs the first scan signal Gout (n) to turn on the pixel units of the nth row. The switching transistor T8 receives the first clock signal Ck (n) and outputs the stage signal Carry (n) to pull up the main control node Q1 of the (m+1) -th stage gate driving unit 100 to the first level. In addition, the potential of the second end of the capacitor C1 rises by Δv (Δv is VGH-VGL in theory), and the voltage of the main control node Q1 rises to (vgh+Δv) due to the coupling effect of the capacitor C1, so that the second switching tube T2 and the switching tubes T4 and T8 remain continuously turned on.

As shown in fig. 6c, in the period T4, the second switching tube T21 receives the second clock signal Ck (n+1) and outputs the second scan signal Gout (n+1) to turn on the pixel unit of the (n+1) th row, so that the third switching tube T3 is turned on and pulls down the potential of the main control node Q1 to the second level, and the switching tube T7 is also turned on to suspend the second switching tube T2 from outputting the first scan signal Gout (n). After the potential of Q1 is pulled down to the second level, the second switching tube T2, the switching tubes T4 and T8 are all turned off, and at the same time, the second end of the capacitor C2 receives the second clock signal Ck (n+1), and due to the coupling effect of the capacitor C2, the potential of the first end of the capacitor C2 also rises to Δv, so that both the switching tubes T5 and T6 are turned on, and further the switching tube T8 pauses outputting the output stage signal Carry (n), and the second switching tube T2 pauses outputting the first scanning signal Gout (n). Due to the coupling action of the capacitor C3, the voltage of the first sub-control node Q2 rises to (vgh+Δv), so that the second switching transistor T21 remains continuously turned on, and the gate-source voltage Vgs of the switching transistor T11 is completely turned off below the threshold voltage thereof.

As shown in fig. 6d, in the period T5, the second switching tube T22 receives the third clock signal Ck (n+2) and outputs the third scan signal Gout (n+2) to turn on the pixel cells of the (n+2) th row, so that the third switching tube T31 is turned on and pulls down the potential of the first sub control node Q2 to the second level, thereby turning off the second switching tube T21. Meanwhile, the switching transistor T21 pauses outputting the second scan signal Gout (n+1) without receiving the second clock signal Ck (n+1), thereby turning off all of the third switching transistors T3, T5 to T7. In addition, due to the coupling action of the capacitor C4, the voltage of the second secondary control node Q3 rises to (vgh+Δv) accordingly, so that the switching tube T22 remains continuously turned on, and the gate-source voltage Vgs of the switching tube T12 is completely turned off below the threshold voltage thereof. Since the potential of the first sub control node Q2 is pulled down to the second level, the gate-source voltage Vgs of the switching transistor T11 is greater than the threshold voltage thereof to be turned on.

As shown in fig. 6e, in the stage T6, the second switching tube T23 receives the fourth clock signal Ck (n+3) and outputs the fourth scan signal Gout (n+3) to turn on the pixel cells of the (n+3) th row, so that the third switching tube T32 is turned on and pulls down the potential of the second sub control node Q3 to the second level, thereby turning off the switching tube T22. Meanwhile, the second switching transistor T22 pauses outputting the third scan signal Gout (n+2) without receiving the third clock signal Ck (n+2). In addition, due to the coupling action of the capacitor C4, the voltage of the third secondary control node Q4 rises to (vgh+Δv) accordingly, so that the switching tube T23 remains continuously turned on, and the gate-source voltage Vgs of the switching tube T13 is completely turned off below the threshold voltage thereof. Since the potential of the second sub control node Q3 is pulled down to the second level, the gate-source voltage Vgs of the switching transistor T12 is greater than the threshold voltage thereof to be turned on.

Similarly, in the next stage, when the (m+1) -th stage gate driving unit 100 starts to operate, the second switching transistor T2 of the (m+1) -th stage gate driving unit 100 receives the corresponding first clock signal Ck (n+4) and outputs the corresponding first scan signal Gout (n+4), so that the third switching transistor T33 is turned on and pulls down the potential of the third sub control node Q4 to the second level, thereby turning off the switching transistor T23.

In the gate driving circuit 1011 provided in this application, the primary gate driving unit 100 includes (n+1) sub-driving units, which can drive the (n+1) pixel units, and since the (n+1) sub-driving units share a trigger signal, only the pull-up control module 10, the pull-down maintaining module 40, the level transmission module 50 and the level transmission signal pull-down module 60 need to be set in the main driving unit 1, and compared with the circuit structure of 8T2C in the existing gate driving circuit, the primary gate driving unit 100 can reduce a plurality of switching tubes and a plurality of capacitors. Therefore, the area of the GDL driving circuit can be reduced, and the ultra-narrow frame design is facilitated.

While embodiments of the present application have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the application, the scope of which is defined by the claims and their equivalents.

Claims

1. The grid driving circuit comprises M levels of grid driving units which are sequentially arranged and are in cascade connection, wherein the M levels of grid driving units are in one-to-one correspondence with M groups of pixel units which are sequentially arranged,

each group of pixel units comprises (N+1) rows of pixel units which are sequentially arranged, wherein M is more than or equal to 1, and N is more than or equal to 2;

each stage of gate driving unit comprises an (n+1) sub driving unit, and the (n+1) sub driving units are in one-to-one correspondence with the (n+1) rows of pixel units of the corresponding group of pixel units;

the (N+1) sub-driving units sequentially output (N+1) scanning signals according to a preset scanning sequence, so that the (N+1) rows of pixel units corresponding to the (N+1) sub-driving units are sequentially started;

the (n+1) sub-driving units comprise a main driving unit and N sub-driving units, the main driving unit corresponds to a first row of pixel units of a corresponding group of pixel units, the N sub-driving units correspond to a second row of pixel units to an (n+1) th row of pixel units of the corresponding group of pixel units one by one, and the main driving unit is used for responding to a trigger signal corresponding to the gate driving unit where the main driving unit is positioned and a first clock signal corresponding to the gate driving unit to output corresponding scanning signals so as to start the first row of pixel units;

The auxiliary driving unit is used for responding to the corresponding clock signals and outputting corresponding scanning signals so as to turn on the corresponding row pixel units; the main driving unit comprises a main control node, the N auxiliary driving units comprise auxiliary control nodes, the N auxiliary driving units are electrically connected with the main control node, and at least 2 auxiliary driving units in the N auxiliary driving units are directly and electrically connected with the main control node;

the trigger signal is used for triggering the corresponding gate driving unit to work, the main control node is pulled up to a first level, so that the main driving unit can respond to a corresponding first clock signal to output a corresponding scanning signal, and each auxiliary control node is pulled up to the first level through the main control node, so that each auxiliary driving unit can respond to a corresponding clock signal to output the corresponding scanning signal.

2. The gate driving circuit of claim 1, wherein the main driving unit further comprises a pull-up control module and a main output module electrically connected to the main control node, respectively;

the pull-up control module is used for receiving a trigger signal corresponding to the gate driving unit where the pull-up control module is located and pulling up the potential of the main control node to a first level when the trigger signal is received;

The main output module is used for outputting a first scanning signal when receiving a corresponding first clock signal and the potential of the main control node is a first level so as to start the first row of pixel units.

3. The gate driving circuit of claim 2, wherein at least a first sub driving unit and a second sub driving unit are included in the N sub driving units, the first sub driving unit including a first sub control node, and a first separation module and a first sub output module electrically connected to the first sub control node, respectively; the first separation module is electrically connected between the main control node and the first auxiliary control node, the first separation module is used for accessing the voltage of the main control node to pull up the potential of the first auxiliary control node to a first level, and the first auxiliary output module is used for outputting a second scanning signal when receiving a second clock signal corresponding to the first separation module and the potential of the first auxiliary control node is the first level so as to start the row pixel units corresponding to the first auxiliary output module;

the second auxiliary driving unit comprises a second auxiliary control node, a second separation module and a second auxiliary output module which are respectively and electrically connected with the second auxiliary control node; the second separation module is electrically connected between the main control node and the second auxiliary control node, and is used for accessing the voltage of the main control node to pull up the potential of the second auxiliary control node to a first level, and the second auxiliary output module is used for outputting a third scanning signal when receiving a third clock signal corresponding to the second auxiliary output module and the potential of the second auxiliary control node is the first level so as to start the row pixel units corresponding to the second auxiliary output module.

4. The gate driving circuit of claim 3, wherein the main driving unit further comprises a main pull-down module electrically connected to the main control node, the main pull-down module being configured to pull down a potential of the main control node to a second level when a main pull-down signal is received, the main output module suspending outputting the first scan signal when the first clock signal is not received or the potential of the main control node is the second level; the main pull-down signal is a second scanning signal output by the first auxiliary output module;

the first auxiliary driving unit further comprises a first auxiliary pull-down module electrically connected to the first auxiliary control node, wherein the first auxiliary pull-down module is used for pulling down the potential of the first auxiliary control node to a second level when a first auxiliary pull-down signal is received, and the first auxiliary output module pauses outputting the second scanning signal when the second clock signal is not received or the potential of the first auxiliary control node is the second level;

the second sub-driving unit further includes a second sub-pull-down module electrically connected to the second sub-control node, the second sub-pull-down module is configured to pull down a potential of the second sub-control node to a second level when receiving a second sub-pull-down signal, and the second sub-output module is configured to suspend outputting the third scan signal when not receiving the third clock signal or when the potential of the second sub-control node is the second level.

5. The gate driving circuit of claim 4, wherein an xth sub driving unit of the N sub driving units includes an xth sub control node, and an xth separation module, an xth sub pull-down module, and an xth sub output module electrically connected to the xth sub control node; wherein, N is more than or equal to x is more than or equal to 3;

the x separation module is electrically connected between the main control node and the x secondary control node, and is used for accessing the voltage of the main control node to pull up the potential of the x secondary control node to a first level; or, the x separation module is electrically connected between a secondary control node included in another secondary driving unit and the x secondary control node, and the x separation module is used for accessing the voltage of the other secondary driving unit to pull up the potential of the x secondary control node to a first level;

the x-th sub output module is used for outputting an (x+1) -th scanning signal when receiving an (x+1) -th clock signal and the x-th sub control node is at a first level;

the x-th auxiliary pull-down module is used for pulling down the potential of the x-th auxiliary control node to a second level when receiving an x-th auxiliary pull-down signal, and the x-th auxiliary output module pauses outputting the (x+1) -th scanning signal when not receiving the (x+1) -th clock signal or when the potential of the x-th auxiliary control node is the second level; the (x-1) th auxiliary pull-down signal is the (x+1) th scanning signal output by the x-th auxiliary output module.

6. The gate driving circuit of claim 2, wherein the main driving unit further comprises a cascode module, a control terminal of the cascode module being electrically connected to the main control node, the cascode module being configured to output a cascode signal when the first clock signal is received and a potential of the main control node is at a first level; the level transmission module is used for suspending outputting the level transmission signal when the first clock signal is not received or the potential of the main control node is at a second level.

7. The gate drive circuit of claim 6, wherein the pull-up control module comprises a first switching tube, a control end of the first switching tube is electrically connected with a first connection end of the first switching tube, the control end of the first switching tube is used for receiving the trigger signal, and a second connection end of the first switching tube is electrically connected with the main control node;

the control end of a first switching tube in the (m+1) th stage gate driving unit is electrically connected with a level transmission module of the m th stage gate driving unit, and a trigger signal received by the (m+1) th stage gate driving unit is a level transmission signal output by the level transmission module of the m th stage gate driving unit; wherein M is more than or equal to M is more than or equal to 1.

8. A gate driving circuit according to claim 3, wherein, for any one of the main output module and the N sub output modules, the output module includes a second switching tube and a capacitor, a control terminal of the second switching tube is electrically connected to a corresponding control node, a first connection terminal of the second switching tube is used for receiving a corresponding clock signal, and a second connection terminal of the second switching tube is used for outputting a corresponding scan signal; the first end of the capacitor is electrically connected with the control end of the second switching tube, and the second end of the capacitor is electrically connected with the second connecting end of the second switching tube.

9. The gate driving circuit of claim 8, wherein the main driving unit further comprises a scan signal pull-down module electrically connected to the second connection terminal of the second switching tube, the scan signal pull-down module being configured to pull down a potential of the second connection terminal of the second switching tube to a second level when the second scan signal is received.

10. A display panel comprising a display area and a non-display area, the display area comprising a plurality of rows of pixel cells, wherein the non-display area is provided with a gate driving circuit according to any one of claims 1 to 9 for providing a plurality of scanning signals for driving the plurality of rows of pixel cells to display.