CN114628498A - Semiconductor device - Google Patents

Abstract

The invention provides a semiconductor device which comprises a substrate, a first buried layer positioned on part of the substrate, an epitaxial layer positioned on the first buried layer and the substrate, a triode unit positioned in the epitaxial layer, a first isolation region and a second isolation region, wherein the first isolation region and the second isolation region sequentially surround the triode unit, base regions of the first isolation region and the triode unit have the same conductivity type, an emission region and a collector region of the triode unit and the first buried layer of the second isolation region and the triode unit have the same conductivity type, and the second isolation region is connected with the first buried layer. The first buried layer and the second isolation region can form a protection ring to isolate the substrate from the triode unit, so that the noise of the substrate is prevented from influencing the performance of the triode unit; the triode unit is used as an effective triode in the semiconductor device, the collector region, the first isolation region and the second isolation region can form an additional triode, and the second isolation region and the substrate can also form a diode, so that the noise of the substrate is further isolated.

Description

Semiconductor device

technical field

The present invention relates to the technical field of semiconductors, and in particular, to a semiconductor device.

Background technique

Bipolar Junction Transistor (BJT) is widely used in various types of analog circuits such as amplifiers, comparators, switching circuits, oscillator circuits or bandgap reference circuits. At present, the vertical bipolar junction transistor usually forms the triode unit in the epitaxial layer of the substrate. However, the isolation performance between the substrate and the triode unit is not good, and the noise of the substrate will affect the performance of the triode unit. In order to improve the isolation performance between the substrate and the triode unit, it is usually necessary to make a deep buried layer to completely surround the triode unit. Although the deep buried layer can isolate part of the noise of the substrate, the isolation effect is limited, and the noise of the substrate will still affect the The performance of the triode unit cannot be further improved.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a semiconductor device to solve the problem that the isolation performance between the substrate of the existing semiconductor device and the triode unit cannot be further improved.

In order to achieve the above object, the present invention provides a semiconductor device, comprising:

substrate;

a first buried layer, located on part of the substrate;

an epitaxial layer, located on the first buried layer and the substrate;

A triode unit, located in the epitaxial layer, includes an emitter region, a base region and a collector region; and,

A first isolation region and a second isolation region are located in the epitaxial layer and sequentially surround the triode unit from the inside to the outside, the first isolation region and the base region have the same conductivity type, and the second isolation region The region, the emitter region, the collector region and the first buried layer have the same conductivity type, and the second isolation region is connected to the first buried layer.

Optionally, also include:

A second buried layer is located on part of the first buried layer, the second buried layer and the first isolation region have the same conductivity type, and the first isolation region is connected to the second buried layer.

Optionally, the first isolation region and the second isolation region are used for applying the same voltage.

Optionally, the voltage is 0V~120V.

Optionally, also include:

a connection well region, located between the second isolation region and the first buried layer, the connection well region and the second isolation region have the same conductivity type, and the second isolation region passes through the connection well A region connects the first buried layer.

Optionally, the connection well region includes at least two stacked sub-well regions.

Optionally, also include:

A drift region located in the N-type epitaxial layer, the drift region and the collector region have the same conductivity type, and the emitter region, the base region and the collector region are all located in the drift region .

Optionally, the triode unit is an NPN triode unit or a PNP triode unit.

Optionally, the first isolation region includes a first well region and a first doped region located in the first well region, and the first well region and the first doped region have the same conductivity type and/or, the second isolation region includes a second well region and a second doped region located in the second well region, the second well region and the second doped region having the same conductivity and/or, the base region includes a third well region and a third doped region located in the third well region, the third well region and the third doped region have the same conductivity type and/or, the collector region includes a fourth well region and a fourth doped region located in the fourth well region, and the fourth well region and the fourth doped region have the same conductivity type .

Optionally, the emitter region is located in the third well region, the third doped region surrounds the emitter region, and the collector surrounds the third well region.

Optionally, the thickness of the epitaxial layer is greater than or equal to 12 microns.

In the semiconductor device provided by the present invention, it includes a substrate, a first buried layer located on a part of the substrate, an epitaxial layer located on the first buried layer and the substrate, and an epitaxial layer located in the epitaxial layer. A triode unit, a first isolation area, and a second isolation area, the first isolation area and the second isolation area surround the triode unit in sequence, and the first isolation area and the base area of the triode unit have the same The conductivity type, the second isolation region, the emitter region and the collector region of the triode unit, and the first buried layer have the same conductivity type, and the second isolation region is connected to the first buried layer. The first buried layer and the second isolation region in the present invention can form a guard ring to isolate the substrate and the triode unit, so as to prevent the noise of the substrate from affecting the performance of the triode unit; at the same time , the triode unit is used as an effective triode in the semiconductor device, and the collector region, the first isolation region and the second isolation region can constitute an additional triode, and the second isolation region and the The substrate can also form a diode, so as to further isolate the substrate and the triode unit and improve the performance of the semiconductor device.

Description of drawings

FIG. 1 is a schematic top view of a semiconductor device according to Embodiment 1 of the present invention;

2 is a schematic cross-sectional view of the semiconductor device in FIG. 1 along the A-A direction;

3 is an equivalent schematic diagram of the semiconductor device provided in Embodiment 1 of the present invention;

4 is a schematic cross-sectional view of a semiconductor device provided in Embodiment 2 of the present invention;

5 is a schematic top view of the semiconductor device provided in Embodiment 3 of the present invention;

6 is a schematic cross-sectional view of the semiconductor device in FIG. 5 along the A-A direction;

FIG. 7 is an equivalent schematic diagram of the semiconductor device provided in Embodiment 3 of the present invention;

Among them, the reference numerals are:

101-substrate; 102-epitaxial layer; 201-first buried layer; 202-second buried layer; 300-triode unit; 301-emitter region; 302-base region; 302a-third doping region; 302b-th 303-collector region; 303a-fourth doped region; 303b-fourth well region; 401-first isolation region; 401a-first doped region; 401b-first well region; 402-th Two isolation regions; 402a-second doping region; 402b-second well region; 403-connecting well region; 500-drift region; 600-isolation structure;

D11-first NPN transistor; D21-second NPN transistor; D12-first PNP transistor; D22-second PNP transistor; D31-first diode; D32-second diode.

Detailed ways

The specific embodiments of the present invention will be described in more detail below with reference to the schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are all in a very simplified form and in inaccurate scales, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.

Example 1

FIG. 1 is a schematic top view of the semiconductor device provided in this embodiment, and FIG. 2 is a schematic cross-sectional view of the semiconductor device in FIG. 1 along the A-A direction. As shown in FIG. 1 and FIG. 2 , this embodiment provides a semiconductor device including a substrate 101 , a first buried layer 201 , an epitaxial layer 102 , a triode unit 300 , a first isolation region 401 and a second isolation region 402 .

Specifically, the substrate 101 is a P-type substrate, the first buried layer 201 is located on part of the substrate 101 to cover part of the top surface of the substrate 101 ; the epitaxial layer 102 is N type epitaxial layer, the epitaxial layer 102 is located on the first buried layer 201 and the substrate 101 to cover the remaining top surface of the first buried layer 201 and the substrate 101 .

It should be understood that the substrate 101 is not limited to be a P-type substrate, and the epitaxial layer 102 is not limited to an N-type epitaxial layer. In other embodiments, the substrate 101 may also be an N-type substrate, so The epitaxial layer 102 may also be a P-type epitaxial layer, which will not be repeated here.

Further, the epitaxial layer 102 has a drift region 500, the drift region 500 is located above the first buried layer 201, the triode unit 300 is located in the drift region 500, and the drift region 500 can start In order to isolate the substrate 101 from the triode unit 300 , noise in the substrate 101 can be prevented from affecting the performance of the triode unit 300 .

In this embodiment, the drift region 500 extends downward from the top surface of the epitaxial layer 102 to the top surface of the first buried layer 201 , that is, the bottom surface of the drift region 500 and the first The top surface of the buried layer 201 is in contact, but it should not be limited thereto, and the bottom surface of the drift region 500 may also not be in contact with the top surface of the first buried layer 201 but have a certain distance.

The triode unit 300 includes an emitter region 301 , a base region 302 and a collector region 303 . Specifically, the base region 302 includes a third well region 302b and a third doped region 302a, the third well region 302b and the third doped region 302a have the same conductivity type, and the third The doped region 302a is located in the third well region 302b and is annular; the emitter region 301 is also located in the third well region 302b, and the emitter region 301 is surrounded by the third doped region 302a, The emitter region 301 has different conductivity types from the third well region 302b and the third doping region 302a; the collector region 303 includes a fourth well region 303b and a fourth doping region 303a, the The fourth well region 303b and the fourth doping region 303a have the same conductivity type, and the fourth doping region 303a is located in the fourth well region 303b and has a ring shape, and the base region 302 is surrounded by the The collector region 303 surrounds. The emitter region 301 , the base region 302 and the collector region 303 can be drawn out to serve as the emitter, base and collector of the triode unit 300 respectively.

In this embodiment, the triode unit 300 is an NPN triode unit. Therefore, the conductivity type of the emitter region 301 and the collector region 303 are both N-type, and the conductivity type of the base region 302 is P-type. That is, the conductivity types of the emitter region 301, the fourth well region 303b, the fourth doped region 303a and the drift region 500 are all N-type, and the third well region 302b and the first The conductivity types of the three-doped regions 302a are all P-type.

Please continue to refer to FIG. 1 and FIG. 2 , the first isolation region 401 is located in the epitaxial layer 102 and includes a first well region 401b and a first doped region 401a, the first well region 401b and the first The doped regions 401a have the same conductivity type, and the first doped regions 401a are located in the first well region 401b. In this embodiment, the first isolation region 401 and the base region 302 have the same conductivity type, so the conductivity type of the first isolation region 401 is P-type, that is, the first well region 401b and the The conductivity types of the first doped regions 401a are all P-type.

Further, the first isolation region 401 is annular and surrounds the triode unit 300 , that is, the first well region 401b and the first doping region 401a are both annular and surround the triode unit 300 .

Please continue to refer to FIG. 1 and FIG. 2 , the second isolation region 402 is located in the epitaxial layer 102 and includes a second well region 402b and a second doped region 402a, the second well region 402b and the second The doped regions 402a have the same conductivity type, and the second doped regions 402a are located in the second well regions 402b. In this embodiment, the second isolation region 402 , the emitter region 301 , the collector region 303 and the first buried layer 201 have the same conductivity type, so the second isolation region 402 and the The conductivity types of the first buried layer 201 are both N-type, that is, the conductivity types of the second well region 402b and the second doped region 402a are both N-type.

Further, the second isolation region 402 is annular and surrounds the first isolation region 401, that is, the second well region 402b and the second doping region 402a are both annular in shape to surround the first isolation region 401. An isolation area 401 . It can also be seen from FIG. 1 that the first isolation region 401 and the second isolation region 402 sequentially surround the triode unit 300 from the inside to the outside.

In this embodiment, the second isolation region 402 is connected to the first buried layer 201 . Specifically, the epitaxial layer 102 further includes a connection well region 403, and the connection well region 403 is located between the second well region 402b and the first buried layer 201 to connect the second well region 402b With the first buried layer 201 , the second isolation region 402 and the first buried layer 201 are further connected.

It can be understood that, since the second well region 402b is annular, the connecting well region 403 is preferably also annular; and, since the connecting well region 403 is used to connect the second isolation region 402 and the The first buried layer 201, so the connection well region 403, the second isolation region 402 and the first buried layer 201 should have the same conductivity type, that is, the conductivity type of the connection well region 403 is Type N.

In this embodiment, the number of the connection well region 403 is one. In other embodiments, if the thickness of the epitaxial layer 102 is relatively large, the connection well region 403 may include at least two stacked sub-well regions. Therefore, the difficulty of preparing the connection well region 403 is reduced; of course, as an optional embodiment, the connection well region 403 can also be omitted, and the first well region 401b can be directly extended downward to the first buried layer 201 to connect the second isolation region 402 with the first buried layer 201 .

Optionally, the thickness of the epitaxial layer 101 may be greater than or equal to 12 microns, but should not be limited thereto.

It can be understood that, between the emitter region 301 and the third doping region 302a, between the third doping region 302a and the fourth doping region 303a, and the fourth doping region 303a There is an isolation structure 600 between the first doping region 401a and the first doping region 401a and the second doping region 402a, so as to avoid mutual influence between adjacent doping regions.

FIG. 3 is an equivalent schematic diagram of the semiconductor device provided in this embodiment. As shown in FIG. 3 , the transistor unit 300 constitutes a first NPN transistor D11, the collector region 303, the first isolation region 401 and the second isolation region 402 can constitute a second NPN transistor D21, the The second isolation region 402 and the substrate 101 may form a first diode D31. When the semiconductor device is in use, the first isolation region 401 and the second isolation region 402 are used to apply the same voltage, for example, a voltage of 0V to 120V can be applied, and the first NPN transistor D11 is used as an effective transistor. , the first buried layer 201 and the second isolation region 402 can form a guard ring to isolate the substrate 101 and the first NPN transistor D11 to prevent the noise of the substrate 101 from affecting the first performance of the NPN triode D11; at the same time, the second NPN triode D21 and the first diode D31 can further isolate the first NPN triode D11 from the substrate 101 to avoid the Noise affects the performance of the first NPN transistor D11, and the isolation effect is better than that of using only one diode for isolation.

Embodiment 2

FIG. 4 is a schematic cross-sectional view of the semiconductor device provided in this embodiment. As shown in FIG. 4 , the difference from Embodiment 1 is that, in this embodiment, the semiconductor device further includes a second buried layer 202 .

Specifically, the second buried layer 202 is located on a part of the first buried layer 201 to cover a part of the top surface of the first buried layer 201 . The second buried layer 202 can be considered to be located in the epitaxial layer 102, or can be considered to be sandwiched between the first buried layer 201 and the epitaxial layer 102, depending on the preparation of the second buried layer 202 Process depends.

Further, the second buried layer 202 and the first isolation region 401 have the same conductivity type, so the conductivity type of the second buried layer 202 is P-type.

In this embodiment, the first isolation region 401 is connected to the second buried layer 202 . Specifically, the first well region 401b extends downward to the top surface of the second buried layer 202 , thereby connecting the first isolation region 401 and the second buried layer 202 . As an optional embodiment, the first isolation region 401 may also be connected to the second buried layer 202 by using an additional connection well region, which will not be illustrated here.

It can be understood that, compared with the first embodiment, the second buried layer 202 is added in this embodiment, and the second buried layer 202 and the first isolation region 401 can form another guard ring, The double guard ring structure can further isolate the noise in the substrate 101 and improve the performance of the semiconductor device.

Embodiment 3

FIG. 5 is a schematic top view of the semiconductor device provided in this embodiment, and FIG. 6 is a schematic cross-sectional view of the semiconductor device in FIG. 5 along the A-A direction. As shown in FIG. 5 and FIG. 6 , the difference from Embodiment 1 and Embodiment 2 is that in this embodiment, the triode unit 300 is a PNP triode unit.

Specifically, in this embodiment, the conductivity types of the emitter region 301 and the collector region 303 are both P-type, and the conductivity type of the base region 302 is N-type, that is, the emitter regions 301, The conductivity types of the fourth well region 303b, the fourth doped region 303a and the drift region 500 are all P-type, while the conductivity types of the third well region 302b and the third doped region 302a Both are N type.

Correspondingly, the first isolation region 401 and the base region 302 have the same conductivity type, so the conductivity type of the first isolation region 401 is N-type, that is, the first well region 401b and the The conductivity types of the first doped regions 401a are all N-type. The second isolation region 402 , the emitter region 301 , the collector region 303 and the first buried layer 201 have the same conductivity type, so the second isolation region 402 and the first buried layer 201 The conductivity type is P-type, that is, the conductivity types of the second well region 402b and the second doped region 402a are both P-type.

FIG. 7 is an equivalent schematic diagram of the semiconductor device provided in this embodiment. As shown in FIG. 7 , the triode unit 300 may constitute a first PNP triode D12, the emitter region 301, the first isolation region 401 and the second isolation region 402 may constitute a second PNP triode D22, the The second isolation region 402 and the epitaxial layer 102 can form a second diode D32. When the semiconductor device is in use, the first isolation region 401 and the second isolation region 402 are used to apply the same voltage, for example, a voltage of 0V to 120V can be applied, and the first PNP transistor D12 is used as an effective transistor , the first buried layer 201 and the second isolation region 402 can form a guard ring to isolate the substrate 101 and the first PNP transistor D12 to prevent the noise of the substrate 101 from affecting the first performance of the PNP triode D12; at the same time, the second PNP triode D22 and the second diode D32 can further isolate the first PNP triode D12 from the substrate 101 to avoid the Noise affects the performance of the first PNP transistor D12, and the isolation effect is better compared to using only one diode for isolation.

To sum up, the semiconductor device provided in the embodiments of the present invention includes a substrate, a first buried layer on a part of the substrate, an epitaxial layer on the first buried layer and the substrate, and a first buried layer on the substrate. The triode unit, the first isolation area and the second isolation area in the epitaxial layer, the first isolation area and the second isolation area surround the triode unit in turn, the first isolation area and the triode unit are The base region has the same conductivity type, the second isolation region, the emitter and collector regions of the triode unit, and the first buried layer have the same conductivity type, and the second isolation region is connected to the first Buried layer. The first buried layer and the second isolation region in the present invention can form a guard ring to isolate the substrate and the triode unit, so as to prevent the noise of the substrate from affecting the performance of the triode unit; at the same time , the triode unit is used as an effective triode in the semiconductor device, and the collector region, the first isolation region and the second isolation region can constitute an additional triode, and the second isolation region and the The substrate can also form a diode, so as to further isolate the substrate and the triode unit and improve the performance of the semiconductor device.

It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the various embodiments may be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant part can be referred to the description of the method.

It should also be noted that although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible changes and modifications can be made to the technical solution of the present invention by using the technical content disclosed above, or modified into equivalents of equivalent changes. Example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solutions of the present invention still fall within the protection scope of the technical solutions of the present invention.

It should also be understood that unless otherwise specified or indicated, the terms "first", "second", "third" and other descriptions in the specification are only used to distinguish various components, elements, steps, etc. in the specification, rather than It is used to represent the logical relationship or sequence relationship among various components, elements, steps, etc.

Also, it should be appreciated that the terminology described herein is used to describe particular embodiments only, and not to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a" and "an" include plural references unless the context clearly dictates otherwise. For example, reference to "a step" or "a means" means a reference to one or more steps or means, and may include sub-steps as well as sub-means. All conjunctions used should be understood in their broadest sense. Also, the word "or" should be understood to have the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly dictates otherwise. Furthermore, implementation of methods and/or apparatuses in embodiments of the present invention may include performing selected tasks manually, automatically, or a combination.

Claims (11)

1. A semiconductor device, comprising:

a substrate;

a first buried layer located on a portion of the substrate;

the epitaxial layer is positioned on the first buried layer and the substrate;

the triode unit is positioned in the epitaxial layer and comprises an emitter region, a base region and a collector region; and the number of the first and second groups,

the first isolation region and the second isolation region are located in the epitaxial layer and sequentially surround the triode unit from inside to outside, the first isolation region and the base region are of the same conductive type, the second isolation region, the emitter region, the collector region and the first buried layer are of the same conductive type, and the second isolation region is connected with the first buried layer.

2. The semiconductor device according to claim 1, further comprising:

and the second buried layer is positioned on part of the first buried layer, has the same conductivity type with the first isolation region, and is connected with the second buried layer by the first isolation region.

3. The semiconductor device according to claim 1 or 2, wherein the first isolation region and the second isolation region are used for applying the same voltage.

4. The semiconductor device according to claim 3, wherein the voltage is 0V to 120V.

5. The semiconductor device according to claim 1 or 2, further comprising:

and the connecting well region is positioned between the second isolation region and the first buried layer, the connecting well region and the second isolation region have the same conductivity type, and the second isolation region is connected with the first buried layer through the connecting well region.

6. The semiconductor device of claim 5, wherein the link well region comprises at least two stacked sub-well regions.

7. The semiconductor device according to claim 1, further comprising:

the drift region is positioned in the N-type epitaxial layer, the drift region and the collector region have the same conductivity type, and the emitter region, the base region and the collector region are all positioned in the drift region.

8. The semiconductor device according to claim 1, wherein the transistor cell is an NPN transistor cell or a PNP transistor cell.

9. The semiconductor device of claim 1, wherein the first isolation region comprises a first well region and a first doped region located in the first well region, the first well region and the first doped region having a same conductivity type; and/or the second isolation region comprises a second well region and a second doped region positioned in the second well region, and the second well region and the second doped region have the same conductivity type; and/or the base region comprises a third well region and a third doped region positioned in the third well region, and the third well region and the third doped region have the same conductivity type; and/or the collector region comprises a fourth well region and a fourth doped region positioned in the fourth well region, and the fourth well region and the fourth doped region have the same conductivity type.

10. The semiconductor device of claim 1, wherein the emitter region is located within the third well region, the third doped region surrounds the emitter region, and the collector region surrounds the third well region.

11. The semiconductor device of claim 1, wherein the epitaxial layer has a thickness greater than or equal to 12 microns.

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