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CN114628369A - A FBGA package structure and method with electromagnetic shielding - Google Patents

A FBGA package structure and method with electromagnetic shielding Download PDF

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Publication number
CN114628369A
CN114628369A CN202210255538.1A CN202210255538A CN114628369A CN 114628369 A CN114628369 A CN 114628369A CN 202210255538 A CN202210255538 A CN 202210255538A CN 114628369 A CN114628369 A CN 114628369A
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electromagnetic shielding
lead frame
fbga
lead
metal carrier
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周健威
胡金花
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Huatian Technology Nanjing Co Ltd
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Huatian Technology Nanjing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
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  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The invention provides an FBGA packaging structure with electromagnetic shielding effect and a method thereof, comprising a metal carrier, a lead wire, a lead frame, a solder ball, a first plastic package material, an ASIC chip and a second plastic package material; the metal carriers are arranged on two sides of the first plastic package material, the lead and the ASIC chip are embedded in the plastic package body, the solder ball is arranged on the outer side of the second plastic package material, the lead frame is embedded in the second plastic package material, one end of the lead is electrically connected with the ASIC chip, the other end of the lead is connected with one end of the lead frame, and the other end of the lead frame is welded with the solder ball; the bottom of the ASIC chip is connected with the second plastic package material; the invention can directly paste the metal sheet on the single-layer lead frame, and the lead frame is wrapped by the plastic package material, thereby playing a role of supporting similar substrates. The invention is equivalent to using a single-layer lead frame to replace 2-layer or even 4-layer substrates, and can flexibly use the metal carrier required in the process of manufacturing the lead frame to replace the traditional metal cover wall.

Description

一种具有电磁屏蔽的FBGA封装结构及方法A FBGA package structure and method with electromagnetic shielding

技术领域technical field

本发明属于电子器件技术领域，涉及一种具有电磁屏蔽的FBGA封装结构及方法The invention belongs to the technical field of electronic devices, and relates to an FBGA packaging structure and method with electromagnetic shielding

背景技术Background technique

电子器件领域有很多对电磁干扰很敏感的集成电路芯片(IC芯片)。在IC芯片封装时应用电磁屏蔽技术，将屏蔽层和封装完全结合在一起，实现IC芯片的高度集成。IC芯片封装有多种封装形式，如DIP，SOP，BGA等。其中FBGA封装形式一般都搭配2层甚至4层基板，成本较高。因此，如何有效降低封装成本，成为了业界的一个重要研究方向。In the field of electronic devices, there are many integrated circuit chips (IC chips) that are sensitive to electromagnetic interference. Electromagnetic shielding technology is applied in IC chip packaging, and the shielding layer and packaging are completely combined to achieve high integration of IC chips. IC chip packaging has a variety of packaging forms, such as DIP, SOP, BGA, etc. Among them, the FBGA package form is generally equipped with a 2-layer or even 4-layer substrate, and the cost is relatively high. Therefore, how to effectively reduce the packaging cost has become an important research direction in the industry.

发明内容SUMMARY OF THE INVENTION

针对现有技术中存在的问题，本发明提供一种具有电磁屏蔽的FBGA封装结构及方法，直接把金属片贴在单层引线框架上，同时引线框架被塑封料包裹，起到了类似于基板的支撑作用。In view of the problems existing in the prior art, the present invention provides an FBGA packaging structure and method with electromagnetic shielding. The metal sheet is directly attached to the single-layer lead frame, and at the same time, the lead frame is wrapped by plastic sealing material, which plays a role similar to that of the substrate. support.

本发明是通过以下技术方案来实现：The present invention is achieved through the following technical solutions:

一种具有电磁屏蔽作用的FBGA封装结构，包括金属载体，引线，引线框架，锡球，第一塑封料，ASIC芯片和第二塑封料；An FBGA package structure with electromagnetic shielding effect, comprising a metal carrier, leads, lead frames, solder balls, a first plastic encapsulation compound, an ASIC chip and a second plastic encapsulation compound;

所述金属载体设置在第一塑封料的两侧，所述引线与ASIC芯片包埋在塑封体中，所述锡球设置在第二塑封料的外侧，所述引线框架包埋在第二塑封料中，所述引线的一端与ASIC芯片电性连接，所述引线的另一端与引线框架的一端连接，所述引线框架的另一端与锡球焊接连接；所述ASIC芯片的底部与第二塑封料连接；所述第一塑封料的顶部设置有金属片，所述金属载体与金属片构成FBGA的电磁屏蔽层。The metal carrier is arranged on both sides of the first plastic sealing compound, the leads and the ASIC chip are embedded in the plastic sealing body, the solder balls are arranged on the outside of the second plastic sealing compound, and the lead frame is embedded in the second plastic sealing body. In the material, one end of the lead is electrically connected to the ASIC chip, the other end of the lead is connected to one end of the lead frame, and the other end of the lead frame is welded to the solder ball; the bottom of the ASIC chip is connected to the second The plastic sealing compound is connected; the top of the first plastic sealing compound is provided with a metal sheet, and the metal carrier and the metal sheet constitute an electromagnetic shielding layer of the FBGA.

优选的，所述金属载体的背面与正面均设有衬底层。Preferably, the backside and the frontside of the metal carrier are provided with a substrate layer.

优选的，所述衬底层的材质采用铜；所述引线框架的材质采用铜。Preferably, the material of the substrate layer is copper; the material of the lead frame is copper.

优选的，所述金属载体的材质采用铜、SPCC和不锈钢中的一种。Preferably, the material of the metal carrier is one of copper, SPCC and stainless steel.

优选的，所述ASIC芯片的底部与第二塑封料通过胶水密封粘连。Preferably, the bottom of the ASIC chip and the second plastic sealing compound are sealed and adhered by glue.

优选的，所述锡球采用阵列排布方式，所述引线框架采用阵列排布方式。Preferably, the solder balls are arranged in an array, and the lead frames are arranged in an array.

优选的，所述FBGA的电磁屏蔽层的厚度为2um～50um。Preferably, the thickness of the electromagnetic shielding layer of the FBGA is 2um-50um.

一种具有电磁屏蔽作用的FBGA封装的方法，包括，A method of FBGA packaging with electromagnetic shielding effect, comprising,

在金属载体上进行涂覆，曝光和电镀铜图案，将金属载体，引线，引线框架，锡球与ASIC芯片按照要求组装成电子元器件，用第一塑封料和第二塑封料对电子元器件进行封装，对封装后的金属载体和金属片进行蚀刻处理后得到电磁屏蔽层，具有电磁屏蔽作用的FBGA封装完成。Coating, exposing and electroplating copper patterns on the metal carrier, assembling the metal carrier, leads, lead frames, solder balls and ASIC chips into electronic components as required, using the first plastic compound and the second plastic compound to assemble the electronic components After encapsulation, the encapsulated metal carrier and the metal sheet are etched to obtain an electromagnetic shielding layer, and the FBGA encapsulation with electromagnetic shielding effect is completed.

与现有技术相比，本发明具有以下有益的技术效果：Compared with the prior art, the present invention has the following beneficial technical effects:

本发明提出了一种具有电磁屏蔽的FBGA封装结构及方法，可直接把金属片贴在单层引线框架上，同时引线框架被塑封料包裹，起到了类似基板的支撑作用。本发明相当于使用单层引线框架去替代2层甚至4层基板，且可灵活运用制造引线框架过程中需要用到的金属载体，使之替代传统的金属盖盖壁。同时，作为电磁屏蔽层，对金属载体的利用达到了最大化，可大幅降低封装成本。此外，本发明把引线框架和金属载体当成了一个三维的整体，除了利用引线框架来替代基板以外，还利用蚀刻后的金属载体来替代封装产品的金属盖盖壁，可进行电磁屏蔽作用，相当于把金属载体也有效利用起来，对金属载体的利用达到了最大化，大大节约了封装成本。The invention proposes an FBGA packaging structure and method with electromagnetic shielding, which can directly attach a metal sheet on a single-layer lead frame, and at the same time, the lead frame is wrapped by a plastic encapsulating material, which plays a supporting role similar to a substrate. The invention is equivalent to using a single-layer lead frame to replace a 2-layer or even a 4-layer substrate, and can flexibly use the metal carrier required in the process of manufacturing the lead frame to replace the traditional metal cover wall. At the same time, as an electromagnetic shielding layer, the utilization of the metal carrier is maximized, which can greatly reduce the packaging cost. In addition, the present invention regards the lead frame and the metal carrier as a three-dimensional whole. In addition to using the lead frame to replace the substrate, the etched metal carrier is also used to replace the metal cover wall of the packaged product, which can perform electromagnetic shielding. Since the metal carrier is also effectively utilized, the utilization of the metal carrier is maximized, which greatly saves the packaging cost.

附图说明Description of drawings

图1为现有技术的FBGA封装外形图；Fig. 1 is the FBGA package outline drawing of the prior art;

图2为现有技术的FBGA封装的内部结构示意图；Fig. 2 is the internal structure schematic diagram of the FBGA package of the prior art;

图3为本发明的具有电磁屏蔽作用的FBGA封装结构图；Fig. 3 is the FBGA package structure diagram with electromagnetic shielding effect of the present invention;

图4为实施例中引线框架制备流程示意图；FIG. 4 is a schematic diagram of the preparation process of the lead frame in the embodiment;

图5为实施例中上芯贴片流程示意图；FIG. 5 is a schematic diagram of a chip loading process in an embodiment;

图6为实施例中焊线流程示意图；6 is a schematic diagram of a wire bonding process in an embodiment;

图7为实施例中安装金属片流程示意图；FIG. 7 is a schematic diagram of a flow chart of installing a metal sheet in an embodiment;

图8为实施例中带金属片塑封模具示意图；Fig. 8 is the schematic diagram of the plastic sealing mold with metal sheet in the embodiment;

图中：金属载体1，引线2，引线框架3，锡球4，衬底层5，第一塑封料6，ASIC芯片7，胶水8，第二塑封料9，金属片10，引脚11，基板12，上模13，下模14。In the figure: metal carrier 1, lead 2, lead frame 3, solder ball 4, substrate layer 5, first plastic compound 6, ASIC chip 7, glue 8, second plastic compound 9, metal sheet 10, lead 11, substrate 12, the upper mold 13, the lower mold 14.

具体实施方式Detailed ways

下面结合具体的实施例对本发明做进一步的详细说明，所述是对本发明的解释而不是限定。The present invention will be further described in detail below in conjunction with specific embodiments, which are to explain rather than limit the present invention.

目前FBGA基本封装结构可参如图1及图2所示。若其封装构造包含以下几个特点，则可以采用本发明方案进行优化。(1)IO数少：一般只有4～6个引脚，最多不会超过8个引脚；(2)对电磁干扰很敏感；目前某些FBGA类IO数较少(4～8个)，封装结构简单，完全可以使用类似框架结构的简单封装，从而降低成本。但目前使用2层甚至4层基板，造成封装成本较高。At present, the basic package structure of FBGA can be referred to as shown in Figure 1 and Figure 2. If the package structure includes the following features, the solution of the present invention can be used for optimization. (1) The number of IOs is small: generally there are only 4 to 6 pins, and no more than 8 pins at most; (2) It is very sensitive to electromagnetic interference; The package structure is simple, and a simple package similar to a frame structure can be used, thereby reducing the cost. However, 2-layer or even 4-layer substrates are currently used, resulting in high packaging costs.

因此，如图3所示，本发明提供的一种具有电磁屏蔽作用的FBGA封装结构，包括金属载体1，引线2，引线框架3，锡球4，第一塑封料6，ASIC芯片7和第二塑封料9；所述金属载体1设置在第一塑封料6的两侧，所述引线2与ASIC芯片7包埋在第一塑封料6中，而本发明把引线框架和金属载体(Carrier)当成了一个3维的整体，除了利用引线框架来替代基板以外，还利用蚀刻后的Carrier作为金属盖壁，对封装体起电磁屏蔽作用，大大节约了产品的封装成本，且对Carrier的利用达到了最大化。Therefore, as shown in FIG. 3, an FBGA package structure with electromagnetic shielding function provided by the present invention includes a metal carrier 1, a lead 2, a lead frame 3, a solder ball 4, a first plastic sealing compound 6, an ASIC chip 7 and a first Two plastic encapsulation compounds 9; the metal carrier 1 is arranged on both sides of the first plastic encapsulation compound 6, the leads 2 and the ASIC chip 7 are embedded in the first plastic encapsulation compound 6, and the present invention combines the lead frame and the metal carrier (Carrier ) as a 3-dimensional whole, in addition to using the lead frame to replace the substrate, the etched carrier is also used as the metal cover wall to play an electromagnetic shielding effect on the package, which greatly saves the packaging cost of the product, and the use of carrier maximized.

所述锡球4设置在第二塑封料9的外侧，所述引线框架3包埋在第二塑封料9中，所述引线2的一端与ASIC芯片7电性连接，所述引线2的另一端与引线框架3的一端连接，所述引线框架3的另一端与锡球4连接；所述ASIC芯片7的底部与第二塑封料9连接。所述金属载体1的背面与正面均设有衬底层5。所述衬底层5的材质为铜，铜具有优异的导电性能，所述金属载体1的材质采用铜、SPCC和不锈钢中的一种。第一塑封料6的顶部设置有金属片(10)，所述金属载体1与金属片10构成FBGA的电磁屏蔽层。金属载体1的高度与第一塑封料6相同，金属片10与第一塑封料6的长、宽尺寸相同。所述FBGA的电磁屏蔽层的厚度为2um～50um。针对引脚较少的FBGA封装形式，本发明提出了一种直接把金属盖贴在单层引线框架上的方案，同时引线框架被塑封料包裹，起到了类似基板的支撑作用。本发明相当于使用单层引线框架替代2层甚至4层基板，且灵活运用制造引线框架过程中需要用到的金属Carrier，使之替代传统的金属盖盖壁，作为电磁屏蔽层，对Carrier的利用达到了最大化，可大幅降低封装成本。The solder balls 4 are arranged on the outer side of the second plastic sealing compound 9 , the lead frame 3 is embedded in the second plastic sealing compound 9 , one end of the lead wire 2 is electrically connected to the ASIC chip 7 , and the other end of the lead wire 2 is electrically connected to the ASIC chip 7 . One end is connected to one end of the lead frame 3 , and the other end of the lead frame 3 is connected to the solder balls 4 ; the bottom of the ASIC chip 7 is connected to the second plastic sealing compound 9 . The backside and the frontside of the metal carrier 1 are provided with a substrate layer 5 . The material of the substrate layer 5 is copper, which has excellent electrical conductivity, and the material of the metal carrier 1 is one of copper, SPCC and stainless steel. A metal sheet (10) is provided on the top of the first plastic sealing compound 6, and the metal carrier 1 and the metal sheet 10 constitute an electromagnetic shielding layer of the FBGA. The height of the metal carrier 1 is the same as that of the first molding compound 6 , and the length and width of the metal sheet 10 and the first molding compound 6 are the same. The thickness of the electromagnetic shielding layer of the FBGA is 2um-50um. Aiming at the FBGA package form with fewer pins, the present invention proposes a scheme of directly attaching the metal cover to the single-layer lead frame, while the lead frame is wrapped by plastic encapsulation material, which plays a supporting role similar to the substrate. The invention is equivalent to using a single-layer lead frame to replace a 2-layer or even a 4-layer substrate, and flexibly utilizes the metal carrier required in the process of manufacturing the lead frame to replace the traditional metal cover wall as an electromagnetic shielding layer. Utilization is maximized and packaging costs can be significantly reduced.

所述ASIC芯片7的底部与第二塑封料9通过胶水8密封粘连。胶水采用低应力胶水或者采用环氧树脂粘结剂；所述引线框架3的材质采用铜。所述锡球4采用阵列排布方式。所述引线框架3采用阵列排布方式。所述第一塑封料6的顶部设置有金属盖。The bottom of the ASIC chip 7 is sealed and adhered to the second plastic sealing compound 9 by glue 8 . The glue adopts low-stress glue or epoxy resin adhesive; the lead frame 3 is made of copper. The solder balls 4 are arranged in an array. The lead frame 3 is arranged in an array. The top of the first plastic sealing compound 6 is provided with a metal cover.

一种具有电磁屏蔽作用的FBGA封装的方法，包括，A method of FBGA packaging with electromagnetic shielding effect, comprising,

先在金属载体上进行涂覆，曝光，电镀金属片，在进行组装电子元器件，用塑封料进行封装，对封装后的塑封料表面进行研磨抛光；对金属载体进行蚀刻处理后得到电磁屏蔽层，在塑封体表面粘贴金属片，整体电子元器件的FBGA封装完成。Coating, exposing, and electroplating metal sheets on the metal carrier first, assembling electronic components, encapsulating them with plastic sealing compound, grinding and polishing the surface of the encapsulated plastic sealing compound; etching the metal carrier to obtain an electromagnetic shielding layer , Paste a metal sheet on the surface of the plastic package, and the FBGA packaging of the overall electronic components is completed.

本发明需要先把用塑封料保护的铜引线框架先制造出来，然后把该框架发送到封装厂进行正常封装。如图4-8所示，整体流程可分解如下：In the present invention, the copper lead frame protected by the plastic sealing compound needs to be manufactured first, and then the frame is sent to a packaging factory for normal packaging. As shown in Figure 4-8, the overall process can be decomposed as follows:

(1)金属载体的制备，金属载体采用SPCC或者不锈钢；(1) Preparation of metal carrier, the metal carrier adopts SPCC or stainless steel;

(2)在金属载体上进行涂覆、曝光，电镀第1层铜图案；(2) coating and exposing on the metal carrier, and electroplating the copper pattern of the first layer;

(3)在第1层铜图案上进行涂覆、曝光，电镀第2层铜图案；(3) coating, exposure on the 1st layer copper pattern, electroplating the 2nd layer copper pattern;

(4)把干膜去除；(4) Remove the dry film;

(5)对电子器件进行塑封；(5) Plastic packaging of electronic devices;

(6)对塑封后的表面进行研磨抛光；(6) Grinding and polishing the surface after plastic sealing;

(7)对金属载体(Carrier)进行蚀刻处理，直到露出第1层铜图案；并且在靠近每个Package的边缘保留2～50um的Carrier的侧壁作为电磁屏蔽用；至此，用塑封料保护的铜引线框架制造完成。(7) The metal carrier (Carrier) is etched until the first layer of copper pattern is exposed; and the side wall of the carrier with 2-50um is reserved near the edge of each Package for electromagnetic shielding; The copper lead frame is manufactured.

(8)把该框架发送到封装厂进行正常封装；(8) Send the frame to the packaging factory for normal packaging;

(9)在该框架上进行贴片；(9) Patching on the frame;

(10)在该框架上进行打线；(10) Lay lines on the frame;

(11)塑封模具内预先安置金属片，采用压缩成型工艺对电子元器件进行塑封，同时在塑封料表面贴上金属片，与刻蚀后的金属载体搭配，以使Package完成完整的电磁屏蔽层，如图8所示；(11) The metal sheet is pre-placed in the plastic sealing mold, and the electronic components are plastic-sealed by the compression molding process. At the same time, the metal sheet is pasted on the surface of the plastic sealing material and matched with the etched metal carrier, so that the Package can complete the complete electromagnetic shielding layer. , as shown in Figure 8;

(12)把整个框架切割成一颗一颗的封装结构，并包装出货。(12) Cut the whole frame into a package structure one by one, and package it for shipment.

本发明在Window etch工程中，增加了Package边缘保留Carrier侧壁的蚀刻工序，该封装流程和封装结构除了可使用在图例无需植球的封装结构上，同样适用于需要植球且引脚较少的FBGA封装结构。In the Window etch project of the present invention, the etching process of retaining the carrier sidewall at the edge of the package is added. The packaging process and packaging structure can be used in the package structure that does not require ball mounting as shown in the legend, and is also suitable for ball mounting and fewer pins. FBGA package structure.

综上所述，本发明把引线框架和Carrier当成了一个3维的整体，除了利用引线框架来替代基板以外，还利用蚀刻后的Carrier来替代封装产品的金属盖盖壁，可进行电磁屏蔽作用，相当于把Carrier也有效利用起来，对Carrier的利用达到了最大化，大大节约了封装成本。目前，硅麦封装成本0.3～0.4元，金属盖成本约0.1元RMB，基板成本约0.06元RMB。使用本发明后金属片成本有望下降50％到0.05元RMB，基板成本可下降30％到0.04元RMB。To sum up, the present invention regards the lead frame and the carrier as a 3-dimensional whole. In addition to using the lead frame to replace the substrate, the etched carrier is also used to replace the metal cover wall of the packaged product, which can perform electromagnetic shielding. , which is equivalent to effectively utilizing the carrier, maximizing the utilization of the carrier, and greatly saving the packaging cost. At present, the cost of silicon wheat packaging is 0.3 to 0.4 yuan, the cost of metal cover is about 0.1 yuan, and the cost of substrate is about 0.06 yuan. After using the invention, the cost of the metal sheet can be reduced by 50% to 0.05 yuan RMB, and the cost of the substrate can be reduced by 30% to 0.04 yuan RMB.

Claims (9)

1. An FBGA packaging structure with electromagnetic shielding effect is characterized by comprising a metal carrier (1), a lead (2), a lead frame (3), a solder ball (4), a first plastic packaging material (6), an ASIC chip (7) and a second plastic packaging material (9);
the metal carrier (1) is arranged on two sides of the first plastic packaging material (6), the lead (2) and the ASIC chip (7) are embedded in the first plastic packaging material (6), the solder ball (4) is arranged on the outer side of the second plastic packaging material (9), the lead frame (3) is embedded in the second plastic packaging material (9), one end of the lead (2) is electrically connected with the ASIC chip (7), the other end of the lead (2) is connected with one end of the lead frame (3), and the other end of the lead frame (3) is connected with the solder ball (4) in a welding mode; the bottom of ASIC chip (7) is connected with second plastic-sealed material (9), the top of first plastic-sealed material (6) is provided with sheetmetal (10), metal carrier (1) constitutes FBGA's electromagnetic shield with sheetmetal (10).
2. FBGA package with electromagnetic shielding effect as claimed in claim 1, characterized in that the metal carrier (1) is provided with a substrate layer (5) on both its back and front side.
3. The FBGA package structure with electromagnetic shielding effect as claimed in claim 2, wherein the material of the substrate layer (5) is copper; the lead frame (3) is made of copper.
4. The FBGA package structure with electromagnetic shielding effect as claimed in claim 1, wherein the metal carrier (1) is made of one of copper, SPCC and stainless steel.
5. The FBGA package structure with electromagnetic shielding effect as claimed in claim 1, wherein the bottom of the ASIC chip (7) is hermetically bonded to the second molding compound (9) by glue (8).
6. The FBGA packaging structure with the electromagnetic shielding effect as claimed in claim 1, wherein the solder balls (4) are arranged in an array.
7. The FBGA package structure with electromagnetic shielding effect as claimed in claim 1, wherein the lead frames (3) are arranged in an array.
8. The FBGA package structure with electromagnetic shielding effect of claim 1, wherein the thickness of the electromagnetic shielding layer of the FBGA is 2um to 50 um.
9. An FBGA packaging method with electromagnetic shielding effect based on the packaging structure of any one of claims 1-8, comprising,
coating the metal carrier (1), exposing and electroplating copper patterns, assembling the metal carrier (1), the lead (2), the lead frame (3), the solder balls (4) and the ASIC chip (7) into an electronic component according to requirements, packaging the electronic component by using a first plastic package material (6) and a second plastic package material (9), etching the packaged metal carrier (1) and the packaged metal sheet (10) to obtain an electromagnetic shielding layer, and completing FBGA packaging with the electromagnetic shielding function.
CN202210255538.1A 2022-03-09 2022-03-09 A FBGA package structure and method with electromagnetic shielding Pending CN114628369A (en)

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Citations (3)

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Publication number Priority date Publication date Assignee Title
US20160260686A1 (en) * 2015-03-05 2016-09-08 Sii Semiconductor Corporation Resin-encapsulated semiconductor device and method of manufacturing the same
CN107210271A (en) * 2015-02-27 2017-09-26 东和株式会社 Electronic unit and its manufacture method and manufacture device
CN108063130A (en) * 2017-12-29 2018-05-22 江苏长电科技股份有限公司 There is electromagnetic shielding encapsulating structure and its manufacturing process that pin side wall climbs tin

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107210271A (en) * 2015-02-27 2017-09-26 东和株式会社 Electronic unit and its manufacture method and manufacture device
US20160260686A1 (en) * 2015-03-05 2016-09-08 Sii Semiconductor Corporation Resin-encapsulated semiconductor device and method of manufacturing the same
CN108063130A (en) * 2017-12-29 2018-05-22 江苏长电科技股份有限公司 There is electromagnetic shielding encapsulating structure and its manufacturing process that pin side wall climbs tin

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