CN114615445A - Phototransistor and photosensitive method thereof - Google Patents

Abstract

The invention relates to a photoelectric transistor with photoelectric response, which comprises a substrate, a bottom gate electrode, a bottom gate dielectric layer, an active layer, a top gate dielectric layer and a top gate electrode which are stacked layer by layer; the active layer comprises a semiconductor material with a light memory function, and the active layer comprises a channel and a source drain region; in the illumination stage and the integration stage, the voltages of a bottom gate electrode and a top gate electrode of the phototransistor are different, and the phototransistor is in an off-state working area; the integration stage at least comprises a first preset time period after the exposure is finished; wherein the semiconductor material with the optical memory function comprises a metal oxide semiconductor. The invention also relates to a method for sensing light by using the double-gate phototransistor, wherein the active layer material of the double-gate phototransistor comprises a material with a light memory function. The invention also relates to an image sensor array.

Description

Phototransistor and photosensitive method thereof

technical field

The invention relates to the field of photoelectric imaging of display technology, in particular to a phototransistor with photoelectric response.

Background technique

In recent years, thin film transistor (Thin Film Transistor, TFT) technology has made great progress. Due to its characteristics of being suitable for large-area mass production and array processing, TFT is very suitable for making active matrix flat panel imagers with high performance, low power consumption and low cost. At present, the mainstream X-ray Digital Radiography (X-ray DR) systems are mainly divided into two types: direct X-ray digital imaging and indirect X-ray digital imaging. In a typical direct X-ray digital imaging scheme, amorphous selenium (a-Se) is used as the photosensitive unit, and amorphous silicon (a-Si) TFT is used to make a switch array to read out photoelectric signals (hereinafter referred to as the The detector is a direct type a-Se flat panel detector). Its working principle is that the incident X-ray makes the selenium layer generate electron-hole pairs. Under the action of an external bias voltage field, the electron and hole pairs move in opposite directions to form a current, and form a stored charge on the internal node capacitance of the pixel circuit. . Corresponding to the dose of incident X-rays, each detection pixel has a corresponding amount of stored charge, and the charge amount of each pixel can be known through the readout circuit, and then the X-ray dose corresponding to each pixel can be detected. For the indirect X-ray detection system, a PIN photodiode is used as the photosensitive unit, and a-Si TFT is used to make a switch array to read out the photoelectric signal. The structure of the indirect X-ray imager includes a scintillation crystal layer, and an array layer composed of PIN diodes and a-Si TFTs. Its working process is divided into two steps. First, the X-ray is converted into visible light through the scintillation crystal layer, and then the visible light is converted into an electrical signal through a PIN diode and read out through the a-Si TFT array (hereinafter referred to as the detector is an indirect type a. -Si flat panel detector). In the above two schemes, since the direct-type a-Se flat panel detector directly detects the X-ray dose, the a-Se layer and the a-Si TFT layer are a three-dimensional stacked structure, and the a-Se layer needs to be applied thousands of times when it works normally. The high voltage of volts is relatively harsh, so the direct type a-Se flat panel detector has high requirements on the working environment, short life, high failure rate, and the maintenance cost is much higher than that of the indirect type a-Si flat panel detector. In contrast, indirect a-Si flat panel detectors have a wider range of applications.

Whether direct or indirect, high-quality flat-panel imagers are always inseparable from TFT technology. With the continuous development of large-area flat-panel imaging panels and increasing requirements, a-Si TFT is increasingly unsuitable for flat-panel imaging technologies such as high resolution and high refresh frame rate. For direct-type a-Se flat panel detectors, the ultra-high voltage working environment is not conducive to the normal operation of a-Si TFT arrays, and the principle and structure of the TFT technology application itself is limited; in addition, a-Si TFT has unstable electrical properties and Disadvantages such as low mobility also limit many performance improvements for indirect a-Si flat panel detectors. First of all, in terms of process, a-Si TFT adopts thin-film transistor process technology, which is two independent and serial processes with that of PIN diode. This special-shaped integrated image sensor panel has defects such as high process complexity, high manufacturing cost, high difficulty in mass production, and low yield rate. Secondly, studies have shown that although the presence of intermediate layer scintillation crystals will lose a certain detection quantum efficiency (DQE) in indirect a-Si flat panel detectors, the DQE of direct a-Se flat panel detectors depends on the level of DQE. Due to the ability of the a-Se layer to generate charges, in general, the limit DQE of the direct a-Se flat panel detector is still lower than the limit DQE of the indirect a-Si flat panel detector, so the photoelectric sensor a-Se or PIN diode DQE also has an improvement range, and it may try to break through from new photoelectric sensors. Furthermore, the mobility of a-Si TFT is relatively low, in the order of 1 cm ² /(Vs), in order to maintain a certain driving capability, a-Si TFT needs to have a larger size (ie, the aspect ratio of the device W/ L value is larger). Therefore, the larger size of the a-Si TFT limits the further improvement of the spatial resolution of the X-ray imaging panel. For example, it is difficult for a single pixel area of a traditional indirect a-Si flat panel detector to be less than 100μm*100μm. As the spatial resolution increases, the number of rows on the panel will increase. Under a certain refresh frame rate, the readout time of each row needs to be shortened accordingly. However, the low mobility of a-Si TFTs also makes it more and more difficult to shorten the readout time per row, so it is difficult to increase the refresh frame rate (>30Hz).

With the in-depth research of Metallic Oxide Thin Film Transistor (MOTFT) and the greatly improved low temperature polycrystalline silicon oxide (Low Temperature Polycrystalline Oxide, LTPO) technology level, related research findings and experimental tests have shown that the metal oxide film with higher mobility MOTFT also has better photoelectric response characteristics. Here, typical metal oxide thin film transistors include amorphous indium gallium zinc oxide (AmorphousInGaZnO, a-IGZO), zinc tin oxide (Zinc Tin Oxide, ZTO) and the like. Moreover, the MOTFT itself is based on the same flat film technology as the readout array TFT. In summary, the MOTFT technology has the possibility of making a photoelectric sensor. It is combined with the readout array TFT to form a flat panel composed of all TFTs in the array. The detector has feasibility and development potential. Compared with the above-mentioned indirect a-Si flat panel detection technology, using MOTFT as the photoelectric sensor will reduce the complexity, difficulty and cost of the process, and improve the yield. However, it should be noted that if thin film transistors are used to make photoelectric converters, several problems will be introduced.

The first problem is that compared with the above-mentioned a-Se or PIN diode, the thin film transistor has three pins. Compared with the previous two, a single pixel needs to introduce an additional signal line. Considering the layout, the increase of pixel signal lines will further reduce the pixel area and effectively use the space, which is not conducive to the improvement of the spatial resolution of the detector.

The second problem is that the preparation of the photosensitive cell TFT and the readout array TFT is completed by the same set of thin film processes, that is, the preparation processes of the photosensitive cell and the readout array are parallel. The photosensitive photosensitive unit TFT and the readout array TFT are two-dimensional structures in the same plane. Compared with the above traditional solutions, whether it is an indirect type or a direct type, the photosensitive unit a-Se or PINdiode and the readout array TFT are both. A three-dimensional structure stacked on top of one another. From this point of view, the photosensitive unit TFT, which is a photoelectric converter, cannot completely fill the entire pixel area, and the fill factor is not as high as that of the traditional structure scheme.

The third problem is that MOTFT has a high photoelectric response and often also has a persistent photoconductivity (PPC) effect, that is, at the stage after the application of illumination, the response of the photoelectric sensor should quickly recover as the illumination is removed. The state before receiving the light, there is no response output. The existence of the PPC effect will make the photosensitive unit still maintain the photoelectric response when receiving the light in the stage after the light is removed. The specific performance takes MOTFT as an example. Under the bias of a certain gate electrode source electrode voltage, when the MOTFT is not exposed to light, the current between the drain electrode and the source electrode is extremely small. In the order of 10 ^-12 AA, the resistance is very small. large, approximately off. When exposed under this bias, the current between the drain electrode and the source electrode will increase rapidly and maintain at the order of 10 ^-6 A, and the resistance will decrease. The state of current large resistance, but will continue for a period of time. Therefore, based on the pixel circuit of the traditional direct type a-Se scheme or the indirect type a-Si scheme, the photoelectric converter cannot be simply replaced by a-Se or PIN diode directly with MOTFT, because when the light is removed, the PPC effect The induced photo-generated charge will continue to change, and the collected photoelectric signal will be affected by the historical state and cause distortion, so that the function of the entire pixel circuit will fail and need to be redesigned.

To sum up, in view of the optoelectronic properties of oxide TFT or low temperature polysilicon oxide TFT, it is necessary to reconsider a new type of image sensing pixel circuit and its readout method to improve the resolution and sensitivity of flat-panel image sensing arrays, thereby reducing X radiation dose, or image sensing at lower intensities of input light. However, there is no pixel circuit or pixel array designed for oxide TFTs in the prior art.

SUMMARY OF THE INVENTION

The present application provides a phototransistor with photoresponse, comprising a layer-by-layer substrate, a bottom gate electrode, a bottom gate dielectric layer, an active layer, a top gate dielectric layer, and a top gate electrode; wherein the active layer includes A semiconductor material with optical memory function, comprising channel and source-drain regions in the active layer; wherein in the illumination stage and the integration stage, the voltages of the bottom gate electrode and the top gate electrode of the phototransistor are different, and the voltage of the bottom gate electrode and the top gate electrode of the phototransistor are different, and the The phototransistor is in an off-state working region; the integration stage includes at least a first preset time period after exposure is completed; wherein the semiconductor material with optical memory function includes a metal oxide semiconductor.

In particular, in the reset phase, the voltages of the bottom gate electrode and the top gate electrode of the phototransistor make the phototransistor in an on-state operating region.

Particularly, the phototransistor further includes a passivation layer at least on the top gate electrode, and a scintillator on the passivation layer and the source and drain regions.

The present application also provides a method for light-sensing using a double-gate phototransistor, wherein the active layer material of the double-gate phototransistor includes a material with a photo-memory function, and the method includes: irradiating the double-gate phototransistor during an illumination stage. Expose, cancel the illumination in the subsequent integration stage, apply different potentials to the bottom gate electrode and the top gate electrode of the dual-gate phototransistor during the entire illumination stage and the integration stage, and keep the dual-gate phototransistor in an off state In the working area, the integration stage includes at least a first preset time after the exposure ends, and the semiconductor material with optical memory function includes a metal oxide semiconductor.

In particular, the method further includes applying voltage to the bottom gate electrode and the top gate electrode of the double-gate phototransistor during the reset phase, so that the double-gate phototransistor is in an on-state working region.

The present application also provides an image sensor array including a readout circuit, a gate drive circuit and a bias circuit, and a pixel array coupled thereto including a phototransistor as described above.

Description of drawings

FIG. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present application;

FIG. 2 is a schematic diagram of the variation of the integral current of the line driving signal and the photosensitive unit in a frame period;

FIG. 3 is a schematic structural diagram of a pixel circuit according to another embodiment of the present application;

FIG. 4 is a schematic structural diagram of a pixel array according to an embodiment of the present application;

FIG. 5 is a schematic structural diagram of a pixel array according to another embodiment of the present application;

6 is a schematic diagram of the pixel circuit structure of X-ray imaging based on LTPO TFT process;

FIG. 7 is a schematic diagram of the timing sequence of driving signals of each row of the pixel array and the corresponding working stages according to an embodiment of the present application;

FIG. 8 is a schematic diagram of the action of the driving pulses of each row of the pixel array on the pixel circuit of each row according to the embodiment of the present application;

FIG. 9 is a schematic diagram of a working phase sequence diagram of a pixel array according to an embodiment of the present application;

FIG. 10 is a schematic diagram of a working sequence of a pixel array not using an embodiment of the present application;

11 is a cross-sectional view of a pixel circuit process according to an embodiment of the present application;

FIG. 12 is a schematic diagram of the connection relationship of the pixel circuit shown in FIG. 6;

FIG. 13 is a transient output waveform diagram during simulation of a pixel circuit according to an embodiment of the present application.

Detailed ways

The present invention will be further described in detail below through specific embodiments in conjunction with the accompanying drawings. Wherein similar elements in different embodiments have used associated similar element numbers. In the following embodiments, many details are described so that the present application can be better understood. However, those skilled in the art will readily recognize that some of the features may be omitted under different circumstances, or may be replaced by other elements, materials, and methods. In some cases, some operations related to the present application are not shown or described in the specification, in order to avoid the core part of the present application from being overwhelmed by excessive description, and for those skilled in the art, these are described in detail. The relevant operations are not necessary, and they can fully understand the relevant operations according to the descriptions in the specification and general technical knowledge in the field.

Additionally, the features, acts, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can also be exchanged or adjusted in order in a manner obvious to those skilled in the art. Therefore, the various sequences in the specification and drawings are only for the purpose of clearly describing a certain embodiment and are not meant to be a necessary order unless otherwise stated, a certain order must be followed.

The serial numbers themselves, such as "first", "second", etc., for the components herein are only used to distinguish the described objects, and do not have any order or technical meaning.

The transistor in this application includes at least three terminals, and the three terminals are a control electrode, a first electrode and a second electrode. The transistors may be bipolar transistors, field effect transistors, or the like. For example, when the transistor is a bipolar transistor, its control electrode refers to the base electrode of the bipolar transistor, the first electrode can be the collector or emitter of the bipolar transistor, and the corresponding second electrode can be the bipolar transistor. When the transistor is a field effect transistor, its control electrode refers to the gate of the field effect transistor, the first electrode can be the drain or source of the field effect transistor, and the corresponding second electrode can be the field effect transistor. The source or drain of an effect transistor.

The present application provides a pixel circuit, which includes a photosensitive unit. The photosensitive unit is a phototransistor with photoelectric response. The photosensitive unit has a memory (storage) function, and the photo-generated current remains in the photosensitive unit even after the incident light is removed. At the same time, the memory effect of the phototransistor can be erased by applying high gate voltage pulses. The pixel circuit further includes a storage unit, which is coupled to the photosensitive unit, and is configured to convert the photogenerated current generated by the photosensitive unit into a first electrical signal (specifically, a photogenerated charge or a photogenerated voltage) during the integration stage and store or maintain, wherein the integration is performed. The stage includes at least a preset time period after the exposure stage ends. The photoelectric sensor pixel also includes a readout unit, which is coupled to the storage unit. In the signal readout phase, through the cooperative control of the signal lines, the photogenerated charges stored in the storage unit in the integration phase are transferred to the off-chip system for further readout processing. .

Further, the photosensitive unit of the present application uses a transistor with photoresponse to replace the traditional photodiode, and the structure of the image sensing array is improved by the emerging low temperature polysilicon oxide (LTPO) process, so that the new image sensing pixel and array have more advantages. Fast response speed, higher imaging resolution, and larger dynamic range. Compared with the traditional imaging array combining the structure of photodiode and thin film transistor, the pixel circuit of the present application uses the same set of thin film process to simultaneously complete the fabrication of the photosensitive unit and the switch array at one time, and has more mature process compatibility, more flexibility. Low cost and greater development potential.

The present application proposes a pixel array, in which driving signal lines of the same type of multiple pixel circuits in the same row in the array are connected to one input signal line, and multiple pixel circuits in adjacent rows are multiplexed with one row scan line to simultaneously receive The driving signal enables the parallel operation of the photoelectric signal integration stage, the readout stage and the clear storage memory stage of the pixels in different rows, and the hardware layout space is saved at the same time. The output ends of the pixel circuits in the same column are connected together to output the first electrical signal at the same time, which improves the output efficiency.

Example 1:

Referring to FIG. 1 , this embodiment provides an image sensor pixel circuit. As shown in FIG. 1 , the pixel circuit includes a photosensitive unit 21 , a storage unit 22 and a readout unit 23 .

Wherein, the photosensitive unit 21 is used for receiving incident light exposure to generate a photoelectric signal, and the photoelectric signal generated by the photosensitive unit can still be maintained for a first preset time after the light is removed; the storage unit 22 is coupled to the photosensitive unit 21, and the storage unit 22 is used for storing the photoelectric signal in the integration stage to obtain the first electrical signal, and the integration stage at least includes the first preset time after the exposure ends. The readout unit 23 is coupled to the storage unit 22 , and the readout unit 23 is used for outputting the first electrical signal stored in the storage unit 22 . Among them, a working cycle of the pixel circuit can be divided into four working stages, namely: a reset stage, an illumination stage, an integration stage and a readout stage. The function of the photosensitive unit 21 is that the off-state current of the device is changed by the light intensity, and the conductance characteristic of the device is changed and maintained for a period of time. The function of the unit 22 is to store the photoelectric signal to obtain the first electrical signal. For example, the storage unit 22 stores the variation of the charge on the capacitor plate, or the storage unit 22 stores the jump of the voltage signal; The first electrical signal stored on 22 is read out, and the first electrical signal may be a voltage signal changed on the capacitance converted into a voltage signal or a current signal.

Among them, the photosensitive unit 22 is modulated by the reset signal, and the reset signal of the photosensitive unit 22 is a non-enable potential in the stage of receiving incident light; and when entering the reset stage, the reset signal of the photosensitive unit 22 is an enable level.

The readout unit of this embodiment includes a first transistor TN-1 and a second transistor TN; the photosensitive unit includes a third transistor TN+1, and the storage unit includes a storage capacitor Cs. The first pole of the third transistor is connected to the preset bias voltage Vref, the second pole of the third transistor is connected to the first pole of the first transistor TN-1, the second pole of the first transistor is connected to the first pole of the second transistor, The output end of the second pole of the second transistor is used for outputting the first electrical signal stored in the storage unit; the control pole of the third transistor is connected to the second pole of the first transistor through a storage capacitor. Among them, the third transistor TN+1 is a transistor with photoelectric response, and its categories include metal oxide semiconductor field effect crystal (MOSFET), thin film transistor (TFT) and other devices. The third transistor will be exposed to incident light. Generates a photoelectric signal (specifically, a photogenerated current), and has a memory memory function, that is, the photoelectric signal is still maintained for the first preset time in the stage after the incident light is removed, and the conductivity of the photosensitive unit 21 changes significantly after receiving the illumination, and the illumination changes significantly. After the removal, the off-state current of the third transistor TN+1 is still larger than the off-state current before illumination.

The storage unit 22 is coupled to the photosensitive unit 21, and is configured to convert the photoelectric signal (ie, photo-generated current) into photo-generated charge or photo-generated voltage and store or maintain it in an integration stage, wherein the integration stage at least includes a first preset after the exposure stage ends period. The readout unit 23 is coupled to the memory unit 22, which is controlled by the coordination of the signal lines in the signal readout stage, and transfers the photogenerated charges stored in the memory unit 22 in the integration stage to the off-chip system for further processing and readout.

The application provides a photoelectric sensor pixel circuit, the photoelectric sensor pixel circuit includes a photosensitive unit 21, the photosensitive unit 21 can be said to be a transistor with photoelectric response, and its function is to generate a photogenerated current of corresponding intensity after receiving incident light exposure, And has a memory function, even after the incident light is removed, the photosensitive unit 21 still maintains the photo-generated current; at the same time, the memory effect of the phototransistor can be erased by applying a high gate voltage pulse. The photosensor pixel circuit further includes a storage unit 22, which is coupled to the photosensitive unit 21, and is used for converting the photo-generated current into photo-generated charge or photo-generated voltage and storing or maintaining it in the integration stage, wherein the integration stage includes the photo-generated current after the exposure stage ends. the first preset time period. The photoelectric sensor pixel circuit also includes a readout unit 23, which is coupled to the storage unit 22. In the signal readout phase, through the cooperative control of the signal lines, the photogenerated charges stored in the storage unit 22 in the integration phase are transferred to the off-chip system and further processed. readout processing.

A first driving signal line G[N-1] is connected to the control electrode of the first transistor TN-1, and the first driving signal line G[N-1] is used to receive a corresponding control signal to turn on the first transistor TN -1, so that the first transistor TN-1 and the third transistor TN+1 are turned on through the storage capacitor Cs, so that the storage capacitor Cs integrates the photoelectric signal to obtain the first electrical signal. A second driving signal line G[N] is connected to the control electrode of the second transistor TN, and G[N] is used to receive a corresponding control signal to turn on the second transistor TN and convert the first electrical signal on the storage capacitor from the second Output on the second pole of transistor TN. A third driving signal line G[N+1] is connected to the control electrode of the third transistor, and G[N+1] is used to receive a corresponding control signal to eliminate the photoelectric signal generated when the third transistor TN+1 is exposed to make it Returns to the conductance state it was when it was not exposed to light.

Further, the readout unit 23 also includes an operational amplifier D1, a first capacitor C1 and a first switch S1; the second pole of the second transistor TN is connected to the negative input terminal of the operational amplifier, and the positive input terminal of the operational amplifier D1 is connected to preset reference level; one end of the first capacitor C1 is connected to the negative input end of the operational amplifier D1, and the other end is connected to the output end of the operational amplifier D1; one end of the first switch S1 is connected to the negative input end of the operational amplifier D1, and the other end is connected to the negative input end of the operational amplifier D1. One end is connected to the output end of the operational amplifier D1 ; the output end of the operational amplifier D1 is used to output the first electrical signal on the storage unit 2 . This embodiment utilizes the virtual short and virtual off performance of the operational amplifier D1 to implement the integral operation on the photo-generated current/charge.

In one embodiment, the first transistor TN-1 and the second transistor TN are field effect thin film transistors; the third transistor TN+1 is a metal oxide semiconductor field effect transistor or a thin film transistor.

In an embodiment, as shown in FIG. 3 , the first transistor TN-1, the second transistor TN and the third transistor TN+1 are all double-gate oxide thin film transistors. Among them, the two gates of the first transistor TN-1 are short-circuited, the two gates of the second transistor TN are also short-circuited, one gate of the third transistor TN+1 is used to receive the light signal, and the other gate is The control electrode is connected to the second electrode of the first transistor TN-1 through the storage capacitor TN+1. The two gates of the first transistor TN-1 and the second transistor TN are shorted together, which can improve the switching performance. The two gates of the third transistor TN+1 for photodetection are individually biased, and the photoelectric conversion efficiency of the third transistor TN+1 can be maximized by proper biasing of the other gate C[N-1]. More preferably, take C[N-1] as the pulse signal of high voltage VC and low voltage as VGL; G[N-1] be the pulse signal of high voltage VGH and low voltage VGL, where VGL<VC<VGH, and VC-VGL is about Equal to VTH0, VTH0 is the threshold voltage of the double gate oxide thin film transistor.

In one embodiment, the first transistor and the second transistor are field effect thin film transistors, and the third transistor is a metal oxide semiconductor field effect transistor; as shown in FIG. 11 , in one embodiment, the second transistor and the third transistor The second transistor is made in one piece by LTPO process, and the second transistor includes a substrate 1101, a buffer layer 1102, a polysilicon layer 1103, a first gate electrode layer 1105, a first source-drain electrode layer 1111, a second source-drain electrode layer 1112 and a first insulating dielectric layer 1107; the buffer layer 1102 is formed on the substrate 1101, the polysilicon layer 1103 is arranged on the upper layer of the buffer layer 1102, the first gate electrode layer 1105 is arranged on the upper layer of the polysilicon layer 1103 and is insulated from the polysilicon layer 1103, and the first insulating medium layer 1107 is arranged On the upper layer of the first gate electrode layer 1105, the first source-drain electrode layer 1111 and the second source-drain electrode layer 1112 are respectively arranged on both sides of the gate electrode layer 1105 and are insulated from the gate electrode layer 1105 by the first insulating medium layer 1107 ; The third transistor includes a first insulating dielectric layer 1109, a second insulating dielectric layer 1104, a second gate electrode layer 1106, a third gate electrode layer 1108, a metal oxide layer 1110, a third source-drain electrode layer 1113, a fourth source The drain electrode layer 1114, the second insulating dielectric layer 1104 are disposed on the buffer layer 1102, the second gate electrode layer 1106 is disposed on the second insulating dielectric layer 1104, and the third gate electrode layer 1108 passes through the first insulating dielectric layer 1107 is provided on the second gate electrode layer 1106 and is insulated from the second gate electrode layer 1106, the first insulating dielectric layer 1109 is provided on the upper layer of the third gate electrode layer 1108, and the metal oxide layer 1110 is provided on the first insulating dielectric layer On 1109 , the third source-drain electrode layer 1113 and the fourth source-drain electrode layer 1114 are respectively disposed on both sides of the metal oxide layer 1110 . The polysilicon layer 1103 , the first gate electrode 1105 , the first source-drain electrode layer 1111 , the second source-drain electrode layer 1112 , and the second insulating dielectric layer 1104 together constitute the low-temperature polysilicon thin film transistor device 1115 . The metal oxide 1110, the third gate electrode layer 1108, the third gate electrode layer 1108, the fourth source-drain electrode layer 1114, and the first insulating dielectric layer 1109 together constitute the metal oxide thin film transistor device 1116. The second gate electrode layer 1106, the third gate electrode layer 1108, and the first insulating dielectric layer 1107 together constitute a metal-insulator-metal (MIM) capacitor 1117, wherein the upper plate of the capacitor 1117 is connected to the MOTFT The third gate electrode layer 1108 is the same layer of metal, and the second gate electrode layer 1106 is connected to the LTPS TFT through the second source and drain electrode layer 1112, thereby completing the structure shown in FIG. 6. The source and drain electrodes of the LTPS TFT are connected to the Electrical connection relationship of MOTFT gate.

In another embodiment, the fabrication of the second transistor and the third transistor is not limited to the LTPO (polysilicon and oxide) process, and a hybrid TFT integration process may actually be used. For example, a mixed integration process of LTPS (polysilicon) TFT and MO-TFT (metal oxide thin film transistor) can be used, a mixed integration process of LTPS-TFT and a-Si TFT can also be used, or LTPS (polysilicon) TFT and organic TFT hybrid integration process, etc. For example, the hybrid integration process of LTPS TFT and a-SiTFT, since amorphous silicon TFT also has better photoelectric effect, and both LTPS TFT and a-Si TFT are based on silicon material system, the compatibility of this process is higher.

The image sensing array of the present invention is realized by a hybrid TFT integrated circuit process, and the hybrid TFT integrated circuit process here is not limited to the LTPO process, that is, metal oxide TFTs are not necessarily used for photosensitive TFTs. In addition to the LTPS TFT as the charge amplification and readout device and the metal oxide as the photosensitive device, it is also possible to use the LTPS TFT as the charge amplification and readout device, the amorphous silicon TFT as the photosensitive device, or the LTPS TFT as the charge amplification And readout devices, organic TFTs as photosensitive devices, etc. The reasons for using LTPS TFT as the charge amplification and readout device and amorphous silicon TFT as the photosensitive device include that amorphous silicon also has a better photoelectric effect, and the material system and process compatibility of amorphous silicon TFT and LTPS TFT are relatively high.

Fig. 12 illustrates the circuit connection relationship between the LTPS TFT, Cs and MOTFT of the structure shown in Fig. 6, corresponding to the schematic cross-sectional view of the process in Fig. 11, the LTPS TFT1201 corresponds to the LTPS TFT (thin film transistor device) 1115 of Fig. 11, the MOTFT1203 corresponds to the MOTFT1116 of Fig. 11, The capacitor Cs1202 corresponds to the capacitor Cs1117 in FIG. 11 . Comparing Fig. 11 and Fig. 12, it is worth pointing out that due to the relatively high mobility of LTPS TFT, its device size can be made relatively small; while the mobility of metal oxide TFT is relatively low, and its device size is generally larger. , occupying a larger area of the layout. In addition, the value of the capacitance in the image sensing pixel circuit is generally larger, otherwise it is not easy to collect enough photo-generated charges within a limited exposure time. Therefore, the capacitor also occupies a larger layout area. The advantage of the design of this embodiment is that the metal oxide TFT is used as the photoelectric sensor, so the larger the area of the metal oxide TFT, the higher the fill factor of the photoelectric sensor pixel circuit. At the same time, the capacitor is formed at the bottom of the metal oxide TFT. With the larger area of the metal oxide TFT, the value of the capacitor can naturally be made larger. Therefore, in general, the polysilicon-metal oxide hybrid TFT integrated pixel circuit has better photoelectric conversion capability, and may realize an image sensor with higher spatial resolution.

Compared with the traditional imaging array combining the structure of photodiode and thin film transistor, the pixel circuit of the present application uses the same set of thin film process to simultaneously complete the fabrication of the photosensitive unit 21 and the switch array at one time, and has more mature process compatibility, more flexibility. Low cost and great development potential.

Embodiment 2

As shown in FIG. 6 , this embodiment provides an image sensor pixel circuit for X-ray imaging based on the LTPO TFT process. The pixel circuit includes a photosensitive unit, a storage unit and a readout unit; wherein the photosensitive unit includes a photoelectric conversion device TN+1, the storage unit includes an integral switching device TN-1, and the readout unit includes a readout switching device TN and an integrating capacitor CS. The conversion device TN+1 is an N-type device, composed of metal oxide TFT, such as IZO TFT (oxide thin film transistor); the integration switching device TN-1 and the readout switching device TN are P-type devices, composed of LTPS TFT; The first terminal of the capacitor CS is connected to the gate of TN+1 and its second terminal is connected to the source of TN-1. The gate of TN+1 is connected to the exposure control signal Gph, its drain is connected to the reference voltage source Vref, and its source is connected to the drain of TN-1. The gate of TN-1 is connected to the integration control signal Gint, and its source is connected to the drain of TN. The gate of TN is connected to the readout control signal Gread, and its source is connected to an external amplifier.

The advantages of the LTPO TFT X-ray pixel circuit provided in this embodiment as shown in FIG. 6 are:

1) The photoelectric sensitivity of metal oxide TFT is significantly higher than that of LTPS TFT, especially in the blue-violet band; while LTPS TFT has higher mobility and stronger device reliability. Therefore, the circuit can not only take advantage of the high photoelectric sensitivity and low leakage current of the metal oxide TFT, but also take advantage of the strong driving ability and fast response speed of the LTPS TFT. Such an image sensor may significantly reduce the dose of X-rays when used for X-ray imaging. In other words, even if the peripheral light input intensity is weak, it can image well, so it has unique advantages for high-resolution imaging of weak light input.

2) LTPO is a three-dimensional integrated X-ray photosensitive panel structure. After the process integration of LTPS TFT and capacitive elements is completed, a metal oxide TFT for photosensitive is formed at a lower processing temperature and integrated on the LTPS TFT array. . As a result, almost the entire pixel has the function of X-ray sensing. This is beneficial to reduce the radiation dose of X-rays and improve the efficiency of photoelectric conversion. At the same time, due to the three-dimensional integrated structure, the spatial resolution of this X-ray image sensing array is high, and the size of the unit pixel may be small.

Embodiment 3

This embodiment provides an image sensing array, as shown in FIG. 4 , the pixel array includes a plurality of pixel circuits as provided in the first embodiment, and the plurality of pixel circuits are arranged in the form of four rows and four columns, that is, a plurality of pixel circuits are composed of 4X4 pixel array. The multiple pixel circuits in this embodiment are connected in the form of multiplexed scan lines, so as to reduce the overall circuit arrangement of the pixel array. The first driving signal lines G[N-1] of the plurality of pixel circuits in each row are connected to the first input signal lines to input the same driving signal, and the second driving signal lines of the plurality of pixel circuits in each row are connected to the first input signal line to input the same driving signal. G[N] are all connected to the second input signal lines to input the same driving signal; the third driving signal lines G[N+1] of the plurality of pixel circuits in each row are all connected to the third input signal lines to input the same driving signal drive signal.

The second electrodes of the second transistors of the plurality of pixel circuits in each column are connected to the same signal output line, and the signal output line is used to output the first electrical signal of each pixel circuit; The driving signals input on the first input signal lines connected to the plurality of pixel circuits are the same as the driving signals input on the second input signal lines in the previous row; the second input signal lines connected to the plurality of pixel circuits in each lower row are the same The input driving signal is the same as the driving signal input on the third input signal line in the previous row.

Further, as shown in FIG. 5 , the pixel array further includes a readout circuit, a gate drive circuit and a bias circuit. The readout circuit is connected with the signal output lines of the plurality of pixel circuits in each column; the gate driving circuit is respectively connected with the first driving signal line, the second driving signal line and the third driving signal of the pixel circuits in each row through a plurality of row scanning lines. Line connection; the first electrodes of the third transistors of the plurality of pixel circuits in each column are connected to the bias circuit through the column scan line, and the bias circuit is used to input the same bias voltage uniformly. 4, it can be seen that the pixel array in this embodiment shares a set of gate driving circuits, and the G[N] signal is multiplexed between the N-1th row, the Nth row, and the N+1th row, and the structure is simple. The complexity of the peripheral drive circuit is not increased. Wherein, the gate driving circuit can be formed of the same oxide TFT (thin film transistor) as that in the image sensor array, and it is not necessary to increase the overhead of additional gate driving IC design. The bias circuit provides the Vref voltage to the drain of the phototransistor in each pixel. Considering the leakage current of each pixel, and the possible large photo-generated current when the same row of pixels is simultaneously photosensitive and read out, the bias circuit should have a strong voltage regulation capability.

The specific working stages of the pixel array are divided into reset stage, illumination stage, integration and readout stage. The high-level state of all row drive signals is VH, the low-level state is VL, the reference level of the non-inverting input terminal of the operational amplifier and the bias of the initial level of the on-chip pixel circuit are both Vref.

As shown in FIG. 2, in the T1 reset stage, both the photosensitive unit 21 and the readout unit 23 are in the open state, that is, the first transistor TN-1, the second transistor TN, and the third transistor TN+1 are all in the open state. Capacitor Cs is biased to an initial state, and its stored charge is Q ₀ .

Q ₀ =C _s ·(V _ref -VH)

T2 is the illumination/exposure stage: after illumination, the conductivity of the third transistor TN+1 of the photosensitive unit 21 changes, and this state can be maintained until the next high level of the gate voltage arrives.

The integration and readout stage includes a high-level pulse stage as shown in i-xi in Figure 2. As shown in Figure 2, when the high-level pulse of the gate drive line of row G[0] in the i stage arrives, the first row The TN-1 tube is turned on. Since the conductance of the photosensitive unit TN+1 tube in this row has changed, the light intensity information is stored. When the TN-1 tube is turned on, Vref passes through the TN-1 and TN+1 tubes, and the corresponding current will flow. , as shown by Iph[1] in the i stage, this will charge and discharge the memory cell 22, changing the amount of charge Q' on Cs, after this stage the amount of charge on Cs is Q1.

Q ₁ =Q ₀ -Q'

In stage ii, when the high-level pulse of the gate drive line of row G[1] arrives, the TN tube of the readout unit 23 in the first row is turned on, and the charge on Cs of the storage unit 22 is transferred out through the TN tube and the external ROIC, The amount of charge on Cs after this stage is Q2.

Q ₂ =C _s ·(V _ref -VL)

The amount of charge transferred out is ΔQ.

ΔQ=Q ₂ −Q ₁ =C _s ·(VH-VL)+Q′

At the same time, in stage ii, the high-level pulse of the gate drive line of G[1] also turns on the TN-1 tube of the second row, forming an integral path for the Vref, TN+1, and TN-1 tubes of the second row, and there is current Flow through, as shown by Iph[2] in stage ii, changes the charge stored on Cs of the memory cells 22 of the second row. In stage iii, the high-level pulse of the gate drive line (ie, the row scan line) of the G[2] row arrives, and the charge of the memory cell 22 in the second row is transferred out like the first row. At the same time, the G[2 ] The high-level pulse of the row gate drive line also integrates the next row (third row), as shown in stage iii Iph[3], and also stores the TN+1 of the photosensitive cell 21 in the previous row (first row) at the same time. The photoelectric information is eliminated. By analogy, in the v stage, the high level of the G[N-1] gate line eliminates the photoelectric information stored in the photosensitive unit 21 of the N-2 row, and performs the photoelectric integration of the readout unit 23 of the N-1th row. Transfer readout, integrate the storage unit 22 of the Nth row; in the vi stage, the high level of the G[N] gate line eliminates the photoelectric information stored in the photosensitive unit 21 of the N-1 row, and the readout unit 23 of the Nth row is performed. Integrate the photoelectric integral of the N+1 row for transfer and readout, integrate the photoelectric signal on the storage unit 22 in the N+1th row... and proceed in this way, converting the light intensity information sensed by the entire panel into charge (voltage) information for readout.

After being illuminated, the conductance of the photosensitive unit 21 (ie, the phototransistor) in this embodiment will change and last for a period of time, so the photoelectric information generated by the photosensitive unit 21 is used to describe it (this is also called the continuous photoconductive effect, persistent photo-conduct PPC), it takes a long time for the conductance of the phototransistor to return to its original state, or a positive voltage pulse is applied to the gate of the phototransistor, so that the conductance state of the phototransistor will return to the original unacceptable state The state of lighting. Please refer to FIG. 4 , FIG. 7 and FIG. 8 , the G[n] line pulses in this embodiment are used to eliminate the photoelectric signals stored in the photosensitive cells 21 of the N−1 line. The difference is two different signals. The G[n-1] line pulse signal also has three functions. First, the G[n-1] line pulse signal has two effects on the phototransistor in the N-2th row (the photosensitive cell TN+1 transistor in the N-2th row) Second, the G[n-1] line pulse signal turns on the readout unit 23 transistor (the readout tube TN of the N-1th line) of this line (N-1 line), and the current line ( The stored first electrical signal on the storage capacitor Cs in the N-1th row) is output to the peripheral readout unit 23; The transistor (TN-1) forms a path between the storage capacitor Cs and the photosensitive unit 21 (TN+1), and uses the change of the photoconductivity of the photosensitive unit 21 to integrate the charge on Cs to form the conversion of the light intensity signal to the voltage signal. The first electrical signal is obtained. That is: The G[n] line pulse signal also has three functions. First, the conductance of the G[n] line pulse signal to the phototransistor of the N-1th row (the photosensitive cell TN+1 transistor of the N-1th row) Second, the G[n] line pulse signal turns on the readout cell transistor (the readout transistor TN of the Nth line) in this line (Nth line), and the memory cell 22 of this line (Nth line) is turned on. The stored voltage information is read out in conjunction with the peripheral readout unit 23; thirdly, the G[n] line pulse signal turns on the transistor (TN-1) of the next line (the N+1th line), and the memory unit 22 communicates with the photosensitive A path is formed between the units 21, and the change of the photoconductivity of the photosensitive unit is used to integrate the charge on the Cs to form the conversion of the light intensity signal to the voltage signal. Similarly, the G[n+1] line pulse signal also has three functions. First, the G[n+1] line pulse signal has three effects on the phototransistor in the Nth row (the photosensitive cell TN+1 transistor in the Nth row). The conductance state is reset; secondly, the G[n+1] row pulse signal turns on the transistor (transistor TN in the N+1th row) of the readout unit 23 in this row (N+1 row), and turns on the current row (N+1 row transistor TN). The voltage information stored on the memory cell Cs of the +1 row) is read out in conjunction with the peripheral readout unit 23; thirdly, the G[n+1] row pulse signal turns on the transistor ( TN-1), a path is formed between the storage unit 22 and the photosensitive unit 21, the charge on Cs is integrated by the change of the photoconductivity of the photosensitive unit 21, and the conversion of the light intensity signal to the voltage signal is formed to obtain the first electrical signal.

FIG. 2 is a schematic diagram of a time sequence diagram of a row driving signal and a corresponding change of the integrated current of the transistor of the photosensitive unit 21 in a frame period of the pixel array of M rows. Wherein, I _ph [i] represents the integrated current of the transistors of the photosensitive unit 21 in the i-th row during the detection period of one frame. G[i] represents the row drive signal of the transistor of the readout unit 23 in the i-th row. T1 represents the initial reset phase within a frame detection period. T2 represents the exposure stage within a frame detection period. i, ii, iii, .

Please refer to FIG. 7 , which shows the row driving signals G[N], G[ of the pixel array with the parallel pipeline structure proposed in the present application in the Nth row, the N+1th row, and the N+2th row in the readout stage. N+1], G[N+2] timing, T _N represents the readout phase of the pixel circuit in the Nth row, and Treset _N represents the reset phase of the off-chip readout circuit after the pixel in the Nth row is readout.

FIG. 8 illustrates the function and state transition of the pixel array of the parallelized pipeline structure proposed in the present application. Referring to FIG. 7, the adjacent gate drive signals G[N], G[N+1], G[N +2] The three pulses respectively undertake the actions of photoelectric signal integration, photoelectric signal readout, and photoelectric memory effect elimination of the pixel circuit in the N+1 row, and fulfill the above functional requirements of the pixel circuit in the N+1 row by time periods. Vertically, a single gate drive signal G[N] pulse simultaneously completes the photoelectric memory erasing action of the pixel circuit in the N-1 row, the photoelectric signal readout action of the pixel circuit in the Nth row, and the pixel circuit in the N+1 row. The photoelectric signal integration action is performed simultaneously, and the above-mentioned functional requirements of the pixel circuits of three adjacent rows in space are fulfilled at the same time.

The advantages of the parallelized pipeline readout drive timing shown in FIG. 8 applied to the pixel circuit structure of the present application are as follows:

1) When MO-TFT (Metal Oxide Thin Film Transistor) is used for photodetection, if MO-TFT is used for photoelectric signal integration in the stage of receiving light, the PPC effect becomes a negative influence, and some structures need to be added to eliminate interference. , which requires an additional set of timing controls. If the photoelectric signal integration is performed by using the PPC effect of the MO-TFT after the illumination is removed, additional timing control is also required. In this application, the image sensing pixel circuit uses the PPC effect to perform photoelectric integration to enhance the efficiency of photoelectric conversion. Through the invented novel pipeline structure, only one set of gate drivers is required without increasing the complexity of peripheral driving. Signal, through the principle of time-division multiplexing, can better realize a series of functions of photoelectric signal integration, readout and reset. From the perspective of image sensing array layout implementation, the multiplexing structure of row and row driving signal lines reduces the number of signal lines, which is beneficial to improve the fill factor of the image sensing pixel array.

2) The parallelized pipeline structure can reset the photosensitive cells of the previous row in time while reading out the photoelectric signal in each row. This time-sharing reset operation avoids additional clock cycles for global reset, which is beneficial to shortening the frame time and improving frame rate. Since the image sensor array is reset by sub-line and time-sharing, the global reset of the entire image sensor array at the same time period is avoided, which avoids the high current situation that may be generated by the global reset, which is beneficial to improve the image sensor. Robustness of the array.

FIG. 9 illustrates a simplified timing diagram of the parallelized pipeline structure of the present application. The i stage is the initialization reset stage, ii is the exposure stage, iii is the readout stage, iv is the exposure stage of the next frame, and v is the readout stage of the next frame. That is, T ₁ and T ₂ are one frame period, and the sequence of exposure-readout-exposure-readout-exposure-readout... is repeated.

Figure 10 illustrates a timing case without parallelized pipeline structure. The i stage is the initialization reset stage, ii is the exposure stage, iii is the readout stage, iv is the PPC effect reset stage, v is the exposure stage of the next frame, vi is the readout stage of the next frame, and iv is the next frame PPC effect reset phase. That is, T ₁ and T ₂ are one frame period, and the process is repeated with exposure-readout-PPC effect reset-exposure-readout-PPC effect reset-exposure-readout-PPC effect reset...and so on. According to the comparison of FIG. 9, it can be seen that the timing of the parallelized pipeline structure is one PPC reset stage less than the cycle of the general timing sequence that has not been designed, which is beneficial to the improvement of the frame rate.

Fig. 13 shows the SPICE simulation waveform of the transient output of the photoelectric pixel circuit according to an embodiment. The example is a 12X1 pixel array, where each pulse is the output of the corresponding row of pixel circuits, and the output pulses have different sizes, corresponding to The situation of different photo-generated currents generated by different illuminations of pixels in different rows is presented. In this simulation, by modifying the off-state current parameter iol in the TFTSPICE model, it is simulated that the phototransistor in the photoelectric sensing unit is subjected to different intensities of illumination to generate currents of different magnitudes and the conductance changes accordingly. The iol parameter of the phototransistor in the 12X1 pixel array of this simulation example gradually increases from the first row to the twelfth row. In the simulation of the pixels from the first row to the twelfth row, the light intensity received by the pixels in this row is dark in turn. From the left to the right, the simulated output waveform corresponds to the output response of the column from the first row without light to the twelfth row with the light intensity gradually increasing. According to the above-mentioned principle analysis, after the reset of each frame, the initial charge is maintained on the charge of the memory cell, and the charge on the capacitor returns to the initial charge after readout. During the intermediate process, the amount of charge on the capacitor changes. Among them, the amount of change of the integrated charge generated in the integration stage is positively related to the light intensity; the amount of transferred charge read out in the read-out stage is proportional to the jump amplitude of the output signal. Because the voltage difference between the initial and final state of the capacitor is equal in the process, the sum of the integral charge change positively related to the light intensity and the readout transfer charge is zero. Therefore, the jump amplitude of the output signal is related to the input photocurrent, That is, the magnitude of the light intensity is negatively correlated. From the simulation results, the amplitude of the transition of the output signal voltage decreases sequentially from left to right, and the corresponding situation is that the photocurrent generated by the pixels in this column increases row by row, and the light intensity received increases row by row. The simulation results show that the voltage jump amplitude of the output signal is negatively correlated with the simulated illumination light intensity, which is in line with the expected working principle of the structure. If the voltage amplitude corresponds to the light intensity to be distinguished, and subsequent analysis and processing is performed, the conversion of the light intensity signal to the electrical signal can be realized. Therefore, the simulation results can prove that the pixel structure of this example can work normally and accurately for photoelectric image readout.

The above specific examples are used to illustrate the present invention, which are only used to help understand the present invention, and are not intended to limit the present invention. For those skilled in the art to which the present invention pertains, according to the idea of the present invention, several simple deductions, modifications or substitutions can also be made.

Claims (6)

1. A phototransistor having a photoresponse, comprising:

the device comprises a substrate, a bottom gate electrode, a bottom gate dielectric layer, an active layer, a top gate dielectric layer and a top gate electrode which are stacked layer by layer; the active layer comprises a semiconductor material with a light memory function, and the active layer comprises a channel and a source drain region;

in the illumination stage and the integration stage, the voltages of a bottom gate electrode and a top gate electrode of the phototransistor are different, and the phototransistor is in an off-state working area; the integration stage at least comprises a first preset time period after the exposure is finished;

wherein the semiconductor material with the optical memory function comprises a metal oxide semiconductor.

2. The phototransistor of claim 1, wherein a voltage of a bottom gate electrode and a top gate electrode of the phototransistor causes the phototransistor to be in an on-state region of operation during a reset phase.

3. The phototransistor of claim 1, wherein the phototransistor further comprises a passivation layer located at least on the top gate electrode, and a scintillator located over the passivation layer and the source and drain regions.

4. A method of sensing light using a dual-gate phototransistor, wherein an active layer material of the dual-gate phototransistor includes a material having a memory function, the method comprising:

exposing the double-gate phototransistor in an illumination stage, canceling the illumination in a subsequent integration stage, respectively applying different electric potentials to a bottom gate electrode and a top gate electrode of the double-gate phototransistor in the whole illumination stage and the whole integration stage, and enabling the double-gate phototransistor to be in an off-state working area, wherein the integration stage at least comprises a first preset time period after the exposure is finished, and the semiconductor material with the optical memory function comprises a metal oxide semiconductor.

5. The method of claim 4, further comprising:

and in a reset stage, applying voltage to a bottom gate electrode and a top gate electrode of the double-gate phototransistor to enable the double-gate phototransistor to be in an on-state working area.

6. An image sensor array comprising a readout circuit, a gate drive circuit and a bias circuit, and coupled thereto an array of pixels comprising a phototransistor as set forth in any one of claims 1-3.

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