CN114613672A - Method for manufacturing semiconductor device - Google Patents

Abstract

The invention provides a manufacturing method of a semiconductor device, which comprises the following steps: forming patterned polycrystalline silicon on a semiconductor substrate, and forming a spacer layer on the side wall of the polycrystalline silicon; covering a protective layer on the surface of the semiconductor substrate, wherein the protective layer exposes the top parts of the polycrystalline silicon and the spacing layer and buries the spacing layer with a preset height; and etching to remove the exposed spacer layer, wherein the rest spacer layer is the spacer layer required on the side wall of the polycrystalline silicon. After the spacer layer is normally etched and formed, a protective layer with a certain thickness is formed on the semiconductor substrate, then the height of the spacer layer is reduced through etching, and as the root of the spacer layer is covered and protected by the protective layer, the side effect of spacer layer thickness reduction caused by conventional isotropic etching is avoided in the isotropic etching process.

Description

A method of manufacturing a semiconductor device

technical field

The present invention relates to the technical field of semiconductor devices, in particular to a method for manufacturing a semiconductor device.

Background technique

The polysilicon spacer (POLY Spacer, also known as polysilicon sidewall) is used to protect the polysilicon (POLY) sidewall and define the area for subsequent ion implantation (IMP). Among them, spacer height and spacer width are two very important parameters. As shown in Figure 1, the height of the spacer layer is used to characterize the protection area of the spacer layer on the polysilicon sidewall. If the spacer layer is too high or too low, it will have a direct impact on the protection area of the polysilicon itself, and will also affect the subsequent nickel silicide (Nickle silicide). Silicide, referred to as NiSi) and other metal silicides generated. The spacer thickness is more used to define the area for subsequent ion implantation.

In spacer etch, if the spacer layer is too high, the height of the spacer layer can generally be reduced by increasing the etching time or adjusting the etching rate. Specifically, please refer to Figures 2a and 2b , Figure 2a is a schematic diagram before the spacer layer is etched, and Figure 2b is a schematic diagram after the spacer layer is etched. Comparing Figures 2a and 2b, it can be seen that after the spacer layer is etched, although the height of the spacer layer can be reduced to the required height , but at the same time, the thickness of the spacer layer will be affected and become smaller (that is, the spacer layer will become shorter and thinner), this is because the spacer layer etching is mainly chemical-based etching (that is, the isotropic etching that is often referred to). Etching, isotropic etch), the longitudinal and lateral etch rates of the spacer layer are basically the same, thereby causing the spacer layer to become shorter in the longitudinal direction and also thin in the lateral direction. However, if the thickness of the spacer layer is too small, the width of the area where the subsequent ion implantation is easy is insufficient. The etching not only reduces the height of the spacer layer, but also reduces the thickness of the spacer layer due to the influence of the etching process, which leads to the subsequent wafer acceptance test. (WAT: wafer acceptance test) failed.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a method for manufacturing a semiconductor device, so as to solve the problem that isotropic etching reduces the height and thickness of the spacer layer at the same time.

In order to solve the above-mentioned technical problems, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps:

forming patterned polysilicon on a semiconductor substrate, and forming spacers on sidewalls of the polysilicon;

A protective layer is covered on the surface of the semiconductor substrate, and the protective layer exposes the polysilicon and the top of the spacer layer and buries the spacer layer with a predetermined height;

The exposed spacer layer is removed by etching, and the remaining spacer layer is the spacer layer required on the polysilicon sidewall.

Preferably, the step of covering the surface of the semiconductor substrate with a protective layer includes:

A protective layer is covered on the surface of the semiconductor substrate, polysilicon and the spacer layer, and the thickness of the protective layer on the semiconductor substrate at the periphery of the spacer layer is at least higher than the height of the polysilicon, so that the polysilicon and the spacer layer is buried therein;

The protective layer is etched back to expose the polysilicon and the top of the spacer layer, and to bury the spacer layer to a predetermined height.

Preferably, the material of the protective layer includes an anti-reflection material and/or photoresist for photolithography, and is covered on the surface of the semiconductor substrate, polysilicon and the spacer layer by a deposition or coating process.

Preferably, the etching gas used to etch back the protective layer includes carbon monoxide.

Preferably, the exposed spacer layer is removed by using an isotropic etching process.

Preferably, after etching back the protective layer, the method further includes: removing the protective layer.

Preferably, after removing the protective layer, the method further includes: rounding the spacer layer to make the top of the spacer layer smooth.

Preferably, the etching gas used for rounding the spacer layer includes hydrogen-containing fluorocarbon.

Preferably, after removing the protective layer, the method further includes: using the spacer layer and the polysilicon as a mask, performing ion implantation on the semiconductor substrate.

Preferably, the polysilicon is the gate of the MOS device, and the spacer layer and the polysilicon are used as masks, and after ion implantation is performed on the semiconductor substrate on both sides of the polysilicon, the semiconductor substrate on both sides of the polysilicon is ion-implanted. The source region and the drain region of the MOS device are respectively formed in the semiconductor substrate.

In the manufacturing method of the semiconductor device provided by the present invention, after the spacer layer is normally etched and formed, a protective layer of a certain thickness is formed on the semiconductor substrate to protect the required spacer layer (which can be called the root of the spacer layer). , and then remove the spacer layer above the protective layer by etching to achieve the purpose of reducing the height of the spacer layer. Since the root of the spacer layer is covered and protected by the protective layer, on the basis of reducing the height of the spacer layer, conventional isotropic etching is avoided. The side effect of reducing the thickness of the spacer layer caused by the etching further avoids the failure of the wafer acceptance test (WAT: wafer acceptance test), which eventually leads to low yield or even scrap of the product.

Further, here, the protective layer is made of photolithographic materials such as anti-reflection materials, and the redundant part of the protective layer can be removed by coating and photolithography, so that the remaining protective layer can achieve the purpose of protecting the spacer layer of the required thickness. Simple and low cost to manufacture. Moreover, when the protective layer is made of anti-reflection material, it can not only be used as the protective layer of the spacer layer, but also can reduce reflection during the etching process, reduce the influence of the standing wave effect, and help to control the lowering height of the spacer layer more accurately.

Description of drawings

Fig. 1 is the electron microscope picture under the existing embodiment;

2a is a schematic cross-sectional view of the polysilicon and the spacer layer before etching in the prior art;

2b is a schematic cross-sectional view of the polysilicon and the spacer layer after etching in the prior art;

Fig. 3 is the flow chart of the implementation of the present invention;

4 is a schematic cross-sectional view of the present invention after polysilicon and spacer layers are formed;

5 is a schematic cross-sectional view of an example of the covering protective layer of the present invention after covering the protective layer;

FIG. 6 is a cross-sectional schematic diagram of an example of the covering protective layer of the present invention after the protective layer covered in FIG. 5 is etched back;

7 is a schematic cross-sectional view of the present invention after the top of the spacer layer is etched;

8 is a schematic cross-sectional view of another example of the present invention after removing the protective layer;

9 is a schematic cross-sectional view of another example of the present invention after the shape of the spacer layer is rounded.

In the figure,

1. Semiconductor substrate; 2. Polysilicon; 3. Spacer layer; 4. Protective layer.

Detailed ways

The manufacturing method of the semiconductor device proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become apparent from the following description and claims. It should be noted that, the accompanying drawings are all in a very simplified form and in inaccurate scales, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.

The inventor's research found that while the height of the spacer layer 3 is reduced by adjusting the etching parameters, the thickness of the spacer layer 3 will also become thinner due to isotropic etching, which cannot meet the performance requirements of the device.

Based on this, please refer to FIGS. 3-7 , the core idea of the present invention is to form a protective layer 4 on the semiconductor substrate 1 after the spacer layer 3 is normally etched and formed (ie, a conventional sidewall etching process). , protect the required root of the spacer layer 3 (the end of the spacer layer 3 close to the semiconductor substrate 1) and expose the top of the spacer layer 3, and then remove the top of the spacer layer 3 exposed by the protective layer 4 by etching to achieve For the purpose of reducing the height of the spacer layer 3 , and since the root of the spacer layer 3 is protected, the thickness of the root portion remains unchanged, thereby ensuring the ion implantation region defined by the thickness of the spacer layer 3 .

Specifically, please refer to FIGS. 3-7 , which are schematic diagrams of an embodiment of the present invention. As shown in FIG. 3, an embodiment of the present invention provides a method for manufacturing a semiconductor device, including the following steps:

S1, a patterned polysilicon 2 is formed on the semiconductor substrate 1, and a spacer layer 3 is formed on the sidewall of the polysilicon 2. As shown in FIG. 4, the semiconductor substrate 1 is a silicon substrate, and the spacer layer 3 is silicon nitride .

S2, cover the protective layer 4 on the surface of the semiconductor substrate 1, and the protective layer 4 exposes the top of the polysilicon 2 and the spacer layer 3 and bury the spacer layer 3 with a predetermined height, as shown in FIG. 6, the protective layer 4 covers The root of the spacer layer 3 is protected to prevent the spacer layer 3 from being thinned in the lateral direction due to isotropic etching.

In an example, the step of covering the protective layer 4 on the surface of the semiconductor substrate 1 includes:

First, a protective layer 4 is covered on the surfaces of the semiconductor substrate 1 , the polysilicon 2 and the spacer layer 3 , as shown in FIG. 5 , and in order to smooth the height difference caused by the topography of the surface of the semiconductor substrate 1 , the protective layer The predetermined thickness of the coating on the semiconductor substrate 1 around the spacer layer 3 is at least higher than the height of the polysilicon 2. At this time, the protective layer 4 can completely cover the polysilicon 2 and the spacer layer 3, and has a relatively flat top surface.

Then, the protective layer 4 is etched back to expose the top of the polysilicon 2 and the spacer layer 3, and the spacer layer 3 with a predetermined height is buried, as shown in FIG. The etching gas depends on the material of the protective layer 4 . In the process of etching back the protective layer 4 , the etching gas has a high etching selectivity ratio to the protective layer 4 , and has little effect on the polysilicon 2 and the spacer layer 3 .

The material of the protective layer 4 includes an anti-reflection material and/or photoresist for photolithography, and is covered on the surfaces of the semiconductor substrate 1 , the polysilicon 2 and the spacer layer 3 by a deposition or coating process.

In an example of the protective layer 4, the protective layer 4 is selected from the BARC (Bottom Anti-Reflective Coatings) commonly used between the photoresist (PR) and the semiconductor substrate 1 under the current technology, and the BARC is A layer of organic or inorganic anti-reflection material is deposited before the photoresist covering, in order to achieve the purpose of increasing the photolithography process window and improving the control of the photolithography strip width. BARC has good photosensitive properties. It can not only realize the etching back after covering the protective layer 4 in the S2 step to achieve the purpose of burying the spacer layer 3 with a predetermined height, but also perform etching on the top of the spacer layer 3. In step S3), the light wave reflected by the semiconductor substrate 1 can also be reduced, and the influence of the standing wave effect on the photoresist can be reduced, which is more conducive to determining the etching stop point in step S3, so as to accurately control the height of the remaining spacer layer 3.

As an example, when the protective layer 4 only has a BARC single-layer film, the etching gas used to etch back the protective layer 4 in this step may include carbon monoxide, and only the BARC is etched during the etching, which will not affect the Other parts, such as polysilicon 2 and spacer layer 3 and other film layers.

S3, the spacer layer 3 exposed by the protective layer 4 is removed by etching, and the remaining spacer layer 3 is the spacer layer 3 required on the sidewall of the polysilicon 2, as shown in FIG. 7, wherein an isotropic etching process is used The exposed spacer layer 3 is removed by etching (ie, the top of the spacer layer 3 is removed by etching), the longitudinal height of the spacer layer 3 is reduced, and the root of the spacer layer 3 is covered and protected by the protective layer 4, so the top of the spacer layer 3 is etched During the etching, the root height and thickness of the spacer layer 3 are not affected by the etching.

Specifically, please refer to FIGS. 7-9. In another example of this method, after performing the above steps S1, S2, and S3 in sequence, the following steps are also performed in sequence:

S4, remove the protective layer 4, as shown in FIG. 8, the protective layer 4 proposed in S2 is BARC, when the protective layer 4 is removed, the removal process of the protective layer 4 also needs to be reduced to the polysilicon 2, the spacer layer 3 and the semiconductor substrate 1. effect, so the main gas for etching includes carbon monoxide (CO).

It should be noted that when removing the protective layer 4 (when the material is BARC proposed by S2), the low pressure process of the main etching machine can be used to reduce the formation of the underlying oxide layer, and carbon monoxide is selected as the main etching for removal. Gas, the main etching machine adopts 0 bias power (zero bias power, or guide power output), and controls the percentage of over ash at 30% (normal 100%) to minimize the impact on polysilicon 2. Influence of the spacer layer 3 and the underlying semiconductor substrate 1 .

S5, after removing the protective layer 4, rounding the remaining spacer layer 3 to make the top of the remaining spacer layer 3 smooth, wherein the etching gas used for rounding the remaining spacer layer 3 includes hydrogen-containing gas fluorocarbons, as shown in Figure 9.

In an example, the main etching machine adopts 0 bias power (zero bias power, or guide power output) to reduce the impact on the underlying semiconductor substrate 1, and selects the spacer layer 3 (such as the spacer layer mentioned in S1). The material of 3 is Si ₃ N ₄ , silicon nitride) etching gas with high selectivity ratio, such as CHF ₃ and a class of hydrogen-containing fluorocarbons, in a short time (3-5 seconds), quickly round the spacer layer 3 shape.

S6 , using the remaining spacer layer 3 and the polysilicon 2 as a mask, ion implantation is performed on the semiconductor substrate 1 .

As an example, the polysilicon 2 can be the gate of the MOS device. In step S6, the spacer layer 3 and the polysilicon 2 are used as masks to perform ion implantation on the semiconductor substrate 1 on both sides of the polysilicon. The source region (not shown) and the drain region (not shown) of the MOS device are respectively formed in the semiconductor substrate 1 on both sides of 2 .

To sum up, in the manufacturing method of the semiconductor device provided by the embodiment of the present invention, by using the protective layer to protect the root of the spacer layer, on the basis of reducing the height of the spacer layer, the conventional isotropic etching is avoided. Side effects of spacer thickness reduction.

The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosure all belong to the protection scope of the claims.

Claims (10)

1. a manufacturing method of a semiconductor device, is characterized in that, comprises the following steps: provide semiconductor substrates; forming a patterned photoresist layer on the semiconductor substrate; The photoresist layer is first etched with an etching gas containing a halogen element, and in the first etching, the halogen element is adhered to the upper surface of the photoresist layer, and is combined with the photoresist layer. The surface layer on the upper surface of the photoresist layer reacts to form a resist complex layer. 2 . The method for manufacturing a semiconductor device according to claim 1 , wherein the material of the photoresist layer comprises a 248 nm photoresist material and/or a 193 nm photoresist material. 3 . 3 . The method for manufacturing a semiconductor device according to claim 2 , wherein the material of the photoresist layer comprises polymethacrylate derivatives, polyparahydroxystyrene and polyparahydroxystyrene derivatives. 4 . at least one. 4 . The method for manufacturing a semiconductor device according to claim 1 , wherein the step of forming a patterned photoresist layer on the semiconductor substrate comprises: exposing and developing the photoresist layer to form a pattern. 5 . photoresist layer. 5 . The method for manufacturing a semiconductor device according to claim 4 , wherein after exposing and developing the photoresist layer, the photoresist layer is subjected to an etching gas containing a halogen element after the photoresist layer is exposed and developed. 6 . Before the first etching, a second etching is performed on the photoresist layer, and the shrinkage of the critical dimension of the photoresist layer in the second etching is smaller than that in the first etching quantity. 6. The method for manufacturing a semiconductor device according to claim 5, wherein the etching gas used in the second etching is the same as the etching gas used in the first etching, and the second etching gas is the same as the etching gas used in the first etching. The etching time of etching and the first etching are different; Or, the etching gas used in the second etching is less than the halogen element in the etching gas used in the first etching; Alternatively, the process temperature of the second etching is higher than the process temperature of the first etching. 7. The method for manufacturing a semiconductor device according to claim 5, further comprising: after exposing and developing the photoresist layer and before performing the second etching on the photoresist layer, or After the second etching is performed on the photoresist layer and before the first etching is performed on the photoresist layer, using the photoresist layer as a mask, first ion implantation is performed on the semiconductor substrate; as well as, After the photoresist layer is first etched with an etching gas containing halogen elements, the photoresist layer is used as a mask to perform second ion implantation on the semiconductor substrate. 8. The method for manufacturing a semiconductor device according to any one of claims 1 to 7, wherein the etching gas comprises a main etching gas and an auxiliary etching gas for generating the halogen element, The auxiliary etching gas includes at least one of hydrogen bromide, carbon tetrafluoride and chlorine. 9 . The method for manufacturing a semiconductor device according to claim 8 , wherein the auxiliary etching gas comprises hydrogen bromide, and the flow rate of the hydrogen bromide is at least 50 sccm; and the main etching gas comprises oxygen. 10 . 10. The method for manufacturing a semiconductor device according to any one of claims 1 to 7, wherein the resist complex layer enables the etching gas to have a longitudinal etching rate of the photoresist layer and the lateral etch rate is less than 5:1.

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