CN114613311B - 9T2C circuit for improving stability of display screen and driving method thereof - Google Patents
9T2C circuit for improving stability of display screen and driving method thereof Download PDFInfo
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- CN114613311B CN114613311B CN202210324384.7A CN202210324384A CN114613311B CN 114613311 B CN114613311 B CN 114613311B CN 202210324384 A CN202210324384 A CN 202210324384A CN 114613311 B CN114613311 B CN 114613311B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The invention discloses a 9T2C circuit for improving the stability of a display screen and a driving method thereof, wherein a grid electrode of a transistor T1 is connected with a first GIP output signal Gn-4, a grid electrode of a transistor T7 is connected with a second GIP output signal Gn+4, a drain electrode of the transistor T1 and a drain electrode of the transistor T7 are respectively and electrically connected with a grid electrode of a transistor T2, a drain electrode of a transistor T3, a grid electrode of a transistor T4, a grid electrode of a transistor T8, a grid electrode of a transistor T9 and one end of a capacitor C2, and the drain electrode of the transistor T2 is respectively and electrically connected with a grid electrode of a transistor T3, a grid electrode of a transistor T6 and one end of the capacitor C1; the other end of the capacitor C1 is grounded; the source of the transistor T3 is connected to the source of the transistor T8 and the drain of the transistor T9, respectively, and the source of the transistor T4, the drain of the transistor T5, the drain of the transistor T6 and the other end of the capacitor C2 are connected to the third GIP output signal Gn. The invention effectively reduces the leakage current of the transistor T3, thereby improving the stability of the display screen.
Description
Technical Field
The invention relates to the technical field of panel display, in particular to a 9T2C circuit for improving the stability of a display screen and a driving method thereof.
Background
In a display screen driving circuit, the problem of leakage of the TFT device often occurs due to the influence of various factors, and once the potential of a key node point loses a required level, the display screen is abnormal.
Disclosure of Invention
The invention aims to provide a 9T2C circuit for improving the stability of a display screen and a driving method thereof, which can prevent a key node from influencing the subsequent level transmission due to the fact that the electric leakage of a TFT (thin film transistor) cannot reach a standard level, achieve the purpose of improving the poor picture of the display screen due to the electric leakage, and effectively improve the stability of the display screen.
The technical scheme adopted by the invention is as follows:
A9T 2C circuit for improving the stability of a display screen comprises a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a capacitor C1 and a capacitor C2, wherein a grid electrode of the transistor T1 is connected with a first GIP output signal Gn-4, a grid electrode of the transistor T7 is connected with a second GIP output signal Gn+4,
the drain of the transistor T1 and the drain of the transistor T7 are respectively and electrically connected with the gate of the transistor T2, the drain of the transistor T3, the gate of the transistor T4, the gate of the transistor T8, the gate of the transistor T9 and one end of the capacitor C2,
the drain electrode of the transistor T2 is electrically connected with the grid electrode of the transistor T3, the grid electrode of the transistor T6 and one end of the capacitor C1 respectively; the other end of the capacitor C1 is grounded;
the source of transistor T3 is connected to the source of transistor T8 and the drain of transistor T9 respectively,
the source of the transistor T4, the drain of the transistor T5, the drain of the transistor T6 and the other end of the capacitor C2 are all connected to the third GIP output signal Gn.
Further, the drain of the transistor T4 is connected to the first clock signal CK1, and the gate of the transistor T5 is connected to the second clock signal CK5.
Further, the source of the transistor T1 and the drain of the transistor T8 are both connected to the positive electrode VGH of the power supply.
Further, the source of the transistor T2, the source of the transistor T5, the source of the transistor T6, the source of the transistor T7 and the source of the transistor T9 are all connected to the negative voltage VGL of the power supply.
Further, the transistors T1, T2, T3, T4, T5, T6, T7 and T8 are all N-channel MOS transistors, and the transistor T9 is a P-channel MOS transistor.
The driving method of the 9T2C circuit for improving the stability of the display screen comprises a first time period, a second time period, a third time period, a fourth time period, a fifth time period, a sixth time period and a seventh time period; wherein,,
in a first period t1: the first clock signal CK1 is in a high level, the capacitor C1 is charged, the potential of the first node P becomes a high potential, the transistors T3 and T6 are turned on, the potential of the third GIP output signal Gn is pulled to a low potential, the second node Q is pulled to a low potential under the coupling action of the capacitor C2, and the transistor T9 is turned on;
during a second time period t2: the first clock signal CK1 becomes low level, the first node P point potential becomes low level, and the transistors T3 and T6 are turned off;
in a third time period t3: the first GIP output signal Gn-4 is high, the second clock signal CK5 is high, the transistors T1 and T5 are turned on, the second node Q point becomes high, and the transistors T2, T4 and T8 are turned on; the third node R point becomes a high potential;
in a fourth time period t4: the first GIP output signal Gn-4 and the second clock signal CK5 become low level, the transistors T1 and T5 are turned off, and the second node Q point is kept high;
in a fifth period t5: the first clock signal CK1 becomes high level, the third GIP output signal Gn outputs high potential, the second node Q point is pulled to higher potential under the coupling action of the capacitor C2, the transistor T8 is kept in an on state, the third node R point is high potential, even if the transistor T3 is greatly floated due to the Vth, the potential of the transistor T3 leaked into the Q point is still high potential, and the transistor T4 works normally;
in a sixth time period t6: the first clock signal CK1 becomes low level, the third GIP output signal Gn becomes low level, and the second node Q point falls to high level in the presence of the capacitor C2;
in a seventh period t7: the second GIP output signal gn+4 and the second clock signal CK5 are high, the transistor T7 is turned on to pull the potential of the second node Q to low, the transistor T8 is turned off, the transistor T9 is turned on, and the third node R becomes low.
According to the technical scheme, the leakage current of the TFT device depends on the relation between the voltage difference between the gate voltage and the source voltage and the Vth, and in the driving process T5, even if the Vth of the T3 device is in a negative drift condition, the R point is pulled to a high potential at the moment, which is equivalent to pulling the source (R point) voltage of the T3 high, so that the leakage current of the T3 is effectively reduced, and the stability of the display screen is improved. In the GIP driving process, the invention prevents the key node from influencing the subsequent level transmission due to the fact that the TFT electric leakage does not reach the level, achieves the purpose of improving the poor picture caused by the electric leakage of the display screen, and effectively improves the stability of the display screen.
Drawings
The invention is described in further detail below with reference to the drawings and detailed description;
FIG. 1 is a schematic diagram of a 9T2C circuit for improving display screen stability;
fig. 2 is a timing diagram corresponding to a 9T2C circuit for improving stability of a display screen according to the present invention.
Detailed Description
For the purposes, technical solutions and advantages of the embodiments of the present application, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
As shown in fig. 1, the invention discloses a 9T2C circuit for improving the stability of a display screen, which comprises a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a capacitor C1 and a capacitor C2, wherein the gate of the transistor T1 is connected with a first GIP output signal Gn-4, the gate of the transistor T7 is connected with a second GIP output signal gn+4,
the drain of the transistor T1 and the drain of the transistor T7 are respectively and electrically connected with the gate of the transistor T2, the drain of the transistor T3, the gate of the transistor T4, the gate of the transistor T8, the gate of the transistor T9 and one end of the capacitor C2,
the drain electrode of the transistor T2 is electrically connected with the grid electrode of the transistor T3, the grid electrode of the transistor T6 and one end of the capacitor C1 respectively; the other end of the capacitor C1 is grounded;
the source of transistor T3 is connected to the source of transistor T8 and the drain of transistor T9 respectively,
the source of the transistor T4, the drain of the transistor T5, the drain of the transistor T6 and the other end of the capacitor C2 are all connected with a third GIP output signal Gn;
further, the drain of the transistor T4 is connected to the first clock signal CK1, and the gate of the transistor T5 is connected to the second clock signal CK5.
Further, the source of the transistor T1 and the drain of the transistor T8 are both connected to the positive electrode VGH of the power supply.
Further, the source of the transistor T2, the source of the transistor T5, the source of the transistor T6, the source of the transistor T7 and the source of the transistor T9 are all connected to the negative voltage VGL of the power supply.
Specifically, VGH is a dc high voltage and VGL is a dc low voltage.
Further, the transistors T1, T2, T3, T4, T5, T6, T7 and T8 are all N-channel MOS transistors, and the transistor T9 is a P-channel MOS transistor.
As shown in fig. 2, a driving method of a 9T2C circuit for improving stability of a display screen includes a scan period including a first period, a second period, a third period, a fourth period, a fifth period, a sixth period, and a seventh period; wherein,,
in a first period t1: the first clock signal CK1 is in a high level, the capacitor C1 is charged, the potential of the first node P becomes a high potential, the transistors T3 and T6 are turned on, the potential of the third GIP output signal Gn is pulled to a low potential, the second node Q is pulled to a low potential under the coupling action of the capacitor C2, and the transistor T9 is turned on;
during a second time period t2: the first clock signal CK1 becomes low level, the first node P point potential becomes low level, and the transistors T3 and T6 are turned off;
in a third time period t3: the first GIP output signal Gn-4 is high, the second clock signal CK5 is high, the transistors T1 and T5 are turned on, the second node Q point becomes high, and the transistors T2, T4 and T8 are turned on; the third node R point becomes a high potential;
in a fourth time period t4: the first GIP output signal Gn-4 and the second clock signal CK5 become low level, the transistors T1 and T5 are turned off, and the second node Q point is kept high;
in a fifth period t5: the first clock signal CK1 becomes high level, the third GIP output signal Gn outputs high potential, the second node Q point is pulled to higher potential under the coupling action of the capacitor C2, the transistor T8 is kept in an on state, the third node R point is high potential, even if the transistor T3 is greatly floated due to the Vth, the potential of the transistor T3 leaked into the Q point is still high potential, and the transistor T4 works normally;
in a sixth time period t6: the first clock signal CK1 becomes low level, the third GIP output signal Gn becomes low level, and the second node Q point falls to high level in the presence of the capacitor C2;
in a seventh period t7: the second GIP output signal gn+4 and the second clock signal CK5 are high, the transistor T7 is turned on to pull the potential of the second node Q to low, the transistor T8 is turned off, the transistor T9 is turned on, and the third node R becomes low.
According to the technical scheme, the leakage current of the TFT device depends on the relation between the voltage difference between the gate voltage and the source voltage and the Vth, and even if the Vth of the transistor T3 device is in a negative floating condition in the fifth time period T5 of the driving process, the third node R point is pulled to a high potential at the moment, which is equivalent to pulling the source (R point) voltage of the transistor T3 high, so that the leakage current of the transistor T3 is effectively reduced, and the stability of the display screen is improved. In the GIP driving process, the invention prevents the key node from influencing the subsequent level transmission due to the fact that the TFT electric leakage does not reach the level, achieves the purpose of improving the poor picture caused by the electric leakage of the display screen, and effectively improves the stability of the display screen.
It will be apparent that the embodiments described are some, but not all, of the embodiments of the present application. Embodiments and features of embodiments in this application may be combined with each other without conflict. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the detailed description of the embodiments of the present application is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
Claims (2)
1. 9T2C circuit for improving stability of display screen, which is characterized in that: which comprises a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9, a capacitor C1 and a capacitor C2, wherein the grid electrode of the transistor T1 is connected with a first GIP output signal Gn-4, the grid electrode of the transistor T7 is connected with a second GIP output signal Gn+4,
the drain of the transistor T1 and the drain of the transistor T7 are respectively and electrically connected with the gate of the transistor T2, the drain of the transistor T3, the gate of the transistor T4, the gate of the transistor T8, the gate of the transistor T9 and one end of the capacitor C2,
the drain electrode of the transistor T2 is electrically connected with the grid electrode of the transistor T3, the grid electrode of the transistor T6 and one end of the capacitor C1 respectively; the other end of the capacitor C1 is grounded;
the source of transistor T3 is connected to the source of transistor T8 and the drain of transistor T9 respectively,
the source of the transistor T4, the drain of the transistor T5, the drain of the transistor T6 and the other end of the capacitor C2 are all connected with a third GIP output signal Gn; the drain electrode of the transistor T4 is connected with the first clock signal CK1, and the gate electrode of the transistor T5 is connected with the second clock signal CK5; the source electrode of the transistor T1 and the drain electrode of the transistor T8 are both connected with the positive pole VGH of the power supply; the source electrode of the transistor T2, the source electrode of the transistor T5, the source electrode of the transistor T6, the source electrode of the transistor T7 and the source electrode of the transistor T9 are all connected with the negative pole VGL of the power supply; the transistors T1, T2, T3, T4, T5, T6, T7 and T8 are all N-channel MOS transistors, and the transistor T9 is a P-channel MOS transistor.
2. A driving method of a 9T2C circuit for improving stability of a display screen, applied to the 9T2C circuit for improving stability of a display screen according to claim 1, characterized in that: the scanning period includes a first period, a second period, a third period, a fourth period, a fifth period, a sixth period, and a seventh period; wherein,,
in a first period t1: the first clock signal CK1 is in a high level, the capacitor C1 is charged, the potential of the first node P becomes a high potential, the transistors T3 and T6 are turned on, the potential of the third GIP output signal Gn is pulled to a low potential, the second node Q is pulled to a low potential under the coupling action of the capacitor C2, and the transistor T9 is turned on;
during a second time period t2: the first clock signal CK1 becomes low level, the first node P point potential becomes low level, and the transistors T3 and T6 are turned off;
in a third time period t3: the first GIP output signal Gn-4 is high, the second clock signal CK5 is high, the transistors T1 and T5 are turned on, the second node Q point becomes high, and the transistors T2, T4 and T8 are turned on; the third node R point becomes a high potential;
in a fourth time period t4: the first GIP output signal Gn-4 and the second clock signal CK5 become low level, the transistors T1 and T5 are turned off, and the second node Q point is kept high;
in a fifth period t5: the first clock signal CK1 becomes high level, the third GIP output signal Gn outputs high potential, the second node Q point is pulled to higher potential under the coupling action of the capacitor C2, the transistor T8 is kept in an on state, the third node R point is high potential, even if the transistor T3 is greatly floated due to the Vth, the potential of the transistor T3 leaked into the Q point is still high potential, and the transistor T4 works normally;
in a sixth time period t6: the first clock signal CK1 becomes low level, the third GIP output signal Gn becomes low level, and the second node Q point falls to high level in the presence of the capacitor C2;
in a seventh period t7: the second GIP output signal gn+4 and the second clock signal CK5 are high, the transistor T7 is turned on to pull the potential of the second node Q to low, the transistor T8 is turned off, the transistor T9 is turned on, and the third node R becomes low.
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| CN105336300B (en) * | 2015-12-04 | 2019-03-26 | 昆山龙腾光电有限公司 | Shift register, gate driving circuit and display device |
| CN105788553B (en) * | 2016-05-18 | 2017-11-17 | 武汉华星光电技术有限公司 | GOA circuits based on LTPS semiconductor thin-film transistors |
| CN107068088B (en) * | 2017-04-14 | 2019-04-05 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit, display device |
| CN108399902A (en) * | 2018-03-27 | 2018-08-14 | 京东方科技集团股份有限公司 | Shift register, gate driving circuit and display device |
| CN108520724B (en) * | 2018-04-18 | 2020-02-28 | 京东方科技集团股份有限公司 | Shift register unit and driving method, gate driving circuit and display device |
| CN209045139U (en) * | 2018-09-26 | 2019-06-28 | 福建华佳彩有限公司 | A kind of pixel-driving circuit and liquid crystal display device |
| CN112885282B (en) * | 2021-02-25 | 2024-04-05 | 福建华佳彩有限公司 | GIP circuit suitable for high-resolution display screen and control method thereof |
| CN215220223U (en) * | 2021-02-25 | 2021-12-17 | 福建华佳彩有限公司 | GIP circuit |
| CN215265527U (en) * | 2021-02-25 | 2021-12-21 | 福建华佳彩有限公司 | GIP drive circuit |
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