CN114598882A - Symmetric Intra Block Copy Mode - Google Patents

Abstract

A symmetric intra block copy mode is described. Systems, methods, and apparatus for encoding, decoding, or transcoding digital video are described. An example method of video processing includes: a conversion is performed between a video block of video comprising two or more color component blocks and a bitstream representation of the video. Two or more color component blocks are coded using a plurality of prediction methods according to a coding rule, at least one of the plurality of prediction methods being a Symmetric Intra Block Copy (SIBC) method.

Description

Symmetric Intra Block Copy Mode

technical field

This patent document relates to digital video codec techniques, including video encoding, transcoding, or decoding.

Background technique

Digital video accounts for the largest use of bandwidth on the Internet and other digital communication networks. Bandwidth requirements for digital video usage are expected to continue to grow as the number of connected user devices capable of receiving and displaying video increases.

SUMMARY OF THE INVENTION

This document discloses techniques that can be used by video encoders and decoders in order to process codec representations of video or images according to file formats.

In one example aspect, a video processing method is disclosed. The method includes performing a conversion between a video block of the video comprising two or more color component blocks and a bitstream representation of the video; wherein the two or more are encoded and decoded using a plurality of prediction methods according to encoding and decoding rules For color component blocks, at least one of the multiple prediction methods is a Symmetric Intra Block Copy (SIBC) method.

In another example aspect, another video processing method is disclosed. The method includes determining whether to use a Symmetric Intra Block Copy (SIBC) method to encode and decode the video block according to a codec rule for conversion between a video block of the video comprising one or more color component blocks and a codec representation of the video ; and performing a conversion based on the determination.

In another example aspect, another video processing method is disclosed. The method includes performing a conversion between a video block of the video comprising one or more color component blocks and a bitstream representation of the video, wherein the bitstream representation conforms to a format rule, wherein the format rule specifies whether and not to be indicated in the bitstream representation and How to use the Symmetric Intra Block Copy (SIBC) method to codec the color component blocks of a video block.

In yet another example aspect, a video encoder apparatus is disclosed. The video encoder includes a processor configured to implement the above-described method.

In yet another example aspect, a video decoder apparatus is disclosed. The video decoder includes a processor configured to implement the above-described method.

In yet another example aspect, a computer-readable medium having code stored thereon is disclosed. The code embodies one of the methods described herein in the form of processor executable code.

In yet another example aspect, a computer-readable medium having a bitstream stored thereon is disclosed. This bitstream is generated or processed using the methods described in this document.

These and other features are described throughout this document.

Description of drawings

1 is a block diagram of an example video processing system.

FIG. 2 is a block diagram of a video processing apparatus.

3 is a flowchart of an example method of video processing.

4 is a block diagram illustrating a video codec system according to some embodiments of the present disclosure.

5 is a block diagram illustrating an encoder according to some embodiments of the present disclosure.

6 is a block diagram illustrating a decoder according to some embodiments of the present disclosure.

7 is a block diagram of a video encoder.

Detailed ways

Section headings are used in this document for ease of understanding and do not limit the applicability of the techniques and embodiments disclosed in each section to that section only. Furthermore, H.266 terminology is used in some of the descriptions only for ease of understanding, and not for the purpose of limiting the scope of the disclosed technology. As such, the techniques described herein are also applicable to other video codec protocols and designs. In this document, editorial changes to text are shown relative to the current draft of the VVC specification by strikethrough indicating deletion of text and highlighting (including bold italics) indicating added text.

1. Preliminary discussion

This document deals with video codec technology. Specifically, this document relates to transform skip modes and transform types (ie including identity transforms) in video codecs. It can be applied to existing video codec standards such as HEVC, or to a standard to be finalized (Universal Video Codec). It can also be applied to future video codec standards or video codecs.

2. Basics of video codec

Video codec standards have largely evolved through the development of well-known ITU-T and ISO/IEC standards. ITU-T developed H.261 and H.263, ISO/IEC developed MPEG-1 and MPEG-4 Visual, and the two organizations jointly developed H.262/MPEG-2 Video, H.264/MPEG-4 Advanced Video Coding (AVC) and H.265/HEVC standards. Since H.262, video codec standards have been based on a hybrid video codec structure, in which temporal prediction plus transform codec is employed. In order to explore future video codec technologies other than HEVC, VCEG and MPEG jointly established the Joint Video Exploration Team (JVET) in 2015. Since then, JVET has taken many new methods and applied them to a reference software called the Joint Exploration Model (JEM). In April 2018, the Joint Video Expert Team (JVET) was created between VCEG (Q6/16) and ISO/IEC JTC1 SC29/WG11 (MPEG), which is dedicated to studying the VVC standard with the goal of 50% bitrate drop compared to HEVC.

The latest version of the VVC draft, Generic Video Codec (Draft 10), can be found at:

http://phenix.it-sudparis.eu/jvet/doc_end_user/current_document.php?f id=10399

VVC's latest reference software called VTM can be found at:

https://vcgit.hhi.fraunhofer.de/jvet/VVCSoftware_VTM/-/tags/VTM-10.0

2.1. Codec process of typical video codec

Figure 7 shows an example of a block diagram of an encoder for VVC that includes three in-loop filter blocks: deblocking filter (DF), Sample Adaptive Offset (SAO) and ALF . Unlike DF, which uses predefined filters, SAO and ALF by means of signalling codec side information of offset and filter coefficients, by adding offset and applying finite impulse response (FIR) filter, respectively. Use the original samples of the current image to reduce the mean square error between the original samples and the reconstructed samples. ALF is at the final processing stage of each picture and can be seen as a tool that attempts to capture and fix artifacts created by previous stages.

3. Examples of technical problems solved by the disclosed technical solutions

The current design of the IBC has the following problems:

1. Because many text characters and computer-generated graphics are symmetrical, symmetry is more often observed in pictures of screen content. Encoding and decoding a pattern and its symmetrical images independently is redundant.

4. Example Embodiments and Solutions

The following list should be considered as an example explaining the general inventive concept. These terms should not be interpreted narrowly. Furthermore, these items can be combined in any way.

min(x, y) returns the smaller of x and y.

max(x, y) returns the larger of x and y.

Symmetric/Mirror Intra Block Copy

It is proposed that before the IBC reference block is used to predict the current block, it is firstly determined whether the IBC reference block is flipped horizontally or vertically, or refined by other transformation methods (eg clockwise rotation or counterclockwise rotation). This method is called "symmetric IBC".

A "block" can be a transform unit (TU)/prediction unit (PU)/coding unit (CU)/transform block (TB)/prediction block (PB) /coding block (CB) or other video unit covering multiple samples/pixels. A TU/PU/CU may include one or more color components, such as for a dual-tree partition only a luma component and the current codec color component is luma; and for a dual-tree partition there are two chroma components and the current codec color component is the chrominance; or three color components for the single tree split case.

In the following disclosure, W and H represent the width and height of the block mentioned, or the width and height of the block mentioned in a specific color component (eg, the luminance of the 3 color components CU).

1. It is proposed to use multiple prediction methods for a block, wherein at least one of the multiple prediction methods is SIBC.

a. In one example, for the luma block, SIBC is utilized, while for the other two color components, the intra prediction method is applied.

b. In one example, for the luma block, SIBC is utilized, while for the other two color components, the inter prediction method is applied.

c. In one example, for the luma block, SIBC is utilized, while for the other two color components, the palette prediction method is applied.

d. In one example, for the luma block, SIBC is utilized, while for the other two color components, the prediction from the reconstructed luma block is applied.

Implicit Signaling Using SIBC

2. The determination to use SIBC for the first block may depend on the color components of the first block.

a. For example, SIBC can be applied to the first component of the first block (eg luma), while normal intra prediction is always used for the second component of the first block (eg Cb or Cr).

b. For example, SIBC can be applied to all color components of the first block.

3. The determination to use SIBC for the first block may depend on the dimensions of the first block.

a. SIBC applies only when W>=T1 and H>=T2. For example, T1=T2=4.

b. SIBC applies only when W<=T1 and H<=T2. For example, T1=T2=16.

c. SIBC is applicable only when max(W, H)<=T1. For example, T1=16.

d. SIBC is applicable only when min(W, H)<=T1. For example, T1=4.

e. SIBC is applicable only when W*H>=T1. For example, T1=16.

f. SIBC is applicable only when W*H<=T1. For example, T1=256.

g. SIBC is applicable only when max(W,H)/min(W,H)<=T1. For example T1=1 or T1=2.

h. In the bullet points above, ">=" can be replaced with ">" and "<=" can be replaced with "<".

4. The determination to use SIBC may further depend on the codec information of the current block.

a. In one example, the determination may further depend on block vector (BV) information.

i. In one example, BVy is zero, then vertical SIBC is not applied to the current block.

ii. In one example, BVx is zero, then horizontal SIBC is not applied to the current block.

b. In one example, whether SIBC is applied may depend on the ABVR precision of the IBC codec block.

i. In one example, SIBC is only applicable if the ABVR accuracy is equal to one or some specific values. For example, SIBC only applies if the ABVR precision is equal to 1 pixel.

c. In one example, the determination may further depend on the block position within the slice/slice/picture/sub-picture.

i. In one example, SIBC can be disabled if the block is at a picture boundary.

Explicit signaling using SIBC

5. Multiple levels of signaling indicating whether and/or how to apply SIBC may be utilized, with one signaling at a higher level (eg, at the level that includes more samples than blocks), one signaling at a lower level (eg, block level).

a. In one example, the first higher level is the sequence level and the second higher level is the picture level.

i. Optionally, in addition, the third higher level is the stripe level.

ii. Optionally, in addition, the lower level is a block level.

b. In one example, the first higher level is the picture level and the second higher level is the slice level.

i. Optionally, in addition, the lower level is the block level.

c. Optionally, furthermore, the indication at a higher level may be conditionally signalled, eg, depending on whether IBC is enabled.

d. In one example, the information on how to apply SIBC may include whether a SIBC (eg horizontal SIBC or vertical SIBC) applies to a video unit (eg sequence or picture or slice).

e. In one example, whether SIBC can be applied to a block can be signaled in higher level units, eg in SPS/sequence header/PPS/picture header/slice header.

i. For example, sibc_enable_flag may be signaled in the sequence header to indicate whether SIBC can be applied to the sequence.

1) sibc_enable_flag may be signaled only if IBC is enabled for the sequence (eg, ibc_enable_flag equals 1).

6. Information on whether to use SIBC for the first block (denoted as SIBC_flag) may be signalled conditionally.

a. If the SIBC_flag does not exist in the bitstream, the SIBC_flag is inferred to be a default value, such as 0.

b. SIBC_flag is only signaled when the first block uses IBC.

c. SIBC_flag is only signaled if the higher level element including the first block indicates that the use of SIBC is allowed.

d. If it is determined that SIBC is not applicable for this block, then SIBC_flag is not signaled.

e. Whether or not to signal SIBC_flag may depend on the dimension of the first block.

i. SIBC_flag is signaled only when W>=T1 and H>=T2. For example, T1=T2=4.

ii. SIBC_flag is only signaled when W<=T1 and H<=T2. For example, T1=T2=16.

iii. SIBC_flag is signaled only when max(W,H)<=T1. For example, T1=16.

iv. SIBC_flag is signaled only when min(W,H)<=T1. For example, T1=4.

v. SIBC_flag is signaled only when W*H>=T1. For example, T1=16.

vi. SIBC_flag is signaled only when W*H<=T1. . For example, T1=256.

vii. SIBC is applicable only when max(W,H)/min(W,H)<=T1. For example T1=1 or T1=2.

viii. In the bullet points above, ">=" can be replaced with ">" and "<=" can be replaced with "<".

7. After the first syntax element of the block (denoted SIBC_flag), a second syntax element (denoted sibc_dir_flag) indicating which SIBC to use may be signaled.

a. In one example, SIBC_flag indicates whether SIBC is applied to the block.

b.sibc_dir_flag indicates which SIBC is applied.

i. For example, sibc_dir_flag=0 means horizontal SIBC is used, and sibc_dir_flag=1 means vertical SIBC is used.

c.sibc_dir_flag is conditionally signaled by SIBC_flag.

i. Signal sibc_dir_flag only if SIBC_flag indicates that SIBC is used.

d. sibc_dir_flag and/or SIBC_flag can be encoded and decoded by arithmetic codec.

i.sibc_dir_flag and/or SIBC_flag can be bypassed.

ii. The sibc_dir_flag and/or SIBC_flag may be encoded and decoded with one or more contexts.

1) The context for encoding and decoding the SIBC_flag of the current block may depend on the SIBC_flag of neighboring blocks.

2) The context for encoding and decoding the sibc_dir_flag of the current block may depend on the sibc_dir_flag of the neighboring blocks.

3) The context can be derived based on the block dimension.

4) The context can be derived based on the codec information of neighboring blocks.

e. If it is determined that only one SIBC is applicable, the sibc_dir_flag is not signaled.

f. Optionally, which SIBC is applicable is not signaled but dynamically derived.

8. Information on whether SIBC is used for the first block and if SIBC is used, which SIBC (denoted as SIBC_type_idx) is used may be signaled with a non-binary syntax element.

a. In one example, the original IBC (ie, without any transform) is further treated as a new transform (eg, NON_TRANSFORM) type of SIBC mode.

b. In one example, non-binary syntax elements may be binarized into binary strings with truncated unary, unary, fixed-length, K-th order exp-golomb, or the like.

i. Optionally, in addition, at least one bin is context encoded and decoded, and at least another bin is bypass encoded.

ii. Optionally, furthermore, the same context is utilized for at least two bins.

iii. Optionally, additionally, different contexts are utilized for at least two bins in the binary string.

iv. The context can be derived based on the block dimension.

v. The context can be derived based on the codec information of neighboring blocks.

c. In one example, when a non-binary syntax element is equal to K (eg, K=0), SIBC is disabled and the original IBC design is used (ie, without any transformation).

i. Optionally, in addition, enable SIBC when non-binary syntax elements are not equal to K

ii. Optionally, in addition, when the non-binary syntax element is not equal to K and equal to L, the Lth transform of the SIBC method is applied.

d. In one example, when the first bin of a non-binary syntax element is equal to K (eg, K=0), SIBC is disabled and the original IBC design is used (ie, without any transformation).

i. Optionally, in addition, SIBC is enabled when the first binary bit is not equal to K.

e. In one example, the mapping between decoded values and conversion types of non-binary syntax elements may be fixed.

i. Optionally, the mapping can be determined dynamically.

5. Examples

5.1. Example #1

This section gives an example of a solution to the Implicit Selection of TransformSkip (ISTS) mode. Basically, it follows the design principle of Implicit Selection of Transform (IST) adopted by AVS3. A high-level flag is signaled in the picture header to indicate that ISTS is enabled. If ISTS is enabled, the allowed transform set is set to {DCT-II TS}, and the determination of the TS mode is based on the parity of the number of non-zero coefficients in the block. Simulation results show that, compared with HPM6.0, the proposed ISTS achieves 15.86% and 12.79% bit rate reduction for screen content encoding and decoding under AI and RA configurations, respectively. It can be asserted that the increase in encoder and decoder complexity is negligible.

5.1.2. The proposed method

In this contribution, SIBC is proposed. A flag is signaled in each IBC codec and high precision ABVR CU to indicate whether the prediction mode of the current CU is symmetric and the CU size is in the range of 4x4 to 32x32. 0 indicates normal IBC mode, 1 indicates SIBC mode. When SIBC is applied, one more 1-bit flag is signaled to indicate whether horizontal or vertical flipping is used. After horizontal flipping, the sample value denoted as S(x,y) at coordinates (x,y) is derived as,

S(x,y)=S'(W-1-x,y), (1)

where S' represents the sample value before flipping, and W represents the block width. Similarly, after vertical flip, the sample value denoted as S(x,y) is derived as,

S(x, y)=S'(x, H-1-y), (1)

where H represents the block height.

5.1.3. Proposed Modifications to Syntax Tables, Semantics and Decoding Processes

标记。Newly added changes to the syntax table, semantics, and decoding process are highlighted with bold underline , and deleted text is highlighted with

mark.

7.1.2.2 Sequence header

Table 14 Sequence header definitions

7.1.6 Codec unit

Table 15 Codec unit definitions

7.2.2.2 Sequence header

The symmetric intra block copy prediction enable flag sibc_enable_flag is a binary variable. A value of '1' means yes Use symmetric intra block copy prediction method; a value of '0' means no symmetric intra block copy prediction method is used. The value of SibcEnableFlag is equal to sibc_enable_flag. If the flag sibc_enable_ is not present in the bitstream flag, the value of SibcEnableFlag is 0.

7.2.6 Codec unit

The symmetric intra block copy mode flag sibc_flag is a binary variable. A value of '1' indicates that the current codec unit uses Use symmetric intra-block copy prediction mode; a value of '0' indicates that the current codec does not use symmetric intra-block copy prediction model. The value of SibcFlag is equal to sibc_flag. If sibc_flag is not present in the bitstream, the value of SibcFlag is equal to 0.

The symmetric intra block copy mode direction flag sibc_dir_flag is a binary variable. A value of '1' indicates the current codec The code unit uses a vertically symmetric intra-block copy prediction mode; a value of '0' indicates that the current codec uses a horizontally symmetric frame Intra-block copy prediction mode. The value of SibcDirFlag is equal to sibc_dir_flag. If sibc_dir_ is not present in the bitstream flag, the value of SibcDirFlag is equal to 0.

8.3.3.2 Derivation of binary symbolic models

8.3.3.2.1 Derivation of a binary symbolic model

Table 61 ctxIdxStart and ctxIdxInc corresponding to syntax elements

syntax element ctxIdxInc ctxIdxStart number of ctx abvr_index binIdx 109 2 sbic_flag 0 111 1 sibc_dir_flag 0 112 1

9.8 Symmetric/Mirror Intra Block Copy Prediction

9.8.2 Derivation of predicted samples

If the current prediction block is a luminance prediction block, record the position of the upper left corner sample of the current prediction block in the luminance sample matrix of the current image as (xE, yE), and perform the following operations: 1. When SibcFlag is 0, the luminance prediction sample The value of the element predMatrixIbc[x][y] in the matrix predMatrixIbc is the unfiltered reconstruction of the current image. The position in the luminance sample matrix is (((xE+x))+BvE_x>>2,(yE+y) )+BvE_y>>2))) sample value. where BvE_x and BvE_y are the horizontal and vertical components of the current prediction unit block vector BvE, respectively. 2. When SibcFlag is 1 and SibcDirFlag is 0, the value of the element predMatrixIbc[x][y] in the luminance prediction sample matrix predMatrixIbc is the unfiltered reconstruction of the current image. The position in the luminance sample matrix is (((xE +W-1-x))+BvE_x>>2, (yE+y))+BvE_y>>2))) sample value. where W is the width of the luma prediction sample matrix. 3. When SibcFlag is 1 and SibcDirFlag is 1, the value of the element predMatrixIbc[x][y] in the luminance prediction sample matrix predMatrixIbc is the integer pixel precision of the unfiltered reconstruction of the current image. The position in the luminance sample matrix is (((xE +x))+BvE_x>>2,(yE+H- 1-y))+BvE_y>>2))) sample value. where H is the height of the luma prediction sample matrix.

If the current prediction block is a chroma prediction block, denote the position of the upper-left corner sample of the luma prediction block containing the upper-left corner sample of the current prediction block in the luma sample matrix of the current image as (xE, yE), and perform the following operations: 1. When SibcFlag is 0 , the value of the element predMatrixIBc[x][y] in the chroma prediction sample matrix predMatrixIbc is the position in the 1/2 precision chroma sample matrix of the unfiltered reconstruction of the current image (((xE+ 2×x))+BvC_x>>2,(yE+2×y))+BvC_y>>2))) sample value. Wherein, BvC_x and BvC_y are respectively the horizontal component and the vertical component of the block vector BvE of the spatial motion information storage unit containing the lower right corner sample of the current prediction block. The element value of each position in the chroma 1/2 precision sample matrix of the reference image is obtained by interpolation. 2. When SibcFlag is 1 and SibcDirFlag is 0, the value of the element predMatrixIBc[x][y] in the chrominance prediction sample matrix predMatrixIbc is the position in the 1/2-precision chroma sample matrix of the unfiltered reconstruction of the current image ( ((xE+2×(W-1-x)))+BvC_x>>2,(yE+2×y))+BvC_y>>2))) sample value. where W is the width of the chrominance prediction sample matrix. 3. When SibcFlag is 1 and SibcDirFlag is 1, the value of the element predMatrixIBc[x][y] in the chrominance prediction sample matrix predMatrixIbc is the position in the 1/2 precision chroma sample matrix of the unfiltered reconstruction of the current image ( ((xE+2×x))+BvC_x>>2,(yE+2×(H-1-y)))+BvC_y>>2))) sample value. where H is the height of the chrominance prediction sample matrix.

1 is a block diagram illustrating an example video processing system 1900 in which various techniques disclosed herein may be implemented. Various implementations may include some or all of the components of system 1900 . System 1900 can include input 1902 for receiving video content. Video content may be received in raw or uncompressed format, eg, 8- or 10-bit multi-component pixel values, or may be in compressed or encoded format. Input 1902 may represent a network interface, a peripheral bus interface, or a storage interface. Examples of network interfaces include wired interfaces such as Ethernet, Passive Optical Network (PON), etc., and wireless interfaces such as Wi-Fi or cellular interfaces.

System 1900 can include a codec component 1904 that can implement the various codecs or encoding methods described in this document. The codec component 1904 can reduce the average bit rate of the video from the input 1902 to the output of the codec component 1904 to produce a codec representation of the video. Codec techniques are therefore sometimes referred to as video compression or video transcoding techniques. The output of codec component 1904 may be stored, or transmitted via a communication connection as represented by component 1906. The stored or communicated bitstream (or codec) representation of video received at input 1902 may be used by component 1908 to generate pixel values or communicated to display interface 1910 for displayable video. The process of generating user-viewable video from a bitstream representation is sometimes referred to as video decompression. Furthermore, although certain video processing operations are referred to as "codec" operations or tools, it will be understood that the codec tools or operations are used at the encoder and the corresponding decoding tools or operations that invert the codec result will be decoded by device executes.

Examples of peripheral bus interfaces or display interfaces may include Universal Serial Bus (USB), or High Definition Multimedia Interface (HDMI), or Displayport, and the like. Examples of storage interfaces include SATA (Serial Advanced Technology Attachment), PCI, IDE interfaces, and the like. The techniques described in this document may be embodied in various electronic devices, such as mobile phones, laptop computers, smart phones, or other devices capable of performing digital data processing and/or video display.

FIG. 2 is a block diagram of a video processing apparatus 3600 . Apparatus 3600 may be used to implement one or more of the methods described herein. Apparatus 3600 may be embodied in a smartphone, tablet, computer, Internet of Things (IoT) receiver, or the like. Apparatus 3600 may include one or more processors 3602, one or more memories 3604, and video processing hardware 3606. The processor(s) 3602 may be configured to implement one or more of the methods described in this document. Memory(s) 604 may be used to store data and code for implementing the methods and techniques described herein. Video processing hardware 606 may be used to implement some of the techniques described in this document in hardware circuitry. In some embodiments, video processing hardware 3606 may be included at least in part in processor 3602 (eg, a graphics co-processor).

4 is a block diagram illustrating an example video codec system 100 that may utilize the techniques of this disclosure.

As shown in FIG. 4 , the video codec system 100 may include a source device 110 and a target device 120 . The source device 110 generates encoded video data, where the source device 110 may be referred to as a video encoding device. Target device 120 may decode encoded video data generated by source device 110, and target device 120 may be referred to as a video decoding device.

Source device 110 may include video source 112 , video encoder 114 , and input/output (I/O) interface 116 .

Video source 112 may include a source, such as a video capture device, an interface that receives video data from a video content provider, and/or a computer graphics system used to generate the video data, or a combination of these sources. Video data may include one or more pictures. Video encoder 114 encodes video data from video source 112 to generate a bitstream. A bitstream may include a sequence of bits that form a codec representation of the video data. The bitstream may include codec pictures and related data. A codec picture is a codec representation of a picture. Relevant data may include sequence parameter sets, picture parameter sets, and other syntax structures. The I/O interface 116 may include a modulator/demodulator (modem) and/or a transmitter. The encoded video data may be transmitted directly to the target device 120 via the I/O interface 116 over the network 130a. The encoded video data may also be stored on the storage medium/server 130b for access by the target device 120 .

Target device 120 may include I/O interface 126 , video decoder 124 and display device 122 .

I/O interface 126 may include a receiver and/or a modem. I/O interface 126 may obtain encoded video data from source device 110 or storage medium/server 130b. Video decoder 124 may decode the encoded video data. Display device 122 may display the decoded video data to a user. Display device 122 may be integrated with target device 120, or may be external to target device 120 configured to interface with an external display device.

Video encoder 114 and video decoder 124 may operate in accordance with video compression standards, such as the High Efficiency Video Codec (HEVC) standard, the Versatile Video Codec (VVM) standard, and other current and/or additional standards.

FIG. 5 is a block diagram illustrating an example of a video encoder 200 , which may be the video encoder 114 in the system 100 shown in FIG. 4 .

Video encoder 200 may be configured to perform any or all of the techniques of this disclosure. In the example of FIG. 5, video encoder 200 includes a number of functional components. The techniques described in this disclosure may be shared among various components of video encoder 200 . In some examples, a processor may be configured to perform any or all of the techniques described in this disclosure.

The functional components of the video encoder 200 may include a segmentation unit 201, a prediction unit 202 (which may include a mode selection unit 203, a motion estimation unit 204, a motion compensation unit 205, and an intra prediction unit 206), a residual generation unit 207, a transform unit 208 , a quantization unit 209 , an inverse quantization unit 210 , an inverse transform unit 211 , a reconstruction unit 212 , a buffer 213 and an entropy encoding unit 214 .

In other examples, video encoder 200 may include more, fewer, or different functional components. In an example, prediction unit 202 may include an intra block copy (IBC) unit. The IBC unit may perform prediction in IBC mode, where at least one reference picture is the picture in which the current video block is located.

Furthermore, some components such as motion estimation unit 204 and motion compensation unit 205 may be highly integrated, but are shown separately in the example of FIG. 5 for purposes of explanation.

The partitioning unit 201 may partition the picture into one or more video blocks. Video encoder 200 and video decoder 300 may support various video block sizes.

The mode selection unit 203 may select one of the codec modes (eg, intra or inter) based on the error result, and provide the resulting intra codec block or inter codec block to the residual generation unit 207 to generate a residual difference block data, and provided to reconstruction unit 212 to reconstruct the coded block for use as a reference picture. In some examples, mode selection unit 203 may select a combination of intra and inter prediction modes (CIIP), where prediction is based on an inter prediction signal and an intra prediction signal. In the case of inter prediction, the mode selection unit 203 may also select the resolution (eg, sub-pixel or integer-pixel precision) of the motion vector of the block.

To perform inter prediction on the current video block, motion estimation unit 204 may generate motion information for the current video block by comparing one or more reference frames from buffer 213 with the current video block. Motion compensation unit 205 may determine the predicted video block for the current video block based on the motion information and decoding samples from buffer 213 of pictures other than pictures associated with the current video block.

Motion estimation unit 204 and motion compensation unit 205 may perform different operations on the current video block, eg, depending on whether the current video block is in an I slice, a P slice, or a B slice.

In some examples, motion estimation unit 204 may perform uni-directional prediction on the current video block, and motion estimation unit 204 may search list 0 or list 1 reference pictures for reference video blocks of the current video block. Motion estimation unit 204 may then generate a reference index indicating the reference picture in List 0 or List 1, the reference index containing the reference video block and a motion vector indicating the spatial displacement between the current video block and the reference video block. Motion estimation unit 204 may output the reference index, prediction direction indicator, and motion vector as motion information for the current video block. Motion compensation unit 205 may generate a predicted video block for the current block based on the reference video block indicated by the motion information of the current video block.

In other examples, motion estimation unit 204 may perform bidirectional prediction on the current video block, motion estimation unit 204 may search the reference pictures in list 0 for reference video blocks of the current video block, and may also search the current video in list 1 Another reference video block for the block. Motion estimation unit 204 may then generate a reference index indicating the reference pictures in List 0 and List 1 containing the reference video block and a motion vector indicating the spatial displacement between the reference video block and the current video block. The motion estimation unit 204 may output the reference index and motion vector of the current video block as motion information of the current video block. Motion compensation unit 205 may generate a predicted video block for the current video block based on the reference video block indicated by the motion information of the current video block.

In some examples, motion estimation unit 204 may output a complete set of motion information for decoding processing by a decoder.

In some examples, motion estimation unit 204 may not output the complete set of motion information for the current video. Instead, motion estimation unit 204 may signal motion information for the current video block with reference to motion information for another video block. For example, motion estimation unit 204 may determine that the motion information of the current video block is sufficiently similar to the motion information of neighboring video blocks.

In one example, motion estimation unit 204 may indicate a value in a syntax structure associated with the current video block that indicates to video decoder 300 that the current video block has the same motion information as another video block.

In another example, motion estimation unit 204 may identify another video block and a motion vector difference (MVD) in a syntax structure associated with the current video block. The motion vector difference indicates the difference between the motion vector of the current video block and the motion vector of the indicated video block. Video decoder 300 may use the motion vector of the indicated video block and the motion vector difference to determine the motion vector of the current video block.

As discussed above, video encoder 200 may predictively signal motion vectors. Two examples of prediction signaling techniques that may be implemented by video encoder 200 include Advanced Motion Vector Prediction (AMVP) and Merge Mode signaling.

Intra-prediction unit 206 may perform intra-prediction on the current video block. When intra-prediction unit 206 performs intra-prediction on the current video block, intra-prediction unit 206 may generate prediction data for the current video block based on decoded samples of other video blocks in the same picture. The prediction data for the current video block may include the predicted video block and various syntax elements.

Residual generation unit 207 may generate residual data for the current video block by subtracting (eg, indicated by a minus sign) the predicted video block(s) of the current video block from the current video block. Residual data for the current video block may include residual video blocks corresponding to different point components of samples in the current video block.

In other examples, such as in skip mode, there may be no residual data for the current video block for the current video block, and residual generation unit 207 may not perform a subtraction operation.

Transform processing unit 208 may generate one or more transform coefficient video blocks for the current video block by applying one or more transforms to the residual video block associated with the current video block.

After transform processing unit 208 generates the transform coefficient video block associated with the current video block, quantization unit 209 may quantize the quantization parameter (QP) values associated with the current video block based on one or more quantization parameter (QP) values associated with the current video block. Transform coefficient video block.

Inverse quantization unit 210 and inverse transform unit 211 may apply inverse quantization and inverse transform, respectively, to transform coefficient video blocks to reconstruct residual video blocks from the transform coefficient video blocks. Reconstruction unit 212 may add the reconstructed residual video block to corresponding samples from the one or more predicted video blocks generated by prediction unit 202 to produce a reconstructed video block associated with the current block for storage in a buffer. 213.

After reconstruction unit 212 reconstructs the video block, in-loop filtering operations may be performed to reduce video blockiness in the video block.

Entropy encoding unit 214 may receive data from other functional components of video encoder 200 . When entropy encoding unit 214 receives data, entropy encoding unit 214 may perform one or more entropy encoding operations to generate entropy encoded data and output a bitstream including the entropy encoded data.

FIG. 6 is a block diagram illustrating an example of a video decoder 300 , which may be the video decoder 114 in the system 100 shown in FIG. 4 .

Video decoder 300 may be configured to perform any or all of the techniques of this disclosure. In the example of FIG. 6, video decoder 300 includes a number of functional components. The techniques described in this disclosure may be shared among various components of video decoder 300 . In some examples, a processor may be configured to perform any or all of the techniques described in this disclosure.

In the example of FIG. 6 , the video decoder 300 includes an entropy decoding unit 301 , a motion compensation unit 302 , an intra prediction unit 303 , an inverse quantization unit 304 , an inverse transform unit 305 , and a reconstruction unit 306 and a buffer 307 . In some examples, video decoder 300 may perform a decoding process that is generally the inverse of the encoding process described for video encoder 200 (FIG. 5).

The entropy decoding unit 301 may retrieve the encoded bitstream. The encoded bitstream may include entropy encoded video data (eg, encoded blocks of video data). The entropy decoding unit 301 may decode the entropy coded video data, and from the entropy decoded video data, the motion compensation unit 302 may determine motion information including a motion vector, motion vector precision, reference picture list index, and other motion information. Motion compensation unit 302 may determine such information, eg, by performing AMVP and Merge modes.

Motion compensation unit 302 may generate motion compensation blocks, which may perform interpolation based on interpolation filters. The identifier of the interpolation filter to be used with sub-pixel precision may be included in the syntax element.

Motion compensation unit 302 may use interpolation filters as used by video encoder 200 during encoding of the video block to calculate interpolation of sub-integer pixels of the reference block. Motion compensation unit 302 may determine an interpolation filter used by video encoder 200 from the received syntax information and use the interpolation filter to generate a prediction block.

Motion compensation unit 302 may use some syntax information to determine the size of blocks used to encode frame(s) and/or slice(s) of an encoded video sequence, each macroblock describing a picture of an encoded video sequence Partition information of how it was partitioned, a mode indicating how each partition was encoded, one or more reference frames (and reference frame lists) for each inter-coded block, and other information used to decode the encoded video sequence.

The intra prediction unit 303 may form a prediction block from spatially adjacent blocks using, for example, an intra prediction mode received in the bitstream. The inverse quantization unit 303 inversely quantizes, ie, dequantizes, the quantized video block coefficients provided in the bitstream and decoded by the entropy decoding unit 301 . The inverse transform unit 303 applies the inverse transform.

Reconstruction unit 306 may add the residual block to the corresponding prediction block generated by motion compensation unit 202 or intra prediction unit 303 to form a decoded block. If desired, a deblocking filter can also be applied to filter the decoded block in order to remove blockiness. The decoded video blocks are then stored in buffer 307, providing reference blocks for subsequent motion compensation/intra prediction, and also producing decoded video for presentation on a display device.

Next, a list of preferred solutions for some embodiments is provided.

The following solutions illustrate example embodiments of the techniques discussed in the previous section (eg, item 1).

1. A method of video processing (eg, the method 700 depicted in FIG. 3 ), comprising: performing (702) a conversion between a video block of video comprising two or more color component blocks and a bitstream representation of the video; Wherein, according to the encoding and decoding rules, two or more color component blocks are encoded and decoded using multiple prediction methods, and at least one of the multiple prediction methods is a Symmetric Intra Block Copy (SIBC) method.

2. The method of solution 1, wherein the rules specify that the SIBC method is used for a luma component block of the two or more color component blocks, and the other color component blocks of the two or more color component blocks are used Intra-frame encoding and decoding methods.

3. The method of solution 1, wherein the rules specify that the SIBC method is used for a luma component block of the two or more color component blocks, and the other color component blocks of the two or more color component blocks are used Interframe encoding and decoding methods.

4. The method of solution 1, wherein the rules specify that the SIBC method is used for a luma component block of the two or more color component blocks, and the other color component blocks of the two or more color component blocks are used Palette prediction codec method.

5. The method of solution 1, wherein the rules specify that the SIBC method is used for a luma component block of the two or more color component blocks, and a reconstructed luma block of the luma component block is used to encode and decode the two or more luma component blocks. Other color component blocks of the color component block.

The following solutions illustrate example embodiments of the techniques discussed in the previous section (eg, item 2).

6. A video processing method, comprising: for conversion between a video block comprising one or more color component blocks and a codec representation of the video, determining whether to use symmetric intra-block copying (SIBC) according to codec rules a method to encode and decode a color component block of a video block; and perform a conversion based on the determination.

7. The method of solution 6, wherein the codec rules specify that the luma component block is encoded and decoded using the SIBC method, and the other color component blocks are encoded and decoded using the intra prediction method.

8. The method of solution 6, wherein the encoding and decoding rules specify that each of the one or more component blocks is encoded and decoded using the SIBC method.

The following solutions illustrate example embodiments of the techniques discussed in the previous section (eg, item 3).

9. The method of solution 6, wherein the rules are based on the dimensions of the video blocks.

10. The method of solution 9, wherein the rules state that the following conditions are met for use of the SIBC method:

a. SIBC is applicable only when W>=T1 and H>=T2,

b. SIBC applies only when W<=T1 and H<=T2,

c. SIBC is applicable only when max(W, H)<=T1,

d. SIBC is applicable only when min(W, H)<=T1,

e. SIBC is applicable only when W*H>=T1,

f. SIBC is applicable only when W*H<=T1,

g. SIBC is applicable only when max(W, H)/min(W, H)<=T1;

where T1 and T2 are rational numbers.

11. The method of solution 10, wherein T1=1, 2, 4, 8, 16 or 256 and T2=4 or 16.

The following solutions illustrate example embodiments of the techniques discussed in the previous section (eg, item 4).

12. The method of any of solutions 1-11, wherein the rules depend on codec information of the video blocks.

13. The method of solution 12, wherein the codec information includes information on whether the video block uses block vector codec.

The following solutions illustrate example embodiments of the techniques discussed in the previous sections (eg, items 5-8).

14. A method of video processing comprising: performing a conversion between a video block of a video comprising one or more color component blocks and a bitstream representation of the video, wherein the bitstream representation conforms to format rules, wherein the format rules specify Whether and how to use the Symmetric Intra Block Copy (SIBC) method to encode and decode the color component blocks of the video block is indicated in the bitstream representation.

15. The method of solution 14, wherein the format rule specifies that for indicating that the bitstream representation includes at least a first syntax element at a first codec level and a second syntax element at a second codec level, wherein, The first level is a higher level than the video block level, and the second level is a video block level or lower.

16. The method of solution 14, wherein the format rule provisions conditionally include syntax elements for indication based on codec characteristics.

17. The method of solution 16, wherein the codec characteristics include whether intra block copy mode is enabled for the video block.

18. The method of solution 16, wherein the codec characteristic includes a dimension of the video block.

19. The method of any of solutions 14-18, wherein the format rule specification includes two fields to indicate use of the SIBC method, wherein the first field signals the use of the SIBC method, and the first field The second field after that indicates the type of symmetry used by the SIBC method.

20. The method of solution 19, wherein the first field and the second field comprise non-metasyntax elements.

21. The method of any of solutions 1-20, wherein converting comprises generating a bitstream representation from the video.

22. The method of any of solutions 1-20, wherein converting comprises decoding a bitstream representation to generate a video.

23. A video decoding apparatus comprising a processor configured to implement the method of one or more of solutions 1 to 22.

24. A video encoding apparatus comprising a processor configured to implement the method of one or more of solutions 1 to 22.

25. A computer program product having computer code stored thereon which, when executed by a processor, causes the processor to implement the method of any one of solutions 1 to 22.

26. A computer-readable medium storing a bitstream representation generated according to any of solutions 1 to 22.

27. The method, apparatus or system described in this document.

In the solution described herein, the encoder can comply with the format rules by producing a codec representation according to the format rules. In the solution described herein, a decoder can use format rules to parse syntax elements in a codec representation to produce decoded video, knowing the presence and absence of syntax elements from the format rules.

In this document, the term "video processing" may refer to video encoding, video decoding, video compression, or video decompression. For example, a video compression algorithm may be applied during the conversion from a pixel representation of a video to a corresponding bitstream representation, and vice versa. The bitstream representation of the current video block may, for example, correspond to bits within the bitstream that are collocated or interspersed in different places, as defined by the syntax. For example, macroblocks may be encoded from transformed and coded error residual values and also using bits in headers and other fields in the bitstream. Furthermore, during conversion, the decoder can parse the bitstream based on this determination, knowing that some fields may or may not be present, as described in the solution above. Similarly, an encoder may determine to include or exclude certain syntax fields, and generate the codec representation accordingly by including or excluding syntax fields from the codec representation.

The disclosed and other solutions, examples, embodiments, modules, and functional operations described in this document may operate in digital electronic circuitry, or in computer software, firmware, or hardware (including the structures disclosed in this document and their structural equivalents) ), or a combination of one or more of them. The disclosed and other embodiments may be implemented as one or more computer program products, ie, one or more modules of computer program instructions encoded on a computer-readable medium for execution by a data processing apparatus or Controls the operation of the data processing device. The computer-readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, a combination of matter that affects a machine-readable propagated signal, or a combination of one or more of these. The term "data processing apparatus" includes all apparatus, devices, and machines for processing data, including, for example, a programmable processor, a computer, or multiple processors or computers. In addition to hardware, an apparatus may include code that creates an operating environment for the computer program in question, eg, code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of these . A propagated signal is an artificially generated signal, such as a machine-generated electrical, optical or electromagnetic signal, that is generated to encode information for transmission to a suitable receiver device.

A computer program (also known as a program, software, software application, script, or code) may be written in any form of programming language, including compiled or interpreted languages, and it may be deployed in any form, including as a stand-alone program or as a A module, component, subroutine, or other unit used in a computing environment. A computer program does not necessarily correspond to a file in a file system. Programs may be stored in part of a file that holds other programs or data (for example, one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinators. in a file (eg, a file that stores one or more modules, subprograms, or portions of code). A computer program can be deployed to run on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.

The processes and logic flows described in this document can be performed by one or more programmable processors running one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, eg, an FPGA (Field Programmable Gate Array) or an ASIC (application-specific integrated circuit).

Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Typically, a processor will receive instructions and data from read-only memory or random access memory, or both. The basic elements of a computer are a processor for executing instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include, or be operably coupled to receive data from, or to, one or more mass storage devices (eg, magnetic, magneto-optical, or optical disks) for storing data The one or more mass storage devices transfer data to, receive data from, and transfer data to. However, a computer does not need such a device. Computer-readable media suitable for storage of computer program instructions and data include all forms of non-volatile memory, media, and memory devices, including, for example, semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks, such as internal hard disks or removable disks. magnetic disks; magneto-optical disks; and CD-ROM and DVD-ROM disks. The processor and memory may be supplemented by or incorporated in special purpose logic circuitry.

Although this patent document contains many details, these should not be construed as limitations on the scope of any subject matter or what may be claimed, but as descriptions of features specific to particular embodiments of particular technologies. Certain features that are described in this patent document in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Furthermore, although features may be described above as functioning in certain combinations and even originally claimed as such, in some cases one or more features from the claimed combination may be excluded from the combination and the claimed combination Variations of sub-combinations or sub-combinations can be targeted.

Similarly, although operations in the figures are depicted in a particular order, this should not be construed as requiring that such operations, or all illustrated operations be performed, in the particular order shown, or sequential order, to be performed to achieve desirable results. Furthermore, the separation of various system components in the embodiments described in this patent document should not be construed as requiring such separation in all embodiments.

Only some implementations and examples have been described, and other implementations, enhancements and variations are possible based on what is described and illustrated in this patent document.

Claims (26)

1. A video processing method, comprising: performing a conversion between a video block of video comprising two or more color component blocks and a bitstream representation of the video; Wherein, the two or more color component blocks are encoded and decoded using multiple prediction methods according to encoding and decoding rules, and at least one of the multiple prediction methods is a Symmetric Intra Block Copy (SIBC) method. 2. The method of claim 1, wherein the rule specifies that a SIBC method is used for a luminance component block of the two or more color component blocks, and a The other color component blocks use the intra-coding method. 3. The method of claim 1, wherein the rule specifies that a SIBC method is used for a luma component block of the two or more color component blocks, and a The other color component blocks use the inter-coding method. 4. The method of claim 1, wherein the rule specifies that a SIBC method is used for a luma component block of the two or more color component blocks, and a The other color component blocks use the palette prediction codec method. 5. The method of claim 1, wherein the rule specifies that a SIBC method is used for a luma component block of the two or more color component blocks, and a reconstructed luma block of the luma component block is used for coding. Other color component blocks of the two or more color component blocks are decoded. 6. A video processing method, comprising: For a conversion between a video block of video that includes one or more color component blocks and a codec representation of the video, it is determined according to codec rules whether to use the Symmetric Intra Block Copy (SIBC) method to codec the video block The color component block of ; and The conversion is performed based on the determination. 7. The method of claim 6, wherein the encoding and decoding rules specify that the luminance component block is encoded and decoded using the SIBC method, and the other color component blocks are encoded and decoded using the intra prediction method. 8. The method of claim 6, wherein the encoding and decoding rules specify that each of the one or more component blocks is encoded and decoded using a SIBC method. 9. The method of claim 6, wherein the rules are based on dimensions of the video blocks. 10. The method of claim 9, wherein the rules specify that the following conditions are met for the use of the SIBC method: a. SIBC is applicable only when W>=T1 and H>=T2, b. SIBC applies only when W<=T1 and H<=T2, c. SIBC is applicable only when max(W, H)<=T1, d. SIBC is applicable only when min(W, H)<=T1, e. SIBC is applicable only when W*H>=T1, f. SIBC is applicable only when W*H<=T1, g. SIBC is applicable only when max(W, H)/min(W, H)<=T1; where T1 and T2 are rational numbers. 11. The method of claim 10, wherein T1=1, 2, 4, 8, 16, or 256, and T2=4 or 16. 12. The method of claim 6, wherein the rule depends on codec information for the video block. 13. The method of claim 12, wherein the codec information includes information on whether the video block uses block vector codec. 14. A video processing method, comprising: performing a conversion between a video block of video comprising one or more color component blocks and a bitstream representation of said video, Wherein, the bit stream indicates that the format rules are met, Wherein, the format rules specify whether and how to use a Symmetric Intra Block Copy (SIBC) method to indicate in the bitstream representation whether and how the color component blocks of the video block are encoded or decoded. 15. The method of claim 14, wherein the format rule specifies that for the indication, the bitstream representation includes at least a first syntax element at a first codec level and a first syntax element at a second codec level. Two syntax elements, wherein the first codec level is a higher level than a video block level, and the second codec level is a video block level or a lower level. 16. The method of claim 14, wherein the format rule specifies that syntax elements are conditionally included for the indication based on codec characteristics. 17. The method of claim 16, wherein the codec characteristic includes whether an intra-block copy mode is enabled for the video block. 18. The method of claim 16, wherein the codec characteristic includes a dimension of the video block. 19. The method of claim 14, wherein the format rule specification includes two fields to indicate use of the SIBC method, wherein the first field signals the use of the SIBC method, and after the first field The second field of indicates the type of symmetry used by the SIBC method. 20. The method of claim 19, wherein the first field and the second field comprise non-binary syntax elements. 21. The method of claim 1, wherein the converting comprises generating the bitstream representation from the video. 22. The method of claim 1, wherein the converting comprises decoding the bitstream representation to generate the video. 23. A video decoding apparatus comprising a processor configured to implement the method of one or more of claims 1 to 22. 24. A video encoding apparatus comprising a processor configured to implement the method of one or more of claims 1 to 22. 25. A computer program product having computer code stored thereon which, when executed by a processor, causes the processor to implement the method of any one of claims 1 to 22. 26. A computer-readable medium storing a bitstream representation generated according to any of claims 1 to 22.

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