CN114598319A

CN114598319A - Method for reducing loop stability time of phase-locked loop, phase-locked loop and phase-locked loop adjusting system

Info

Publication number: CN114598319A
Application number: CN202210209549.6A
Authority: CN
Inventors: 杨建伟; 周文婷
Original assignee: Calterah Semiconductor Technology Shanghai Co Ltd
Current assignee: Calterah Semiconductor Technology Shanghai Co Ltd
Priority date: 2022-03-03
Filing date: 2022-03-03
Publication date: 2022-06-07

Abstract

The application relates to a method for reducing the loop stability time of a phase-locked loop, a phase-locked loop and a phase-locked loop adjusting system. The phase-locked loop is used for outputting a frequency-modulated continuous wave signal, the period of the frequency-modulated continuous wave signal comprises an effective signal stage and an ineffective signal stage, and the phase-locked loop comprises a charge pump; the method for reducing the loop stability time of the phase-locked loop comprises the following steps: aiming at any period of the frequency-modulated continuous wave signal, in the invalid signal stage, the working current of the charge pump is a first current; in the effective signal stage, the working current of the charge pump is a second current; wherein the first current is greater than the second current. The method for reducing the loop stability time of the phase-locked loop can effectively improve the frequency response speed and the signal stability of the FMCW signal.

Description

Method for reducing loop stability time of phase-locked loop, phase-locked loop and phase-locked loop adjusting system

Technical Field

The invention relates to the technical field of sensing, in particular to a method for reducing the loop stability time of a phase-locked loop, the phase-locked loop and a phase-locked loop adjusting system.

Background

Frequency Modulated Continuous Wave (FMCW) may be used for radar ranging. In an FMCW radar, a Phase-Locked Loop (PLL) circuit is generally provided to provide a continuously frequency-adjustable swept waveform.

Currently, a frequency modulated continuous wave phase locked loop (FMCW PLL) mostly uses a two-point modulation (two-point modulation) for modulation. However, the two-point modulation technique is complicated, occupies a large chip area, and requires a complicated digital circuit for assistance, which easily affects the frequency response speed and signal stability of the FMCW signal.

Disclosure of Invention

In view of the above, it is necessary to provide a method for reducing the loop settling time of a phase-locked loop, a phase-locked loop and a phase-locked loop adjusting system to improve the frequency response speed and signal stability of the FWCM signal.

One embodiment of the present application provides a method for reducing loop settling time of a phase-locked loop, wherein the phase-locked loop is configured to output a frequency-modulated continuous wave signal, a cycle of the frequency-modulated continuous wave signal includes an active signal phase and an inactive signal phase, and the phase-locked loop includes a charge pump; the method comprises the following steps: aiming at any period of the frequency modulation continuous wave signal, in an invalid signal stage, the working current of the charge pump is a first current; in the effective signal stage, the working current of the charge pump is a second current; wherein the first current is greater than the second current.

According to the method for reducing the loop stability time of the phase-locked loop, when the frequency modulation continuous wave signal is in an invalid signal stage, the working current of the charge pump is set to be a first current which is larger, so that the loop bandwidth of the PLL is increased, the loop stability time is reduced, and the frequency modulation continuous wave signal can be rapidly stabilized; when the frequency modulation continuous wave signal is in an effective signal stage, the working current of the charge pump is set to be a smaller second current, so that the loop bandwidth of the PLL is reduced, low-pass noise inside the loop is effectively filtered, and the frequency modulation continuous wave signal has better signal stability. Based on the relation between the working current of the charge pump and the loop bandwidth of the phase-locked loop, the loop bandwidth of the phase-locked loop is adjusted by changing the working current of the charge pump so as to modulate the FMCW signal, and the frequency response speed and the signal stability of the FMCW signal are effectively improved.

In one embodiment, the charge pump is operated at the first current or the second current by adjusting the power supply current of the charge pump or the size ratio between different MOS tubes in the charge pump.

In one embodiment, the charge pump comprises a parallel bias power supply and an additional power supply, and the method for enabling the charge pump to work at a first current or a second current by adjusting the power supply current of the charge pump comprises the following steps: receiving a first control signal, controlling the conduction of an additional power supply according to the first control signal, and providing additional bias current for the charge pump when the additional power supply is conducted so as to regulate the working current of the charge pump to a first current; and receiving a second control signal, and controlling the additional power supply to be switched off according to the second control signal, wherein the additional power supply stops providing the additional bias current for the charge pump so as to regulate the working current of the charge pump to a second current.

In one embodiment, the first current + K × additional bias current; wherein K is the gain factor of the charge pump.

In one embodiment, the method for reducing loop settling time of the phase-locked loop further comprises: setting the frequency dividing ratio of a frequency divider in a phase-locked loop to adjust the ratio of an effective signal stage and an ineffective signal stage in the period of the frequency-modulated continuous wave signal; and generating a first control signal and a second control signal according to the frequency dividing ratio.

One embodiment of the present application provides a phase-locked loop for outputting a frequency modulated continuous wave signal, a cycle of the frequency modulated continuous wave signal including an active signal phase and an inactive signal phase, the phase-locked loop including a charge pump; the charge pump is used for adopting a first current as a working current in an invalid signal stage and adopting a second current as the working current in an effective signal stage aiming at any period of a frequency-modulated continuous wave signal; the first current is greater than the second current.

The phase-locked loop can be used for implementing the method for reducing the loop settling time of the phase-locked loop in some embodiments, and the technical effect which can be achieved by the phase-locked loop is the same as the beneficial technical effect which can be achieved by the method for reducing the loop settling time of the phase-locked loop, and is not described herein again.

In one embodiment, the charge pump comprises a parallel bias power supply and an additional power supply, and the additional power supply provides additional bias current for the charge pump when being conducted; in the effective signal stage, the parallel bias power supply is switched on, the additional power supply is switched off, and the working current of the charge pump is a second current; in the invalid signal stage, the parallel bias power supply and the additional power supply are both conducted, and the working current of the charge pump is the first current.

In one embodiment, the phase-locked loop further comprises a frequency divider, and the phase-locked loop determines the ratio of the valid signal phase and the invalid signal phase in the period of the frequency-modulated continuous wave signal according to the frequency dividing ratio of the frequency divider.

The embodiment of the application provides a phase-locked loop regulating system, which comprises a frequency sweeping control module and a phase-locked loop in any one of the embodiments, wherein the frequency sweeping control module is connected with the phase-locked loop and is used for setting a frequency dividing ratio of the phase-locked loop and generating a charge pump control signal according to the frequency dividing ratio; the charge pump is controlled to adopt the first current as the working current in the invalid signal stage and adopt the second current as the working current in the valid signal stage.

In one embodiment, the phase-locked loop regulation system further comprises a processor connected between the sweep control module and the phase-locked loop, for receiving the charge pump control signal and forwarding the charge pump control signal to the phase-locked loop.

The embodiment of the application provides an integrated circuit, which comprises a radio frequency module, an analog signal processing module, a digital signal processing module and a data processing module which are connected in sequence; the radio frequency module comprises a phase-locked loop in any one of the embodiments or a phase-locked loop adjusting system in the embodiments, and is used for generating a frequency-modulated continuous wave signal as a radio frequency transmitting signal; the radio frequency module is also used for receiving a radio frequency receiving signal; the analog signal processing module is used for carrying out frequency reduction processing on the radio frequency receiving signal to obtain an intermediate frequency signal; the digital signal module is used for carrying out analog-to-digital conversion on the intermediate frequency signal to obtain a digital signal; and the data processing circuit is used for processing the digital signals to realize target detection and/or wireless communication.

In one embodiment, the integrated circuit is a millimeter wave chip.

In one embodiment, the radio frequency receiving signal is an echo signal formed by the transmission and/or scattering of the radio frequency transmitting signal by the target, and the millimeter wave chip is a sensor chip or a radar chip.

A radio device, comprising: a carrier, an antenna, and the integrated circuit of any of the preceding embodiments, wherein the integrated circuit is disposed on the carrier; the antenna is arranged on the carrier or is arranged on the carrier together with the integrated circuit; the integrated circuit is connected with the antenna and used for transmitting and receiving radio signals.

An apparatus, comprising: an apparatus body and the radio device in the foregoing embodiments, the radio device being provided on the apparatus body; wherein the radio device is used for object detection and/or communication to provide reference information for the operation of the apparatus body.

Drawings

FIG. 1 is a waveform diagram of an embodiment of a frequency modulated continuous wave signal.

Fig. 2 is a waveform diagram of a frequency modulated continuous wave signal in another embodiment.

FIG. 3 is a block diagram of an exemplary phase-locked loop.

Fig. 4 is a block diagram of a phase-locked loop according to another embodiment.

Fig. 5 is a schematic circuit diagram of a charge pump according to an embodiment.

Fig. 6 is a schematic circuit diagram of a charge pump according to another embodiment.

Fig. 7 is a schematic circuit diagram of a charge pump according to yet another embodiment.

Fig. 8 is a block diagram of a phase-locked loop according to still another embodiment.

FIG. 9 is a block flow diagram of a method for reducing PLL loop settling time in one embodiment.

FIG. 10 is a block diagram of a method for adjusting the operating current of a charge pump according to an embodiment.

Fig. 11 is a flow chart of a method for reducing loop settling time of a phase-locked loop in another embodiment.

FIG. 12 is a block diagram of an exemplary PLL conditioning system.

Fig. 13 is a block diagram of a pll adjusting system according to another embodiment.

The reference numbers illustrate: 10. a phase-locked loop; 11. a charge pump; 111. a bias power supply is connected in parallel; 112. an additional power supply; 113. a switch unit; 12. a frequency divider; 20. a sweep frequency control module; 30. a processor.

Detailed Description

To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

Where the terms "comprising," "having," and "including" are used herein, another element may be added unless an explicit limitation is used, such as "only," "consisting of … …," etc. Unless mentioned to the contrary, terms in the singular may include the plural and are not to be construed as being one in number.

Frequency modulated continuous wave radar relies on a frequency tunable FMCW signal provided by an FMCW PLL for ranging. In the FMCW signal provided by the FMCW PLL, only a portion of the signal is typically valid for ranging, and the phase in which this portion of the signal is present is referred to as the valid signal phase. The stage corresponding to the signal other than the valid signal in the FMCW signal is the invalid signal stage.

For example, fig. 1 shows an FMCW signal with a valid rising edge, where the abscissa is time t and the ordinate is frequency f. From time t1 to time t2, the frequency of the FMCW signal rises with time. From time t2 to time t3, the frequency of the FMCW signal decreases with time. From time t3 to time t4, the frequency of the FMCW signal remains stable. Since the rising edge of the FMCW signal is active, the period from time t1 to time t2 is the active signal phase of the FMCW signal, and the period from time t2 to time t4 is the inactive signal phase of the FMCW signal.

For example, fig. 2 shows an FMCW signal with a falling edge active, where the abscissa is time t and the ordinate is frequency f. From time t1 to time t2, the frequency of the FMCW signal rises with time. From time t2 to time t3, the frequency of the FMCW signal remains stable. From time t3 to time t4, the frequency of the FMCW signal decreases with time. Since the falling edge of the FMCW signal is active, the period from time t3 to time t4 is the active signal phase of the FMCW signal, and the period from time t1 to time t3 is the inactive signal phase of the FMCW signal.

Illustratively, the FMCW signal in fig. 1 and 2 may be generated by the phase locked loop shown in fig. 3. As an example, the Phase-locked loop may include a Phase and Frequency Detector (PFD), a Charge Pump (CP), a Low Pass Filter (LPF), a Voltage Controlled Oscillator (VCO), and a Divider (Divider). Wherein PFD and CP are responsible for the input signal f_refAnd a feedback signal f_divConverts the phase difference into a current signal, and transmits the current signal to the LPF. The LPF converts the current signal into a voltage signal after the high-frequency signal is filtered, and transmits the voltage signal to the VCO. VCO outputs frequency modulated continuous wave signal f according to voltage signal_out. The Divider adjusts the frequency of the continuous wave signal f according to the frequency dividing ratio N_outFrequency division is performed to transmit a feedback signal f_divTo PFD. When the phase-locked loop is locked, f_outAnd f_refSatisfies the following relation: f. of_out＝f_ref×N。

Loop bandwidth of PLL and working current I of charge pump_cpPositive correlation, I_cpThe larger the loop bandwidth of the PLL, I_cpThe smaller the loop bandwidth of the PLL.

Based on this, the embodiment of the present application provides a phase-locked loop 10, as shown in fig. 4. The phase-locked loop 10 can output a frequency-modulated continuous wave signal, wherein the cycle of the frequency-modulated continuous wave signal comprises an effective signal stage and an ineffective signal stage, and the phase-locked loop 10 comprises a charge pump 11; the charge pump 11 is configured to use a first current as a working current in an invalid signal stage and use a second current as a working current in an effective signal stage for any period of the frequency modulated continuous wave signal; the first current is greater than the second current.

Illustratively, the charge pump 11 included in the phase-locked loop 10 in fig. 4 has a circuit configuration as shown in fig. 5. Wherein, the charge pump 11 comprises a parallel bias power supply 111 and an additional power supply 112, and the additional power supply 112 provides an additional bias current Ibias1 to the charge pump 11 when being conducted; in the active signal phase, the parallel bias power supply 111 is turned on, the additional power supply 112 is turned off, and the working current of the charge pump 11 is the second current; in the inactive signal phase, the parallel bias power supply 111 and the additional power supply 112 are both turned on, and the operating current of the charge pump 11 is the first current. The parallel bias supply 111 is used to provide an initial bias current Ibias0 to the charge pump 11.

In fig. 5, the charge pump 11 further includes a switching unit 113, an operational amplifier OP, and a plurality of transistors. VDD is a power voltage, and VSS is a ground voltage; SW is a switch. DN is the down current control signal and UPN is the inverse of the up current control signal. The additional power supply 112 is connected to other components in the charge pump 11 via a switching unit 113.

In the active signal phase, the switch unit 113 is turned off, the parallel bias power supply 111 operates alone, the input current of the charge pump 11 is the initial bias current Ibias0, the operating current of the charge pump 11 is the second current, and the second current is K × Ibias 0. Where K is a gain coefficient of the charge pump 11, and the gain coefficient K is related to the structure of the charge pump 11 and can be determined according to a ratio of channel width to length ratios of the transistor M1 and the transistor M0 in the charge pump 11.

In the inactive signal phase, the switch unit 113 is closed, the parallel bias power supply 111 and the additional capacitor jointly supply current to the charge pump 11, the input current of the charge pump 11 is the sum of the initial bias current Ibias0 and the additional bias current Ibias1, the operating current of the charge pump 11 is the first current, and the first current is K0 × (Ibias0+ Ibias1) ═ the second current + K × Ibias 1.

Alternatively, as shown in fig. 6, an embodiment of the present application discloses another structure of the charge pump 11, in which a parallel bias power supply 111 provides an initial bias current Ibias0 for the charge pump 11, and transistors M9 and M10 are connected in parallel at two ends of M1, and transistors M11 and M12 are connected in parallel at two ends of M2, where M9 is controlled by a switch SW1, and M11 is controlled by a switch SW 2.

In the active signal phase, M9 and M11 are controlled to be turned off through SW1 and SW2, the gain coefficient K of the charge pump 11 is unchanged, the input current of the charge pump 11 is the initial bias current Ibias0, the operating current of the charge pump 11 is the second current, and the second current is K × Ibias 0.

In the inactive signal phase, the M9 and M11 are controlled to be conducted through the SW1 and the SW2, which is equivalent to connecting additional transistors in parallel to the M1 and the M2, and is equivalent to increasing the channel width-length ratio of the M1 and the M2. The ratio between the channel width-to-length ratio of M1 and the channel width-to-length ratio of M0 becomes large, the gain factor of the charge pump 11 becomes K1, and K1 is greater than K. The input current of the charge pump 11 is still the initial bias current Ibias0, and the operating current of the charge pump 11 is the first current, which is K1 × Ibias 0.

Optionally, the structure of the charge pump 11 may also include, as shown in fig. 7, a parallel bias power supply 111 and an additional power supply 112, where the additional power supply 112 is connected to other elements in the charge pump 11 through a switch unit 113, and the additional power supply 112 provides an additional bias current Ibias1 to the charge pump 11 when the switch unit 113 is turned on; the parallel bias power supply 111 provides an initial bias current Ibias0 to the charge pump 11; the two ends of M1 are connected in parallel with transistors M9 and M10, and the two ends of M2 are connected in parallel with transistors M11 and M12, wherein M9 is controlled by switch SW1, and M11 is controlled by switch SW 2.

In the active signal phase, the switch unit 113 is turned off, and M9 and M11 are controlled to be turned off by SW1 and SW2, the parallel bias power supply 111 operates alone, the input current of the charge pump 11 is the initial bias current Ibias0, the operating current of the charge pump 11 is the second current, and the second current is K × Ibias 0.

In the invalid signal phase, the switch unit 113 is closed, the parallel bias power supply 111 and the additional capacitor jointly supply current to the charge pump 11, and the input current of the charge pump 11 is the sum of the initial bias current Ibias0 and the additional bias current Ibias 1; and, controlling M9 and M11 to be on through SW1 and SW2 is equivalent to increasing the channel width-to-length ratio of M1 and M2. The ratio between the channel width-length ratio of M1 and the channel width-length ratio of M0 becomes larger, the gain factor of the charge pump 11 becomes K1, the operating current of the charge pump 11 becomes the first current, and the first current is K1 × (Ibias0+ Ibias 1).

When the FMCW signal is in the invalid signal stage, the phase-locked loop 10 increases the working current of the charge pump 11, thereby increasing the loop bandwidth of the PLL, increasing the frequency response speed of the FMCW signal, and reducing the loop stabilization time; when the FMCW signal is in the effective signal stage, the working current of the charge pump 11 is reduced to reduce the loop bandwidth of the PLL, which is beneficial to filtering low-pass noise inside the PLL loop, reducing phase noise, and improving signal stability.

In one embodiment, as shown in fig. 8, the phase-locked loop 10 further includes a frequency divider 12, and the phase-locked loop 10 determines the ratio of the valid signal phase and the invalid signal phase in the period of the frequency-modulated continuous wave signal according to the frequency dividing ratio of the frequency divider 12.

One embodiment of the present application also discloses a method for reducing loop settling time of a phase-locked loop. Wherein the phase-locked loop may be the phase-locked loop 10 in any of the previous embodiments, the phase-locked loop 10 is configured to output a frequency-modulated continuous wave signal, a cycle of the frequency-modulated continuous wave signal includes an active signal phase and an inactive signal phase, and the phase-locked loop 10 includes the charge pump 11. As shown in fig. 9, the method for reducing the loop settling time of the phase-locked loop includes:

s10: aiming at any period of the frequency modulated continuous wave signal, in an invalid signal stage, the working current of the charge pump 11 is a first current; in the active signal phase, the working current of the charge pump 11 is a second current; wherein the first current is greater than the second current.

The method for reducing the loop stability time of the phase-locked loop can be used for modulating an FMCW signal, for example, when a frequency modulated continuous wave signal is in an invalid signal stage, the working current of the charge pump 11 is set to be a first current which is larger, so that the loop bandwidth of the PLL is increased, the loop stability time is reduced, the frequency modulated continuous wave signal can be quickly stabilized, the phase-locked loop 10 is quickly stabilized, and the next signal period is entered as soon as possible; when the frequency modulated continuous wave signal is in the effective signal stage, the working current of the charge pump 11 is set to be a smaller second current, so that the loop bandwidth of the PLL is reduced, the low-pass noise inside the loop is effectively reduced, and the frequency modulated continuous wave signal has better signal stability.

In some embodiments, the charge pump 11 can be operated at the first current or the second current by adjusting the power supply current of the charge pump 11 or the size ratio between different MOS transistors in the charge pump 11.

For example, the charge pump 11 may be operated at a first current or a second current by adjusting a power supply current of the charge pump 11, wherein the structure of the charge pump 11 may refer to fig. 2. The method for adjusting the operating current of the charge pump 11 is shown in fig. 10 and includes:

s11: receiving a first control signal, controlling the additional power supply 112 to be switched on according to the first control signal, and providing an additional bias current to the charge pump 11 when the additional power supply 112 is switched on so as to regulate the working current of the charge pump 11 to a first current;

s12: receiving the second control signal, controlling the additional power supply 112 to be turned off according to the second control signal, and stopping the additional power supply 112 from providing the additional bias current to the charge pump 11 so as to regulate the working current of the charge pump 11 to the second current.

Specifically, in the inactive signal phase, the phase-locked loop 10 receives the first control signal, and the first control signal controls the switch unit 113 to be closed, so that the additional power supply 112 is turned on. At this time, the additional power supply 112 provides an additional bias current Ibias1 to the charge pump 11, the parallel bias power supply 111 provides an initial bias current Ibias0 to the charge pump 11, and the operating current of the charge pump 11 is a first current, which is K × (Ibias0+ Ibias 0).

In the active signal phase, the phase locked loop 10 receives a second control signal, which controls the switching unit 113 to be turned off, so that the additional power supply 112 is turned off. At this time, the parallel bias power supply 111 provides the initial bias current Ibias0 to the charge pump 11, and the operating current of the charge pump 11 is the second current, which is K × Ibias 0.

For example, the charge pump 11 can also be operated at the first current or the second current by adjusting the size ratio between different MOS transistors in the charge pump 11, wherein the structure of the charge pump 11 can refer to fig. 6. For a specific adjustment method, reference may be made to the embodiment related to fig. 6, which is not described herein again.

In one embodiment, as shown in fig. 11, the method for reducing the loop settling time of the phase-locked loop further comprises:

s20: setting the frequency dividing ratio of a frequency divider 12 in the phase-locked loop 10 to adjust the ratio of the effective signal stage and the ineffective signal stage in the period of the frequency-modulated continuous wave signal;

s30: and generating a first control signal and a second control signal according to the frequency dividing ratio.

The division ratio of the divider 12 may be set by an external control module. After determining the frequency division ratio, it is possible to determine when the frequency modulated continuous wave signal is in an active signal phase and in an inactive signal phase according to the frequency division ratio, and accordingly generate the charge pump control signal to control the charge pump 11 to adopt the first current as the operating current in the inactive signal phase and the second current as the operating current in the active signal phase.

According to the method for reducing the loop stability time of the phase-locked loop, when the frequency-modulated continuous wave signal is in an invalid signal stage, the working current of the charge pump 11 is set to be a first larger current, so that the loop bandwidth of the PLL is increased, the loop stability time is reduced, and the frequency-modulated continuous wave signal can be rapidly stabilized; when the frequency modulation continuous wave signal is in an effective signal stage, the working current of the charge pump 11 is set to be a smaller second current, so that the loop bandwidth of the PLL is reduced, low-pass noise inside the loop is effectively filtered, and the frequency modulation continuous wave signal has better signal stability. Based on the relationship between the working current of the charge pump 11 and the loop bandwidth of the phase-locked loop 10, the loop bandwidth of the phase-locked loop 10 is adjusted by changing the working current of the charge pump 11 to modulate the FMCW signal, so that the frequency response speed and the signal stability of the FMCW signal are effectively improved.

As shown in fig. 12, an embodiment of the present application further discloses a phase-locked loop adjustment system, which includes a frequency sweep control module 20 and the phase-locked loop 10 in any of the foregoing embodiments; the frequency sweeping control module 20 is connected to the phase-locked loop 10, and is configured to set a frequency dividing ratio of the phase-locked loop 10, and generate a charge pump control signal according to the frequency dividing ratio, so as to control the charge pump 11 to use a first current as a working current in an invalid signal stage, and to use a second current as a working current in an valid signal stage.

For example, the sweep frequency control module 20 may adjust the ratio of the valid signal phase and the invalid signal phase within the period of the frequency modulated continuous wave signal by setting the frequency division ratio of the phase locked loop 10, thereby knowing when the valid signal phase is and when the invalid signal structure is. Accordingly, the sweep control module 20 may generate the charge pump control signal to control the charge pump 11 to use the first current as the working current during the inactive signal period and the second current as the working current during the active signal period.

Illustratively, the charge pump control signal includes a first control signal and a second control signal, wherein the first control signal is used for closing the switch unit 113 in the inactive signal phase to turn on the additional power supply 112, and increase the operating current of the charge pump 11 to the first current. The second control signal is used to turn off the switch unit 113 in the active signal phase to turn off the additional power supply 112, and to reduce the operating current of the charge pump 11 to the second current.

In one embodiment, as shown in fig. 13, the phase-locked loop adjustment system further comprises a processor 30 connected between the sweep control module 20 and the phase-locked loop 10 for receiving the charge pump control signal and forwarding the charge pump control signal to the phase-locked loop 10.

Illustratively, the processor 30 may be a CPU, microprocessor, or single-chip microcomputer. Optionally, the sweep control module 20 may also be connected to the phase-locked loop 10 via a Serial Peripheral Interface (SPI) to send the charge pump control signal to the phase-locked loop 10.

In the phase-locked loop adjusting system in the above embodiment, by setting the frequency dividing ratio of the phase-locked loop 10 to adjust the duty ratio of the valid signal stage and the invalid signal stage in the period of the FMCW signal, and generating the charge pump control signal according to the frequency dividing ratio, when the FMCW signal is in the invalid signal stage, the first control signal may be sent to increase the operating current of the charge pump 11 in the phase-locked loop 10 to the first current, so as to increase the loop bandwidth of the PLL, improve the frequency response speed of the FMCW signal, and reduce the time for stabilizing the loop; when the FMCW signal is in an effective signal stage, a second control signal is sent out, the working current of the charge pump 11 is reduced to a second current, the bandwidth of a PLL loop is reduced, low-pass noise inside the loop is filtered, phase noise is reduced, and signal stability is improved.

One embodiment of the present application provides an integrated circuit, including a radio frequency module, an analog signal processing module, a digital signal processing module, and a data processing module, which are connected in sequence; the radio frequency module comprises the phase-locked loop 10 in any one of the embodiments or the phase-locked loop adjusting system in any one of the embodiments, and is configured to generate a frequency-modulated continuous wave signal as a radio frequency transmission signal; the radio frequency module is also used for receiving a radio frequency receiving signal; the analog signal processing module is used for carrying out frequency reduction processing on the radio frequency receiving signal to obtain an intermediate frequency signal; the digital signal module is used for carrying out analog-to-digital conversion on the intermediate frequency signal to obtain a digital signal; and the data processing circuit is used for processing the digital signals to realize target detection and/or wireless communication.

Optionally, in an embodiment, the integrated circuit may be a millimeter wave chip, such as a millimeter wave radar chip or a millimeter wave sensor chip. The radio frequency receiving signal is an echo signal formed by the transmission and/or scattering of the radio frequency transmitting signal by a target. The kind of digital function module in the integrated circuit can be determined according to actual requirements. For example, in the millimeter wave radar chip, the data processing module may be used for obtaining information such as range dimension doppler transform, velocity dimension doppler transform, constant false alarm detection, azimuth detection, etc. for obtaining information such as range, angle, velocity, shape, size, surface roughness, and dielectric property of the target.

Optionally, the integrated circuit is an AiP (Antenna-In-Package) Chip structure, a AoP (Antenna-On-Package) Chip structure, or an AoC (Antenna-On-Chip) Chip structure.

A sensing system includes one or more sensing chips, which may be integrated circuits in any of the above embodiments, and the sensing chips may have the same structure and function as each other, or may be combined with each other to form a cascade structure.

In one embodiment, the present application also provides a radio device comprising: a carrier; the sensing system according to the above embodiment, or the integrated circuit according to any of the above embodiments, wherein the sensing die included in the sensing system is disposed on the carrier; an antenna disposed on the carrier or disposed on the carrier as a device integrated with the sensor die or the integrated circuit (i.e., the antenna may be AiP or an antenna disposed in an AoC structure); the sensing chip or the integrated circuit is connected with the antenna through the first transmission line (namely, the sensing chip or the integrated circuit is not integrated with the antenna at the moment, and can be SoC and the like) and is used for receiving and transmitting radio signals. The carrier can be a Printed Circuit Board (PCB), and the first transmission line can be a PCB wiring line.

In one embodiment, the present application further provides an apparatus comprising: an apparatus body; and a radio device as in the above embodiment provided on the apparatus body; wherein the radio device is used for object detection and/or communication to provide reference information for the operation of the apparatus body.

Specifically, on the basis of the above-described embodiments, in one embodiment of the present application, the radio device may be provided outside the apparatus body, in another embodiment of the present application, the radio device may be provided inside the apparatus body, and in other embodiments of the present application, the radio device may be provided partly inside the apparatus body and partly outside the apparatus body. The embodiments of the present application do not limit this, and are determined as the case may be.

In an alternative embodiment, the device body may be a component and a product applied to fields such as smart cities, smart homes, transportation, smart homes, consumer electronics, security monitoring, industrial automation, in-cabin detection (e.g., smart cabins), health care, and the like. For example, the device body may be an intelligent transportation device (such as an automobile, a bicycle, a motorcycle, a ship, a subway, a train, etc.), a security device (such as a camera), a liquid level/flow rate detection device, an intelligent wearable device (such as a bracelet, glasses, etc.), an intelligent household device (such as a sweeping robot, a door lock, a television, an air conditioner, an intelligent lamp, etc.), various communication devices (such as a mobile phone, a tablet computer, etc.), etc., and a barrier gate, an intelligent traffic indicator lamp, an intelligent indicator board, a traffic camera, various industrial mechanical arms (or robots), etc., and may also be various instruments for detecting vital sign parameters and various devices carrying the instruments, such as vital sign detection in an automobile cabin, indoor personnel monitoring, intelligent medical devices, consumer electronic devices, etc.

It should be understood that, although the steps in the flowcharts of fig. 10 and 11 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 10 and 11 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily sequential, but may be performed alternately or alternately with other steps or at least some of the other steps or stages.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A method for reducing loop stability time of a phase-locked loop is characterized in that the phase-locked loop is used for outputting a frequency-modulated continuous wave signal, the period of the frequency-modulated continuous wave signal comprises an effective signal stage and an ineffective signal stage, and the phase-locked loop comprises a charge pump;

the method comprises the following steps:

aiming at any period of the frequency-modulated continuous wave signal, in the invalid signal stage, the working current of the charge pump is a first current; in the effective signal stage, the working current of the charge pump is a second current;

wherein the first current is greater than the second current.

2. The method of claim 1, wherein the charge pump is operated at the first current or the second current by adjusting a power supply current of the charge pump or a size ratio between different MOS transistors in the charge pump.

3. The method of reducing phase-locked loop settling time of claim 2, wherein the charge pump comprises a parallel bias supply and an additional supply, and wherein adjusting a supply current of the charge pump to operate the charge pump at the first current or the second current comprises:

receiving a first control signal, controlling the additional power supply to be conducted according to the first control signal, and providing additional bias current for the charge pump when the additional power supply is conducted so as to regulate the working current of the charge pump to the first current;

and receiving a second control signal, and controlling the additional power supply to be switched off according to the second control signal, wherein the additional power supply stops providing additional bias current for the charge pump so as to regulate the working current of the charge pump to the second current.

4. The method of reducing phase-locked loop settling time of claim 3,

the first current + K × the additional bias current;

and K is the gain coefficient of the charge pump.

5. A method for reducing PLL loop settling time according to claim 3 or 4 and further comprising:

setting a frequency dividing ratio of a frequency divider in the phase-locked loop to adjust the ratio of the effective signal stage and the ineffective signal stage in the period of the frequency-modulated continuous wave signal;

and generating the first control signal and the second control signal according to the frequency dividing ratio.

6. A phase locked loop for outputting a frequency modulated continuous wave signal having a period comprising an active signal phase and an inactive signal phase, the phase locked loop comprising a charge pump;

the charge pump is used for adopting a first current as a working current in the invalid signal stage and adopting a second current as the working current in the valid signal stage aiming at any period of the frequency-modulated continuous wave signal; the first current is greater than the second current.

7. The phase locked loop of claim 6 wherein the charge pump comprises a parallel bias supply and an additional supply, the additional supply providing an additional bias current to the charge pump when turned on;

in the effective signal stage, the parallel bias power supply is switched on, the additional power supply is switched off, and the working current of the charge pump is the second current;

in the inactive signal phase, the parallel bias power supply and the additional power supply are both turned on, and the working current of the charge pump is the first current.

8. The phase locked loop of claim 7,

the first current + K × the additional bias current;

and K is the gain coefficient of the charge pump.

9. Phase locked loop according to claim 7 or 8, characterized in that it further comprises a frequency divider, and that it determines the ratio of the active signal phase and the inactive signal phase within the period of the frequency modulated continuous wave signal in dependence on the division ratio of the frequency divider.

10. A phase-locked loop adjustment system, comprising:

a phase locked loop as claimed in any one of claims 6 to 9;

the frequency sweeping control module is connected with the phase-locked loop and used for setting the frequency dividing ratio of the phase-locked loop and generating a control signal of the charge pump according to the frequency dividing ratio; and controlling the charge pump to adopt a first current as a working current in the invalid signal stage and adopt a second current as the working current in the valid signal stage.

11. The phase-locked loop regulation system of claim 10 further comprising a processor coupled between the sweep control module and the phase-locked loop to receive the charge pump control signal and forward the charge pump control signal to the phase-locked loop.

12. An integrated circuit is characterized by comprising a radio frequency module, an analog signal processing module, a digital signal processing module and a data processing module which are connected in sequence;

the radio frequency module comprising a phase locked loop according to any one of claims 6 to 9 or a phase locked loop tuning system according to any one of claims 10 to 11 for generating the frequency modulated continuous wave signal as a radio frequency transmit signal; the radio frequency module is also used for receiving a radio frequency receiving signal;

the analog signal processing module is used for carrying out frequency reduction processing on the radio frequency receiving signal to obtain an intermediate frequency signal;

the digital signal module is used for carrying out analog-to-digital conversion on the intermediate frequency signal to obtain a digital signal; and

the data processing circuit is used for processing the digital signals to realize target detection and/or wireless communication.

13. The integrated circuit of claim 12, wherein the integrated circuit is a millimeter wave chip.

14. The integrated circuit of claim 12 or 13, wherein the radio frequency receiving signal is an echo signal formed by the radio frequency transmitting signal being transmitted and/or scattered by a target, and the millimeter wave chip is a sensor chip or a radar chip.

15. A radio device, comprising:

a carrier;

the integrated circuit of any of claims 12-14, disposed on a carrier;

an antenna disposed on the carrier or disposed on the carrier as an integrated device with the integrated circuit;

the integrated circuit is connected with the antenna and used for transmitting and receiving radio signals.

16. An apparatus, comprising:

an apparatus body; and

the radio device of claim 15 disposed on the equipment body;

wherein the radio device is used for object detection and/or communication to provide reference information for the operation of the device body.