CN114584149A - Analog-to-digital converter - Google Patents

Abstract

The present invention provides an analog-to-digital converter comprising: the digital-to-analog conversion module comprises two stages of voltage division units, and the two stages of voltage division units are used for performing digital-to-analog conversion processing on the reference analog signal and outputting a target analog signal to a later stage; the sampling comparison module can process the received initial analog signal and the target analog signal into an intermediate digital signal; and the logic control module performs logic processing on the intermediate digital signal to obtain a first digital signal and a second digital signal. According to the digital-to-analog conversion module, accurate digital-to-analog conversion can be realized while high-precision analog-to-digital conversion is realized, the layout area of an integrated circuit is saved, and the adaptability of the analog-to-digital converter on the aspect that the integration level of the integrated circuit is higher and higher is improved.

Description

analog to digital converter

technical field

The present application relates to the technical field of digital-to-analog conversion/analog-to-digital conversion, and in particular, to an analog-to-digital converter.

Background technique

A traditional high-precision successive approximation (successive approximation, SAR) analog-to-digital converter (ADC) usually includes a digital-to-analog converter (DAC), a comparator and a logic control module. Most of the DACs in the ADC are in the form of capacitors to realize the function of converting digital signals into analog signals. This structure needs to occupy a large layout area. In addition, the analog voltage on the DAC in this analog-to-digital converter is very sensitive and does not have the driving ability itself. Even if it is replaced with a DAC in the form of a current steer, it is prone to the problem that the output swing of the DAC is limited. In addition, in the traditional comparator, the common mode input range of the dynamic comparator is limited, and the comparison speed of the analog comparator is slow.

SUMMARY OF THE INVENTION

The present application provides an analog-to-digital converter, which can solve the traditional analog-to-digital converter, which occupies a large layout area, the analog voltage of the DAC module is relatively sensitive, does not have the driving ability, and the output swing of the DAC is easily limited. at least one question.

On the one hand, an embodiment of the present application provides an analog-to-digital converter, including:

A digital-to-analog conversion module is used to receive an external first target control signal, a second target control signal and a reference analog signal; the reference analog signal is processed by the first target control signal and the second target control signal digital-to-analog conversion processing and output a target analog signal to the rear stage; wherein, the digital-to-analog conversion module includes a two-stage voltage dividing unit;

a sampling comparison module for receiving an external initial analog signal and a target analog signal output by the digital-to-analog conversion module, and outputting an intermediate digital signal to a subsequent stage; and,

The logic control module is used to receive the intermediate digital signal output by the sampling and comparison module and the external clock signal, enable signal and initial control signal, perform logical processing on the intermediate digital signal and output the first digital signal to the subsequent stage signal and the second digital signal, and logically process the initial control signal and output the first target control signal and the second target control signal to the digital-to-analog conversion module.

Optionally, in the analog-to-digital converter, the digital-to-analog conversion module includes: a first voltage dividing unit and a second voltage dividing unit connected to the first voltage dividing unit;

The first voltage dividing unit includes: a first switch subunit, a first impedance subunit and a second switch subunit which are connected in sequence;

The second voltage dividing unit includes: a second impedance subunit and a third switch subunit connected to the second impedance subunit;

One end of the first impedance subunit is connected to the external reference analog signal, and the other end of the first impedance subunit is grounded; the first switch subunit and the the second switch subunit, which performs voltage division processing on the reference analog signal to obtain a first intermediate voltage and a second intermediate voltage;

One end of the second impedance subunit is connected to the first intermediate voltage, and the other end of the second impedance subunit is connected to the second intermediate voltage; the third switch subunit is controlled by the second target control signal a unit that performs voltage division processing on the difference between the first intermediate voltage and the second intermediate voltage to obtain the target analog signal.

Optionally, in the analog-to-digital converter, the first impedance subunit includes: ^2M resistors connected in series;

The second impedance subunit includes: 2 ^N resistors connected in series in sequence; wherein M and N are both integers greater than or equal to 1, and M+N is an integer greater than or equal to 10.

Optionally, in the analog-to-digital converter, the first switch subunit includes: ^2M first control switches, and each of the first control switches is respectively connected to two of the first impedance subunits in sequence. a series node between adjacent said resistors;

The second switch subunit includes: ^2M second control switches, each of which is sequentially connected to a series node between two adjacent resistors of the first impedance subunit;

Wherein, one of the series nodes is staggered between the first control switch and the second control switch.

Optionally, in the analog-to-digital converter, the third switch subunit includes: 2 ^N third control switches, each of which is connected to two of the second impedance subunits in sequence. A series node between adjacent said resistors.

Optionally, in the analog-to-digital converter, the sampling and comparison module includes: a first selection switch, a second selection switch, a third selection switch, a capacitor, and a comparison unit, wherein the first selection switch and the The inverting input terminal of the comparison unit is connected, the positive pole of the capacitor is connected to the connection node between the first selection switch and the inverting input terminal of the comparison unit, the negative pole of the capacitor is grounded, and the second selection switch is connected to the ground. The switch and the third selection switch are both connected to the non-inverting input terminal of the comparison unit;

Wherein, through the third selection switch, the output end of the digital-to-analog conversion module is connected to the non-inverting input end of the comparison unit.

Optionally, in the analog-to-digital converter, when the analog-to-digital converter is working, the first selection switch and the second selection switch are closed at the same time, so that the same-direction input end of the comparison unit and the The inverting input terminal receives the target analog signal.

Optionally, in the analog-to-digital converter, a switch working state of the third selection switch is opposite to that of the first selection switch and the second selection switch.

Optionally, in the analog-to-digital converter, the comparison unit includes: a current adder, a pre-amplifier, and a dynamic latch that are connected in sequence.

Optionally, in the analog-to-digital converter, the analog-to-digital converter further includes: a buffer module configured to perform buffer adjustment on the target analog signal.

The technical solution of the present application includes at least the following advantages:

(1) By setting a digital-to-analog conversion module in the present application, it can realize accurate digital-to-analog conversion while realizing high-precision analog-to-digital conversion, which saves the layout area of the integrated circuit and improves the integration of the analog-to-digital converter in the integrated circuit. The degree of adaptability in this regard is getting higher and higher.

(2) Further, the digital-to-analog conversion module includes a two-stage voltage dividing unit, and a higher precision can be obtained through the cooperation of ^2M resistors in the first stage and ^2N resistors in the second stage target analog signal.

(3) In addition, the digital-to-analog conversion module provided by the present application can output a stable target analog signal (analog voltage signal) to the subsequent stage through a two-stage voltage division process, the digital-to-analog conversion module has driving capability and the digital-to-analog conversion module The output swing is larger.

Description of drawings

In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the accompanying drawings that need to be used in the description of the specific embodiments or the prior art will be briefly introduced below. The drawings are some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without any creative effort.

1 is a schematic diagram of a circuit structure of an analog-to-digital converter according to an embodiment of the present invention;

2 is a schematic diagram of a circuit structure of a digital-to-analog conversion module according to an embodiment of the present invention;

3 is a schematic diagram of a circuit structure of a comparison unit according to an embodiment of the present invention;

Among them, the reference numerals are described as follows:

10-digital-to-analog conversion module, 11-first voltage dividing unit, 111-first switching subunit, 112-first impedance subunit, 113-second switching subunit, 12-second voltage dividing unit, 121-th Two impedance subunits, 122-third switch subunit, 20-sampling comparison module, 21-comparison unit, 211-current adder, 212-pre-amplifier, 213-dynamic latch, 30-logic control module, 40-buffer module.

Detailed ways

The technical solutions in the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

In the description of this application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation or a specific orientation. construction and operation, and therefore should not be construed as limitations on this application. Furthermore, the terms "first", "second", and "third" are used for descriptive purposes only and should not be construed to indicate or imply relative importance.

In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection connection, or integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal connection of two components, which can be a wireless connection or a wired connection connect. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood in specific situations.

An embodiment of the present application provides an analog-to-digital converter. Please refer to FIG. 1. FIG. 1 is a schematic diagram of a circuit structure of an analog-to-digital converter according to an embodiment of the present invention. The analog-to-digital converter includes: a digital-to-analog conversion module 10, a sampling The comparison module 20 and the logic control module 30 .

Wherein, the digital-to-analog conversion module 10 is configured to receive the external first target control signal CTL1<M:0>, the second target control signal CTL2<N:0> and the reference analog signal VREF; Signal CTL1<M:0> and the second target control signal CTL2<N:0>, perform digital-to-analog conversion processing on the reference analog signal VREF and output a target analog signal DAC_OUT to the subsequent stage; The analog conversion module 10 includes a two-stage voltage dividing unit. Specifically, please refer to FIG. 2 . FIG. 2 is a schematic diagram of a circuit structure of a digital-to-analog conversion module according to an embodiment of the present invention. The digital-to-analog conversion module 10 includes: a first voltage dividing unit 11 and a first voltage dividing unit 11 . The connected second voltage dividing unit 12 .

Wherein, the first voltage dividing unit 11 includes: a first switch subunit 111, a first impedance subunit 112 and a second switch subunit 113 connected in sequence; the second voltage dividing unit 12 includes: a second impedance subunit 113 unit 121 and a third switch subunit 122 connected to the second impedance subunit 121 .

In this embodiment, one end of the first impedance subunit 112 is connected to the external reference analog signal VREF, and the other end of the first impedance subunit 112 is grounded; through the first target control signal CTL1<M :0> Control the first switch subunit 111 and the second switch subunit 113, and perform voltage division processing on the reference analog signal VREF to obtain a first intermediate voltage VOT and a second intermediate voltage VOB. In addition, one end and the other end of the first impedance subunit 112 can be respectively connected to two voltage signals, one positive and one negative of the reference analog signal VREF, and it is only necessary to ensure that one end and the other end of the first impedance subunit 112 There is a voltage difference between them, and the present invention does not limit the specific value of the voltage signal connected to one end and the other end of the first impedance subunit 112 .

Further, one end of the second impedance subunit 121 is connected to the first intermediate voltage VOT, and the other end of the second impedance subunit 122 is connected to the second intermediate voltage VOB; through the second target control signal CTL2<N:0> controls the third switch subunit 122 to perform voltage division processing on the difference between the first intermediate voltage VOT and the second intermediate voltage VOB to obtain the target analog signal DAC_OUT.

Preferably, the first impedance subunit 112 includes: ^2M resistors R1 connected in series; the second impedance subunit 121 includes: ^2N resistors R2 connected in series; wherein M and N can be Both are integers greater than or equal to 1, and M+N may be an integer greater than or equal to 10.

Preferably, corresponding to the first impedance subunit 112, the first switch subunit includes: ^2M first control switches S1, and each of the first control switches S1 is respectively connected to the first impedance subunits in sequence A series node between two adjacent said resistors R1 of cell 112 . Similarly, corresponding to the first impedance subunit 112, the second switch subunit 122 includes: ^2M second control switches S2, each of which is connected to the first control switch S2 in sequence. A series node between two adjacent resistors R1 of the impedance subunit 112; wherein one series node is staggered between a group of the first control switches S1 and a group of the second control switches S2 .

In this embodiment, corresponding to the second impedance subunit 121, the third switch subunit 122 includes: 2 ^N third control switches S3, each of which is connected to the A series node between two adjacent resistors R2 of the second impedance subunit 122 .

Further, the sampling and comparison module 20 is configured to receive an external initial analog signal VIN and the target analog signal DAC_OUT output by the digital-to-analog conversion module 10, and output an intermediate digital signal CMP_OUT to a subsequent stage. Specifically, the sampling and comparison module 20 includes: a first selection switch SHSW1, a second selection switch SHSW2, a third selection switch SHSW2, a capacitor CAP and a comparison unit 21, wherein the first selection switch SHSW1 and the comparison unit 21 is connected to the inverting input terminal, the positive terminal of the capacitor CAP is connected to the connection node between the first selection switch SHSW1 and the inverting input terminal of the comparison unit 21, the negative terminal of the capacitor CAP is grounded, and the Both the two selection switches SHSW2 and the third selection switch SHSW3 are connected to the non-inverting input terminal of the comparison unit 21; wherein, through the third selection switch SHSW3, the output terminal of the digital-to-analog conversion module 10 is connected to the The non-inverting input terminal of the comparison unit 21 enables the target analog signal DAC_OUT to be input to the non-inverting input terminal of the comparison unit 21 . Further, the switching working state of the third selection switch SHSW3 is opposite to the switching working states of the first selection switch SHSW1 and the second selection switch SHSW2. Specifically, in this embodiment, it is necessary to ensure that the The switch control signals of the second selection switch SHSW2 and the third selection switch SHSW3 will not be enabled at the same time, that is, the second selection switch SHSW2 and the third selection switch SHSW3 will not be closed at the same time (the switching states of the two are opposite to each other) ) to prevent the initial analog signal VIN and the target analog signal DAC_OUT from being short-circuited. When the analog-to-digital converter is working, the first selection switch SHSW1 and the second selection switch SHSW2 are closed at the same time, so that the non-inverting input terminal and the inverting input terminal of the comparison unit 21 receive the initial analog signal VIN balances the input voltage of the comparison unit 21 .

Preferably, please refer to FIG. 3 . FIG. 3 is a schematic diagram of a circuit structure of a comparison unit according to an embodiment of the present invention. The comparison unit 21 includes a current adder 211 , a preamplifier 212 and a dynamic latch 213 which are connected in sequence. Specifically, the current adder 211 is composed of two current sources and a plurality of MOS transistors; the pre-amplifier 212 is a low-gain pre-amplifier, composed of a plurality of resistors and a plurality of MOS transistors; the dynamic latch 213 is composed of It is composed of multiple MOS tubes. The common-mode voltage range of the input signal of the comparison unit 21 is large (GND˜VDD), and the comparison speed is very fast.

Further, the logic control module 30 is configured to receive the intermediate digital signal CMP_OUT and the external clock signal ADC_CLK, the enable signals ADC_EN and CMP_EN, and the initial control signal DAC<L:0> output by the sampling and comparison module 20, Perform logical processing on the intermediate digital signal CMP_OUT and output the first digital signal ADC_OUT<L:0> and the second digital signal ADC_RDY to the subsequent stage, and perform logical processing on the initial control signal DAC<L:0> and send it to the subsequent stage. The digital-to-analog conversion module 10 outputs the first target control signal CTL1<M:0> and the second target control signal CTL2<N:0>.

In this embodiment, the digital-to-analog conversion module 10 adopts a two-stage voltage dividing unit structure, and the first voltage dividing unit 11 and the second voltage dividing unit 12 respectively use ^2M and ^2N resistors in series. The first voltage dividing unit 11 evenly divides VREF into 2 ^M parts. Assuming that the resistance value of the resistor R1 of the first impedance sub-unit 112 is r1, the formula for current consumption is:

According to the first target control signal CTL1<M:0>, one of the 2 ^M voltages (the first intermediate voltage VOT-the second intermediate voltage VOB) is selected, the first intermediate voltage VOT and the second intermediate voltage VOT The intermediate voltage VOB is respectively connected to two ends of the second impedance subunit 122 through the second switch subunit 122 . The second impedance sub-unit 122 then divides the voltage into 2 ^N output nodes and outputs them directly, and the output is the target analog signal DAC_OUT. The second voltage dividing unit 12 is connected to both ends of the first voltage dividing unit 11 in parallel, which will cause a relative error. The formula for this relative error is:

Among them, assuming that the relative error error is less than 0.05%, M and N are both 5, then the calculated r2 is twice of r1. When the first impedance subunit 112 outputs the last node, the resistance values of the last switch S1 of a column and the first switch S2 of a column that are turned on in the first voltage dividing unit 11 and the second voltage divider The resistance values of the first resistor R2 and the last resistor R2 in the unit 12 are combined into a unit resistance value r2; when the second impedance subunit 121 outputs the first node, the switch of the second intermediate voltage VOB is controlled to be turned off. open.

The analog-to-digital converter provided by the present invention uses the digital-to-analog conversion module 10 to realize the conversion of digital signals to analog signals. The first selection switch SHSW1 and the capacitor CAP sample and hold the initial analog signal VIN input by the strobe, so The second selection switch SHSW2 is used to balance the input voltage (initial analog signal VIN) of the comparison unit 21 . The comparison unit 21 compares the initial analog signal VIN with the target analog signal DAC_OUT output by the digital-to-analog conversion module 10 , and sends the comparison result (the intermediate digital signal CMP_OUT) to the logic control module 30 . The logic control module 30 uses SAR logic according to the comparison result (the intermediate digital signal CMP_OUT) to make the target analog signal DAC_OUT generated by the digital-to-analog conversion module 10 approach the initial analog signal VIN. After one analog-to-digital conversion is completed, the result of the analog-to-digital conversion is updated, that is, the first digital signal ADC_OUT<L:0> is updated, where L=M+N.

In this embodiment, the analog-to-digital converter further includes: a buffer module 40, the input terminal of the buffer module 40 is connected to the output terminal of the digital-to-analog conversion module 10, and is used for performing the processing on the target analog signal DAC_OUT. Buffer adjustment.

In the analog-to-digital converter provided in this embodiment, in the reset mode, the currents of all modules of the analog-to-digital converter are turned off, and the output result of the sampling and comparison module 20 and the quantization output of the logic control module 30 are quantified. The results are all pulled down.

In summary, the present invention provides an analog-to-digital converter, comprising: a digital-to-analog conversion module, a sampling comparison module and a logic control module, the digital-to-analog conversion module includes a two-stage voltage dividing unit, and the two-stage voltage dividing unit is used to The reference analog signal undergoes digital-to-analog conversion processing and outputs a target analog signal to the subsequent stage; the sampling and comparison module can process the received initial analog signal and the target analog signal into an intermediate digital signal; the logic control module The intermediate digital signal is logically processed to obtain a first digital signal and a second digital signal. By setting a digital-to-analog conversion module in the present application, accurate digital-to-analog conversion can be realized while high-precision analog-to-digital conversion is realized, which saves the layout area of the integrated circuit and improves the integration degree of the analog-to-digital converter in the integrated circuit. The higher the adaptability in this regard. Further, the digital-to-analog conversion module includes a two-stage voltage dividing unit, and a target analog with higher precision can be obtained through the cooperation of the ^2M resistors in the first stage and the ^2N resistors in the second stage. Signal. In addition, the digital-to-analog conversion module provided by the present application can output a stable target analog signal (analog voltage signal) to the subsequent stage through two-stage voltage division processing. larger.

Obviously, the above-mentioned embodiments are only examples for clear description, and are not intended to limit the implementation manner. For those of ordinary skill in the art, changes or modifications in other different forms can also be made on the basis of the above description. There is no need and cannot be exhaustive of all implementations here. And the obvious changes or changes derived from this are still within the scope of protection created by the present application.

Claims (10)

1. An analog-to-digital converter, comprising:

the digital-to-analog conversion module is used for receiving a first target control signal, a second target control signal and a reference analog signal from the outside; performing digital-to-analog conversion processing on the reference analog signal and outputting a target analog signal to a later stage through the first target control signal and the second target control signal; the digital-to-analog conversion module comprises two stages of voltage division units;

the sampling comparison module is used for receiving an external initial analog signal and a target analog signal output by the digital-to-analog conversion module and outputting an intermediate digital signal to a later stage; and (c) a second step of,

and the logic control module is used for receiving the intermediate digital signal output by the sampling comparison module, an external clock signal, an enable signal and an initial control signal, performing logic processing on the intermediate digital signal, outputting a first digital signal and a second digital signal to a rear stage, performing logic processing on the initial control signal, and outputting a first target control signal and a second target control signal to the digital-to-analog conversion module.

2. The analog-to-digital converter according to claim 1, wherein the digital-to-analog conversion module comprises: the device comprises a first partial pressure unit and a second partial pressure unit connected with the first partial pressure unit;

the first voltage division unit includes: the first switch subunit, the first impedance subunit and the second switch subunit are connected in sequence;

the second voltage division unit includes: a second impedance subunit and a third switching subunit connected with the second impedance subunit;

one end of the first impedance subunit is connected with the external reference analog signal, and the other end of the first impedance subunit is grounded; controlling the first switch subunit and the second switch subunit through the first target control signal, and performing voltage division processing on the reference analog signal to obtain a first intermediate voltage and a second intermediate voltage;

one end of the second impedance subunit is connected with the first intermediate voltage, and the other end of the second impedance subunit is connected with the second intermediate voltage; and controlling the third switch subunit through the second target control signal, and performing voltage division processing on the difference value of the first intermediate voltage and the second intermediate voltage to obtain the target analog signal.

3. The analog-to-digital converter according to claim 2, characterized in that the first impedance subunit comprises: serially connected 2 in turn^MA resistor;

the second impedance subunit includes: serially connected 2 in turn^NA resistor; wherein M and N are both integers greater than or equal to 1, and M + N is an integer greater than or equal to 10.

4. Analog-to-digital converter according to claim 3, characterized in thatCharacterized in that said first switch subunit comprises: 2^MEach first control switch is connected with a series node between two adjacent resistors of the first impedance subunit in sequence;

the second switch subunit includes: 2^MThe second control switches are respectively and sequentially connected with a series node between two adjacent resistors of the first impedance subunit;

wherein one of the series nodes is staggered between the first control switch and the second control switch.

5. The analog-to-digital converter according to claim 3, wherein the third switching subunit comprises: 2^NAnd each third control switch is sequentially connected with a series node between two adjacent resistors of the second impedance subunit.

6. The analog-to-digital converter according to claim 1, wherein the sampling comparison module comprises: the circuit comprises a first selection switch, a second selection switch, a third selection switch, a capacitor and a comparison unit, wherein the first selection switch is connected with the inverting input end of the comparison unit, the positive pole of the capacitor is connected with a connection node between the first selection switch and the inverting input end of the comparison unit, the negative pole of the capacitor is grounded, and the second selection switch and the third selection switch are both connected to the non-inverting input end of the comparison unit;

and the output end of the digital-to-analog conversion module is connected to the non-inverting input end of the comparison unit through the third selection switch.

7. The analog-to-digital converter according to claim 6, wherein when the analog-to-digital converter is in operation, the first selection switch and the second selection switch are simultaneously closed, so that the same-direction input terminal and the reverse-direction input terminal of the comparison unit receive the target analog signal.

8. The analog-to-digital converter according to claim 6, wherein the third selection switch has a switch operation state opposite to the switch operation states of the first selection switch and the second selection switch.

9. The analog-to-digital converter according to claim 6, characterized in that the comparison unit comprises: the current adder, the preamplifier and the dynamic latch are connected in sequence.

10. The analog-to-digital converter according to claim 1, characterized in that it further comprises: and the buffer module is used for carrying out buffer adjustment on the target analog signal.

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