CN114582267A - Control circuit and display device - Google Patents
Control circuit and display device Download PDFInfo
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- CN114582267A CN114582267A CN202210457455.0A CN202210457455A CN114582267A CN 114582267 A CN114582267 A CN 114582267A CN 202210457455 A CN202210457455 A CN 202210457455A CN 114582267 A CN114582267 A CN 114582267A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2074—Display of intermediate tones using sub-pixels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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- Engineering & Computer Science (AREA)
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The application provides a control circuit and a display device, which relate to the technical field of display, wherein the control circuit comprises at least one buffer operation circuit and a buffer delay circuit; the buffer delay circuit is respectively connected with at least one buffer operation circuit and is used for sequentially outputting at least two control voltages; the buffer operation circuit is used for correspondingly outputting at least two sequentially increased driving currents according to at least two control voltages. When the control circuit is applied to a display device, the output stepped driving force can enable the driving force on the driving chip to be gradually loaded into the load within a longer time, and enable the driving force of each load to reach a current preset value required by actual work, so that the problem of power failure of input voltage is effectively solved.
Description
Technical Field
The application belongs to the technical field of display, and particularly relates to a control circuit and a display device.
Background
The display panel of the display device is composed of pixels, the more the pixels are, the finer the displayed picture is, and more information can be displayed in the same display panel area, i.e. the higher the resolution is, the higher the load corresponding to the driving circuit of the display device is. For a common driving circuit at present, at the moment that a display device is powered on, a power supply voltage provides driving force for display of the display device through a driving chip and an output buffer, and the more loads in the driving circuit, the less easily the driving force can meet the requirement that each load in the driving circuit reaches a current preset value in a short time, so that part of the loads in a display panel reach an expected display effect, and the part of the loads do not reach the expected display effect, thereby generating the problem of power failure of input voltage.
If a voltage exceeding the voltage required for normal operation is provided to the display device in order to solve the problem of the power-down of the input voltage, a risk of display abnormality such as a display screen failure due to an excessive input voltage is generated, and therefore, a new circuit is urgently needed to avoid the problem.
Disclosure of Invention
The embodiment of the application provides a control circuit and a display device, which can effectively solve the problem of power failure of input voltage.
In order to achieve the above object, in a first aspect, an embodiment of the present application provides a control circuit, including: at least one buffer arithmetic circuit and a buffer delay circuit; the buffer delay circuit is respectively connected with at least one buffer arithmetic circuit,
the buffer delay circuit is used for sequentially outputting at least two control voltages; the buffer operation circuit is used for correspondingly outputting at least two sequentially increased driving currents according to at least two control voltages.
The embodiment of the application provides a control circuit, a buffer operation circuit of the control circuit correspondingly outputs at least two sequentially increased driving currents according to at least two control voltages sequentially output by a buffer delay circuit, namely, outputs a step driving force, when the control circuit is applied to a display device, the output step driving force can enable the driving force on a driving chip to be gradually loaded into a load in a longer time, and enable the driving force of each load to reach a current preset value required by actual work, so that the situation that the display device is powered on the moment, the situation that the driving force cannot simultaneously meet the current preset value of each load in a short time due to voltage mutation causes that part of the loads in a display panel reach an expected display effect, and part of the loads do not reach the expected display effect, thereby generating the problem that the input voltage is powered off.
In a possible implementation manner of the first aspect, the buffer operation circuit includes a power module, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, a sixth switch tube, and a seventh switch tube;
the first end of the first switch tube, the first end of the second switch tube and the third end of the second switch tube are connected; the second end of the first switch tube, the second end of the second switch tube and the power module are connected; the third end of the first switch tube, the second end of the third switch tube and the first end of the fourth switch tube are connected;
the first end of the third switching tube is connected with the external driving chip, the third end of the third switching tube is connected with the third end of the fourth switching tube, and the third end of the third switching tube is respectively connected with the second end of the fifth switching tube, the second end of the sixth switching tube and the second end of the seventh switching tube;
the first end of the fifth switch tube, the first end of the sixth switch tube and the first end of the seventh switch tube are respectively connected with the buffering delay circuit, and the third end of the fifth switch tube and the third end of the sixth switch tube are connected with the third end of the seventh switch tube and grounded.
In one possible implementation manner of the first aspect, the buffering delay circuit includes a voltage obtaining module, a first delay unit, and a second delay unit; the first end of fifth switch tube, the first end of sixth switch tube, the first end of seventh switch tube link to each other with buffering delay circuit respectively, include:
the first end of the fifth switching tube is connected with the voltage acquisition module, the first end of the sixth switching tube is connected with the first delay unit, and the first end of the seventh switching tube is connected with the second delay unit;
when the voltage acquisition module outputs the control voltage, the fifth switching tube is conducted, and the buffer operation circuit outputs a first driving current;
when the first delay unit and the voltage acquisition module respectively output control voltages, the fifth switching tube and the sixth switching tube are conducted, and the buffer operation circuit outputs a second driving current;
when the second delay unit, the first delay unit and the voltage acquisition module respectively output control voltages, the fifth switching tube, the sixth switching tube and the seventh switching tube are conducted, and the buffer operation circuit outputs a third driving current;
the first drive current, the second drive current and the third drive current are sequentially increased.
In a possible implementation manner of the first aspect, the first switching tube and the second switching tube are P-type MOS tubes, and the third switching tube, the fourth switching tube, the fifth switching tube, the sixth switching tube and the seventh switching tube are N-type MOS tubes; the first end is a grid, the second end is a drain, and the third end is a source.
In a possible implementation manner of the first aspect, the first delay unit includes a first resistor, a first zener diode, and a first capacitor, a first end of the first resistor is connected to the voltage obtaining module, a second end of the first resistor is connected to a first end of the first zener diode, one end of the first capacitor is connected to the first end of the first zener diode and the second end of the first resistor, and the other end of the first capacitor is grounded; and the second end of the first voltage stabilizing diode is connected with the first end of the sixth switching tube.
In a possible implementation manner of the first aspect, the second delay unit includes a second resistor, a second zener diode, and a second capacitor, a first end of the second resistor is connected to the voltage obtaining module, a second end of the second resistor is connected to a first end of the second zener diode, one end of the second capacitor is connected to the first end of the second zener diode and the second end of the second resistor, and the other end of the second capacitor is grounded; and the second end of the second voltage stabilizing diode is connected with the first end of the seventh switching tube.
In a second aspect, an embodiment of the present application provides a display device, which includes at least one pixel unit and a driving chip, and further includes the control circuit according to the first aspect;
at least one buffering operation circuit in the control circuit corresponds to at least one pixel unit one by one, and each buffering operation circuit is connected in series between the corresponding pixel unit and the driving chip.
Based on the possible implementation mode, compared with the prior art that a plurality of sub-pixel units in each row of pixel units are required to be connected with one output buffer, the number of the buffer operation circuits in the application is consistent with that of the pixel units in each row, so that the design capacity of the driving chip can be effectively reduced, the area of the chip is reduced, and the manufacturing cost is saved.
In one possible implementation of the second aspect, the pixel unit includes a plurality of sub-pixel units of different colors.
In a possible implementation manner of the second aspect, the display device further includes a switch circuit, and the switch circuit is configured to sequentially output a first control signal within a preset time of one row scanning period, where the first control signal is used to turn on one sub-pixel unit of the pixel units and turn off other sub-pixel units.
In a possible implementation manner of the second aspect, the first control signals corresponding to sub-pixel units of the same color in at least one pixel unit are the same.
It is to be understood that, the beneficial effects of the second aspect may refer to the relevant description in the first aspect, and are not described herein again.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic diagram illustrating an output buffer connected to a pixel unit in an AMOLED display panel according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a control circuit provided in an embodiment of the present application;
fig. 3 is a circuit diagram of a first delay unit Y1 of the buffering delay circuit according to the embodiment of the present application;
fig. 4 is a circuit diagram of a second delay unit Y2 of the buffering delay circuit according to the embodiment of the present application;
FIG. 5 is a waveform diagram of a voltage provided for a normal display of a pixel circuit according to an embodiment of the present application;
fig. 6 is a schematic diagram of a switching circuit sequentially outputting different control signals according to an embodiment of the present disclosure;
FIG. 7 is a schematic diagram of another control circuit provided by an embodiment of the present application;
fig. 8 is a schematic diagram of another switching circuit based on a control circuit according to an embodiment of the present application.
Description of reference numerals: 101. a first buffer operation circuit; 102. a buffer delay circuit; 103. a second buffer operation circuit; 20. a switching circuit.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, and circuits are omitted so as not to obscure the description of the present application with unnecessary detail.
The display panel of the conventional display device is composed of a plurality of pixel units, each pixel unit may be composed of a plurality of sub-pixel units (e.g., a red sub-pixel unit, a green sub-pixel unit, and a blue sub-pixel unit), the more the pixel units constituting the display panel, the finer the picture displayed by the display device, and the more information can be displayed in the same display panel area, i.e., the higher the resolution. The higher the resolution is, the more the number of driving channels of a circuit (referred to as a driving circuit for short) providing driving force in the display device is, and the larger the load connected to the driving circuit is when the display time of the display device is shortened, which needs to further improve the performance of the circuit and provide stronger driving force for the load.
For a common driving circuit at present, at the moment that a display device is powered on, a power supply voltage provides a driving force for display of the display device through a driving chip and an output buffer, and the more loads in the driving circuit, the more difficult the driving force can meet the requirement that each load in the driving circuit reaches a current preset value in a short time, so that part of the loads in a display panel reach an expected display effect, and part of the loads do not reach the expected display effect, thereby generating the problem of power failure of input voltage.
Taking a pixel unit in an Active Matrix/Organic Light Emitting Diode (AMOLED) display panel as an example, fig. 1 is a schematic diagram illustrating an output buffer connected to a pixel unit in an AMOLED display panel according to an embodiment of the present disclosure, and referring to fig. 1, one pixel unit in the AMOLED display panel comprises three sub-pixel units with different colors, namely a red sub-pixel unit (shown in the figure as red), a green sub-pixel unit (shown in the figure as green) and a blue sub-pixel unit (shown in the figure as blue), wherein each sub-pixel unit in one pixel unit is correspondingly connected with an output buffer respectively, after the output buffer receives the gray voltage selected by the gray voltage selector, the voltage is pushed to a pixel circuit of the AMOLED display panel, and a storage capacitor in the pixel circuit is charged. After the AMOLED display panel is powered on, it is necessary to provide sufficient driving force to complete charging of the storage capacitor in the pixel circuit in one scanning period, so as to achieve a preset display effect on the display screen.
However, if the number of pixel units in the display panel is more, that is, the number of storage capacitors to be charged in the pixel circuit is more, at the moment that the display panel is powered on, a problem easily occurs that the voltage actually reaching the storage capacitors in the pixel circuits is less than the voltage required by the corresponding pixel units for normal display, so that the pixel units cannot achieve the expected display effect, for example, in fig. 1, the voltage values S1 and S2 actually reaching the red sub-pixel units and the green sub-pixel units are equal to the voltage value required for normal display, the red sub-pixel units and the green sub-pixel units in the pixel units can normally display, and the voltage value S3 actually reaching the blue sub-pixel units is less than the voltage required for normal display, so that the blue sub-pixel units cannot achieve the expected display effect, and the problem of power down of the input voltage is generated.
If a voltage exceeding the voltage required for normal operation is provided to the display device in order to solve the problem of the power-down of the input voltage, a risk of display abnormality such as display screen failure due to an excessive input voltage is generated, and therefore, a new circuit is urgently needed to avoid the problem.
The embodiment of the application provides a control circuit for solving the problem of power failure of input voltage, wherein a buffer operation circuit in the control circuit correspondingly outputs at least two sequentially increased driving currents according to at least two control voltages sequentially output by a buffer delay circuit, namely outputs a step driving force.
A control circuit and a display device provided in the present application are described in detail with reference to the accompanying drawings. It should be noted that, since the control circuit and the display device are based on the same concept, the same or similar concept or process may not be repeated in some embodiments.
Example one
The embodiment of the application will be exemplified by the case that the AMOLED display panel includes one pixel unit of three sub-pixel units and the control circuit includes one output buffer operation circuit.
Referring to fig. 2, a schematic diagram of a control circuit according to an embodiment of the present disclosure is shown, where the control circuit includes a first buffer operation circuit 101 and a buffer delay circuit 102, and the buffer delay circuit 102 is configured to sequentially output at least two control voltages. The buffer delay circuit 102 is connected to the first buffer operation circuit 101, and the buffer operation circuit is configured to output at least two sequentially increasing driving currents according to the at least two control voltages.
It should be understood that when the control circuit is applied to an AMOLED display device, the outputted at least two sequentially increased driving currents can provide a stepped driving force for the driving chip S-IC in the AMOLED display device, and gradually reach a current value required by a load in normal operation, for example, a current value required by each pixel unit in the AMOLED display panel in fig. 2 in normal display.
The load in the AMOLED display device refers to a device that receives power in a circuit. Referring to fig. 2, the load may be one pixel unit including three sub-pixel units in the AMOLED display panel.
It should also be understood that the stepped driving force may be set according to the actual application requirements, and for example, the stepped driving force may be divided into three stages of driving force or four stages of driving force. The step driving force refers to at least two sequentially increased current values which are provided by the driving chip S-IC for the load and correspond to at least two control voltages. For example, assuming that the current value required by the load to operate normally is N, if the stepped driving force is divided into three stages of driving forces, the stepped driving force is the driving force corresponding to the three stages, for example, the driving force in the first stage is 50% N, the driving force in the second stage is 80% N, and the driving force in the third stage is 100% N.
Taking a pixel unit in the AMOLED display panel, the step driving force is divided into three stages, and the step driving force is 50% N to 80% N, and further 100% N, for example, as shown in fig. 2, the first buffer operation circuit 101 includes: power module VCC1, first switch tube Mp1A second switch tube Mp2And a third switch tube Mn1The fourth switch tube Mn2The fifth switch tube Mn5The sixth switching tube Mn6And a seventh switching tube Mn7(ii) a The power supply module VCC1 provides a reference current that acts as a dc bias.
First switch tube Mp1First terminal (grid), second switch tube Mp2First terminal (grid), second switch tube Mp2The third end (source electrode) is connected; first switch tube Mp1Second terminal (drain electrode), second switch tube Mp2The second end (drain) is connected with a power supply module VCC 1; first switch tube Mp1Third terminal (source electrode), third switch tube Mn1Second terminal (drain electrode), fourth switch tube Mn2The first terminals (gates) are connected.
Third switch tube Mn1A first terminal (grid) connected with an external driving chip S-IC, and a third switching tube Mn1The third end (source electrode) and the fourth switch tube Mn2The third end (source electrode) is connected with the fifth switch tube Mn5Second terminal (drain electrode), sixth switching tube Mn6Second terminal (drain electrode), seventh switch tube Mn7A second end (drain electrode) connected with a fourth switching tube Mn2First terminal (grid) and third switch tube Mn1The second terminal (drain) is connected.
The fifth switch tube Mn5First end (grid) and sixth switch tube Mn6First end (grid) and seventh switch tube Mn7A first terminal (grid) connected with the buffer delay circuit 102, and a fifth switch tube Mn5Third terminal (source electrode), sixth switch tube Mn6The third terminal (source) and the seventh switch tube Mn7The third terminal (source) is connected and grounded.
In the first buffer operation circuit 101 according to the embodiment of the present application, the first switch tube Mp1And a second switch tube Mp2Is a P-type MOS transistor, a third switching transistor Mn1And a fourth switch tube Mn2The fifth switch tube Mn5The sixth switching tube Mn6And a seventh switching tube Mn7Is an N-type MOS tube; the first end is a grid electrode, the second end is a drain electrode, and the third end is a source electrode.
It should be appreciated that the buffer delay circuit 102 includes a voltage acquisition module VbiasA first delay cell Y1 and a second delay cell Y2; the fifth switch tube Mn5First end (grid) and sixth switching tube Mn6First end (Grid electrode), seventh switch tube Mn7The first terminals (gates) are respectively connected to the buffer delay circuit 102, and include: the fifth switch tube Mn5First terminal (grid) and voltage acquisition module VbiasConnected, a sixth switching tube Mn6A first terminal (gate) connected to the first delay unit Y1, and a seventh switch tube Mn7The first terminal (gate) is connected to the second delay unit Y2.
When the voltage obtains the module VbiasWhen the control voltage is outputted, the fifth switch tube Mn5On, the first buffer operation circuit 101 outputs a first driving current; when the first delay unit Y1 and the voltage acquisition module VbiasWhen the control voltages are respectively output, the fifth switch tube Mn5And a sixth switching tube Mn6On, the first buffer operation circuit 101 outputs a second driving current; when the second delay cell Y2, the first delay cell Y1 and the voltage obtaining module VbiasWhen the control voltages are respectively output, the fifth switch tube Mn5The sixth switching tube Mn6And a seventh switching tube Mn7On, the first buffer operation circuit 101 outputs a third driving current; the first driving current, the second driving current and the third driving current are sequentially increased, and the sequentially increased first driving current, second driving current and third driving current form a stepped driving force.
Optionally, as shown in fig. 3, which is a schematic circuit diagram of the first delay unit Y1 in the buffering delay circuit 102, referring to fig. 3, the first delay unit Y1 includes a first resistor R1, a first zener diode D1, and a first capacitor C1, a first end of the first resistor R1 and the voltage obtaining module VbiasA second end of the first capacitor C1 is connected with the first end of the first voltage-stabilizing diode D1, a first end of the first capacitor D1 and a second end of the first resistor R1, and the other end of the first capacitor C1 is grounded; the second end of the first zener diode D1 and the sixth switch tube Mn6The first terminals (gates) are connected.
Referring to fig. 4, which is a schematic diagram of a circuit structure of the second delay unit Y2 in the buffering delay circuit 102, referring to fig. 4, the second delay unit Y2 includes a second resistor R2, a second zener diode D2 and a second capacitor C2, and a first end of the second resistor R2 is electrically connected to the second capacitor C2Pressure acquisition module VbiasA second end of the second capacitor C2 is connected with the first end of the second zener diode D2, the first end of the second zener diode D2 and the second end of the second resistor R2, and the other end of the second capacitor C2 is grounded; the second end of the second zener diode D2 and the seventh switch tube Mn7The first terminals (gates) are connected.
It should be noted that the resistor and the capacitor in the circuit structure of the second delay unit Y2 or the circuit structure of the first delay unit Y1 can form a delay circuit, and as the voltage at one end of the capacitor (between the capacitor, the resistor and the zener diode) increases, the zener diode is turned on to form a path until the value of the turn-on voltage of the zener diode is reached. According to actual needs, the resistance value of the resistor and the capacitance value of the capacitor in the delay circuit can be changed to obtain the delay time required by the first delay unit Y1 and/or the second delay unit Y2 respectively.
It will be understood that the number of delay cells provided in the buffer delay circuit 102 is related to the number of stages of the stepped driving force. Wherein, the voltage acquisition module V in the buffer delay circuit 102biasIt can also be regarded as a special delay unit, the voltage acquisition module VbiasThe delay time of (2) is 0.
Based on the above-mentioned control circuit, as shown in fig. 5, which is a waveform diagram of the voltage provided for the normal display of the pixel circuit according to the embodiment of the present application, referring to fig. 5, after the power module VCC1 in the first buffer operation circuit 101 receives the input voltage VIN, the clock signal CLK _ G of one line starts along with the start of the frame start signal STV, and the voltage obtaining module V _ G in the buffer delay circuit 102 starts along with the start of the frame start signal STVbiasThe control voltage outputted at the time t1 is applied to the fifth switch tube M of the first buffer operation circuit 101n5Providing the driving chip S-IC with the driving force of 50% N required by the load in the driving circuit; at time t2, the first zener diode D1 in the first delay unit Y1 of the buffering delay circuit 102 reaches the conducting voltage value to form a path, so that the control voltage output by the first delay unit Y1 is applied to the sixth switch M of the first buffering operation circuit 101n6Meanwhile, the control voltage is also continuously applied to the fifth switch tube M of the first buffer operation circuit 101n5Providing 80% of driving force required by the load in the driving circuit for the driving chip S-IC; at time t3, the second zener diode D2 in the second delay unit Y2 of the buffering delay circuit 102 reaches the conducting voltage value to form a path, so that the control voltage output by the second delay unit Y2 is applied to the seventh switch M of the first buffering operation circuit 101n7Meanwhile, the control voltage is also continuously applied to the fifth switch tube M of the first buffer operation circuit 101n5And a sixth switching tube Mn6In the above, the driving chip S-IC is provided with a driving force of 100% N required for driving the load in the circuit.
The voltage acquisition module V will be described belowbiasThe control voltage outputted at the time t1 is applied to the fifth switch tube M of the first buffer operation circuit 101n5To make the fifth switch tube Mn5Turning on is taken as an example, and a process of providing a step driving force to the driving chip S-IC in an actual application process is explained. The fifth switch tube M can be obtained according to the following formula (1)n5Magnitude of the driving force (i.e., magnitude of current) output.
In the above-mentioned formula (1),Kis a function of the number of the bits,V gs representative voltage acquisition module VbiasThe value of the voltage to be output,V th indicating the threshold voltage of the switching tube in the control circuit.
Voltage acquisition module VbiasAfter the control voltage is output, the fifth switch tube Mn5Conducting the first switch tube Mp1A second switch tube Mp2And a third switch tube Mn1And a fourth switching tube Mn2Form a complementary current mirror, and can switch the fifth switch tube Mn5The output current is copied to the output end, and I is realized by the following formula (2)outAnd IinWith the current in between following.
In the above formula (2)I out The current output at S1 in figure 2 is shown,I in showing a fifth switching tube Mn5The current of the output is measured by the current sensor,Athe number of the coefficients is represented by,Asee the following equation (3).
In the above formula (3), W and L represent the width and length of the transistor channel, respectively; vINRepresents the bias voltage, i.e., the voltage output by the power supply module VCC 1;V t which represents the gate voltage of the transistor,K N the coefficients are represented.
It should be noted that, according to practical applications, the reference current value output by the power module VCC1 and the control voltage value output by the buffer delay circuit 102 may be flexibly set, so as to implement output of the step driving force.
In the control circuit, the control voltage output by the buffering delay circuit 102 provides the driving chip S-IC with the stepped driving force required by the driving load through the first buffering operation circuit 101, that is, the driving force of the driving chip S-IC is adjusted by the stepped driving force, so that the driving force on the driving chip S-IC is gradually loaded into the load in a long time, and the driving force of each load reaches the current preset value required by the actual operation, thereby avoiding the problem that part of the loads in the display panel reaches the expected display effect and part of the loads does not reach the expected display effect due to the fact that the driving force cannot meet the current preset value in a short time due to voltage mutation at the moment that the display device is powered on.
Based on the control circuit, the embodiment of the present application further provides a display device, which includes at least one pixel unit, a driving chip S-IC and the control circuit, where the first buffer operation circuit 101 in the control circuit is in one-to-one correspondence with the at least one pixel unit, and the first buffer operation circuit 101 is connected in series between the corresponding pixel unit and the driving chip S-IC.
It should be understood that if a plurality of first buffer operation circuits 101 exist in the control circuit, each first buffer operation circuit 101 in the plurality of first buffer operation circuits 101 may be respectively connected to each sub-pixel unit in the pixel unit; and may be connected to the pixel units in the display device. The specific connection mode can be set according to different practical applications, and the application is not limited in any way.
Referring to fig. 2, the display device further includes a switch circuit 20, for example, a pixel unit in the AMOLED display panel includes a red sub-pixel unit, a green sub-pixel unit, and a blue sub-pixel unit, wherein a first buffer operation circuit 101 in the control circuit is connected to an output of the switch circuit 20, and the switch circuit is configured to sequentially output a control signal for turning on one sub-pixel unit in the pixel unit and turning off the other sub-pixel units within a preset time of a line scanning period.
In this embodiment, taking a pixel unit in the AMOLED display panel as an example, the first buffer operation circuit 101 in the control circuit is connected to the output of the switch circuit 20, and specifically includes: the switch circuit 20 includes a first switch sw1, a second switch sw2, and a third switch sw 3; a first terminal of the first switch sw1 is connected to the red subpixel, a first terminal of the second switch sw2 is connected to the green subpixel, a first terminal of the third switch sw3 is connected to the blue subpixel, a second terminal of the first switch sw1, a second terminal of the second switch sw2, and a second terminal of the third switch sw3 are connected to the first buffer operation circuit 101 in the control circuit.
It should be understood that the preset time may be determined according to the actual application requirement, and the time intervals of the output control signals of the switch circuits are equal. For example, if the pixel unit includes three sub-pixel units, the preset time may refer to a time less than one third of a row scanning period, and the switching circuit first outputs the first control signal in one row scanning period and then outputs the next control signal every time the time less than one third of the row scanning period elapses. For another example, if the pixel unit includes four sub-pixel units, the preset time may be a time less than one fourth of a line scanning period, and the switch circuit outputs the first control signal in one line scanning period, and then outputs the next control signal after each time less than one fourth of the line scanning period elapses.
By way of example and not limitation, referring to fig. 6, during one row scanning period T, the switch circuits first output a first control signal for turning on the first switch sw1, turning off the second switch sw2 and the third switch sw3, and sending the gray scale voltage Rn to the circuit corresponding to the red sub-pixel unit, so that the red sub-pixel achieves the desired display effect; then after the time less than one third T (neglecting the delay of the switch wiring and the like), the switch circuit outputs a second control signal for opening the second switch sw2, closing the first switch sw1 and the third switch sw3, and sending the gray voltage Gn to the circuit corresponding to the green sub-pixel unit, so that the green sub-pixel achieves the expected display effect; in the same switching period (after the time less than one third of T elapses), the switching circuit outputs a third control signal for turning on the third switch sw3, turning off the first switch sw1 and the second switch sw2, and sending the grayscale voltage Bn to the circuit corresponding to the blue sub-pixel unit, so that the blue sub-pixel achieves the desired display effect.
It should be understood that, based on fig. 2, the gray voltages for bringing the display luminance of the display panel to the desired display effect within the driving time are output by S1.
Example two
In one possible implementation, the number of the first buffer operation circuits 101 in the control circuit is equal to the number of the pixel units, that is, the number of the first buffer operation circuits 101 in the driving circuit 10 is related to the resolution of the display device. As will be understood, in the AMOLED display panel, one pixel unit includes three sub-pixel units, each sub-pixel unit includes sub-pixels of one color, and when the number of the first buffer operation circuits 101 in the control circuit is equal to the number of the pixel units, the number of the first buffer operation circuits 101 is equal to the number of the sub-pixels of each color in each pixel unit. For example, if a pixel unit includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel, and the number of sub-pixels of each color in the pixel unit is 1, the corresponding control circuit includes a first buffer operation circuit 101.
Compared with the case that a plurality of sub-pixel units in each row of pixel units in fig. 1 need to be connected with one output buffer, the number of the buffer operation circuits in the present application is equal to the number of the pixel units in each row, for example, referring to fig. 2, one pixel unit in the AMOLED display panel shares one first buffer operation circuit 101, which can effectively reduce the design capacity of the driving chip, reduce the area of the chip, and save the manufacturing cost.
In the embodiment of the application, the AMOLED display panel includes two pixel units, and the control circuit includes two output buffer operation circuits.
Fig. 7 is a schematic diagram of another control circuit provided in the embodiment of the present application, where the control circuit includes a first buffer operation circuit 101, a second buffer operation circuit 103, and a buffer delay circuit 102, and the connection manner of the first buffer operation circuit 101 and the buffer delay circuit 102 may refer to the related description in the first embodiment, which is not repeated herein.
The second buffer operation circuit 103 includes a power module VCC2 and an eighth switch tube Mp3The ninth switch tube Mp4The tenth switch tube Mn3Eleventh switching tube Mn4The twelfth switch tube Mn8Thirteenth switch tube Mn9And a fourteenth switching tube Mn10(ii) a The connection relationship between the power module VCC2 and each switching tube in the second buffer operation circuit 103 is the same as the connection relationship between the power module VCC1 and each switching tube in the first buffer operation circuit 101 in the above embodiment, and is not described herein again.
In addition, the tenth switching tube M in the second buffer arithmetic circuit 103n3The first end (grid) of the driving chip is connected with the driving chip S-IC; twelfth switch tube Mn8And the fifth switch tube M in the first buffer operation circuit 101n5First terminal (grid) and buffer delay circuit102, voltage acquisition module VbiasConnecting; thirteenth switch tube Mn9First end (grid) of and sixth switching tube Mn6Is connected to the first terminal (gate) of the first delay cell Y1; fourteenth switching tube Mn10First terminal (grid) of (1) and seventh switching tube Mn7Is connected to the second delay cell Y2.
It should be understood that the above-mentioned eighth switch tube Mp3And the ninth switch tube Mp4Is a P-type MOS tube; tenth switching tube Mn3Eleventh switching tube Mn4The twelfth switch tube Mn8Thirteenth switch tube Mn9And a fourteenth switching tube Mn10Is an N-type MOS tube; the first end is a grid electrode, the second end is a drain electrode, and the third end is a source electrode.
It should be understood that, when the pixel circuit in each row of the AMOLED display panel includes N pixel units, the corresponding control circuit may include N output buffer operation circuits, and the N output buffer operation circuits are respectively connected to the N pixel units in a one-to-one correspondence manner.
Illustratively, the pixel circuit of each row in the AMOLED display panel includes a pixel unit, and the pixel unit includes a red sub-pixel unit, a green sub-pixel unit, and a blue sub-pixel unit, then the corresponding control circuit includes a first buffer operation circuit 101 as shown in fig. 2; if the pixel circuit of each row in the AMOLED display panel includes two pixel units, the two pixel units respectively include two sets of sub-pixel units, where each set of sub-pixel unit includes a red sub-pixel unit, a green sub-pixel unit, and a blue sub-pixel unit, the corresponding control circuit includes a first buffer operation circuit 101 and a second buffer operation circuit 103 as shown in fig. 5, that is, the control circuit includes two output buffer operation circuits.
As the resolution is increased, the number of pixel units in each row of pixel circuits of the AMOLED display panel increases, and the number of output buffer operation circuits in the control circuit increases as the number of pixel units in each row increases.
Based on the above control circuit, the embodiment of the present application further provides a display device, which includes at least one pixel unit, a driving chip S-IC, a switch circuit 20 and the above control circuit, referring to fig. 7, still taking an example that the AMOLED display panel includes two pixel units, the two pixel units include two groups of sub-pixel units, each group of sub-pixel units includes a red sub-pixel unit, a green sub-pixel unit and a blue sub-pixel unit, and the first buffer operation circuit 101 and the second buffer operation circuit 103 in the control circuit are respectively connected to outputs of the switch circuit 20.
The switch circuit 20 includes two sets of switch groups, the first set of switch groups includes a first switch sw1, a second switch sw2, and a third switch sw 3; the second group of switches includes a fourth switch sw4, a fifth switch sw5, and a sixth switch sw 6.
It should be understood that when two pixel units are included in the AMOLED display panel, the manner in which each sub-pixel unit in the two pixel units receives the control signal can be seen in two manners as shown in fig. 7 and 8, and as shown in fig. 7, the sub-pixel units of the same color in the two pixel units can receive the same control signal based on the same signal output terminal; for example, the red sub-pixel unit of the two pixel units receives the same control signal R _ sw based on the same connection circuit. As shown in fig. 8, the sub-pixel units of the same color in the two pixel units can also receive the same control signal through different signal output terminals. For example, a red sub-pixel cell in one pixel cell receives the output control signal R _ sw1, a red sub-pixel cell in another pixel cell receives the output control signal R _ sw2, and the control signal R _ sw1 is the same control signal as the control signal R _ sw 2.
It should be understood that the same control signal means that the output time, the reception time, and the command type of turning on or off of the control signal are the same.
The connection method of the two buffer operation circuits and the switch circuit 20 in the control circuit may be another connection method according to the resolution of the display device, which is not limited in this application.
It should be understood that in the embodiments of the present application, the pixel unit in the control circuit or the display device includes a plurality of sub-pixel units of different colors, and for example, the pixel unit may include a red sub-pixel unit, a green sub-pixel unit, and a blue sub-pixel unit; alternatively, the pixel unit may include a red sub-pixel unit, a green sub-pixel unit, a blue sub-pixel unit, and a white sub-pixel unit. That is to say, the display device provided in the embodiment of the present application may be a display based on RGB display, or may be a display based on RGBW display. The number of sub-pixels in a pixel unit or the display type of the display device is not limited in any way.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus/electronic device and method may be implemented in other ways. For example, the above-described apparatus/electronic device embodiments are merely illustrative, and for example, a module or a unit may be divided into only one type of logic function, and another division may be implemented in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".
Furthermore, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between descriptions and not necessarily for describing or implying relative importance.
Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather mean "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. A control circuit, wherein the control circuit comprises at least one buffer arithmetic circuit and a buffer delay circuit; the buffer delay circuit is respectively connected with the at least one buffer operation circuit,
the buffer delay circuit is used for sequentially outputting at least two control voltages; the buffer operation circuit is used for correspondingly outputting at least two sequentially increased driving currents according to the at least two control voltages.
2. The control circuit according to claim 1, wherein the buffer operation circuit comprises a power module, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, a sixth switch tube and a seventh switch tube;
the first end of the first switch tube, the first end of the second switch tube and the third end of the second switch tube are connected; the second end of the first switch tube, the second end of the second switch tube and the power supply module are connected; the third end of the first switch tube, the second end of the third switch tube and the first end of the fourth switch tube are connected;
the first end of the third switching tube is connected with an external driving chip, the third end of the third switching tube is connected with the third end of the fourth switching tube, and the third end of the third switching tube is respectively connected with the second end of the fifth switching tube, the second end of the sixth switching tube and the second end of the seventh switching tube;
the first end of the fifth switch tube, the first end of the sixth switch tube and the first end of the seventh switch tube are respectively connected with the buffering delay circuit, and the third end of the fifth switch tube, the third end of the sixth switch tube and the third end of the seventh switch tube are connected and grounded.
3. The control circuit of claim 2, wherein the buffer delay circuit comprises a voltage acquisition module, a first delay unit and a second delay unit; the fifth switch tube first end, the sixth switch tube first end, the seventh switch tube first end respectively with the buffering delay circuit links to each other, includes:
the first end of the fifth switching tube is connected with the voltage acquisition module, the first end of the sixth switching tube is connected with the first delay unit, and the first end of the seventh switching tube is connected with the second delay unit;
when the voltage acquisition module outputs the control voltage, the fifth switching tube is conducted, and the buffer operation circuit outputs a first driving current;
when the first delay unit and the voltage acquisition module respectively output the control voltage, the fifth switching tube and the sixth switching tube are conducted, and the buffer operation circuit outputs a second driving current;
when the second delay unit, the first delay unit and the voltage acquisition module respectively output the control voltage, the fifth switch tube, the sixth switch tube and the seventh switch tube are turned on, and the buffer operation circuit outputs a third driving current;
the first drive current, the second drive current, and the third drive current increase in sequence.
4. The control circuit according to claim 3, wherein the first switching tube and the second switching tube are P-type MOS tubes, and the third switching tube, the fourth switching tube, the fifth switching tube, the sixth switching tube and the seventh switching tube are N-type MOS tubes;
the first end is a grid electrode, the second end is a drain electrode, and the third end is a source electrode.
5. The control circuit according to claim 3 or 4, wherein the first delay unit comprises a first resistor, a first zener diode, and a first capacitor, a first end of the first resistor is connected to the voltage acquisition module, a second end of the first resistor is connected to a first end of the first zener diode, one end of the first capacitor is connected to the first end of the first zener diode and the second end of the first resistor, and the other end of the first capacitor is grounded; and the second end of the first voltage stabilizing diode is connected with the first end of the sixth switching tube.
6. The control circuit according to claim 3 or 4, wherein the second delay unit comprises a second resistor, a second zener diode, and a second capacitor, a first end of the second resistor is connected to the voltage acquisition module, a second end of the second resistor is connected to a first end of the second zener diode, one end of the second capacitor is connected to the first end of the second zener diode and the second end of the second resistor, and the other end of the second capacitor is grounded; and the second end of the second voltage stabilizing diode is connected with the first end of the seventh switch tube.
7. A display device comprising at least one pixel cell and a driver chip, characterized in that the display device further comprises a control circuit according to any one of claims 1-6;
at least one buffering operation circuit in the control circuit corresponds to at least one pixel unit one by one, and each buffering operation circuit is connected in series between the corresponding pixel unit and the driving chip.
8. The device of claim 7, wherein the pixel unit comprises a plurality of sub-pixel units of different colors.
9. The device according to claim 8, wherein the display device further comprises a switch circuit, and the switch circuit is configured to sequentially output a first control signal within a preset time of one row scanning period, and the first control signal is configured to turn on one sub-pixel unit of the pixel units and turn off other sub-pixel units.
10. The apparatus of claim 9, wherein the first control signals corresponding to sub-pixel units of a same color in at least one of the pixel units are the same.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20130002567U (en) * | 2011-10-20 | 2013-04-30 | 에릭슨 엘지 주식회사 | Apparatus for preventing in-rush current |
| CN103927978A (en) * | 2013-12-31 | 2014-07-16 | 厦门天马微电子有限公司 | Active matrix/organic light emitting diode (AMOLED) display panel and organic light emitting display device |
| CN109616042A (en) * | 2019-02-14 | 2019-04-12 | 京东方科技集团股份有限公司 | Pixel circuit and its driving method, display device |
| CN110047436A (en) * | 2019-06-06 | 2019-07-23 | 京东方科技集团股份有限公司 | Pixel circuit, array substrate, its driving method, display panel and display device |
| CN113516938A (en) * | 2021-06-23 | 2021-10-19 | 惠科股份有限公司 | Driving circuit and driving method of display panel and display device |
| CN114038388A (en) * | 2021-12-14 | 2022-02-11 | 集创北方(珠海)科技有限公司 | Output control circuit of source driving chip and display panel |
-
2022
- 2022-04-28 CN CN202210457455.0A patent/CN114582267A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20130002567U (en) * | 2011-10-20 | 2013-04-30 | 에릭슨 엘지 주식회사 | Apparatus for preventing in-rush current |
| CN103927978A (en) * | 2013-12-31 | 2014-07-16 | 厦门天马微电子有限公司 | Active matrix/organic light emitting diode (AMOLED) display panel and organic light emitting display device |
| CN109616042A (en) * | 2019-02-14 | 2019-04-12 | 京东方科技集团股份有限公司 | Pixel circuit and its driving method, display device |
| CN110047436A (en) * | 2019-06-06 | 2019-07-23 | 京东方科技集团股份有限公司 | Pixel circuit, array substrate, its driving method, display panel and display device |
| CN113516938A (en) * | 2021-06-23 | 2021-10-19 | 惠科股份有限公司 | Driving circuit and driving method of display panel and display device |
| CN114038388A (en) * | 2021-12-14 | 2022-02-11 | 集创北方(珠海)科技有限公司 | Output control circuit of source driving chip and display panel |
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