CN114580341B - Method for solving chip time sequence deterioration caused by Metal filling Metal Fill - Google Patents
Method for solving chip time sequence deterioration caused by Metal filling Metal Fill Download PDFInfo
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- CN114580341B CN114580341B CN202210209763.1A CN202210209763A CN114580341B CN 114580341 B CN114580341 B CN 114580341B CN 202210209763 A CN202210209763 A CN 202210209763A CN 114580341 B CN114580341 B CN 114580341B
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- 239000002184 metal Substances 0.000 title claims abstract description 68
- 238000000034 method Methods 0.000 title claims abstract description 31
- 230000006866 deterioration Effects 0.000 title abstract description 9
- 230000004888 barrier function Effects 0.000 claims abstract description 22
- 238000013461 design Methods 0.000 claims description 21
- 230000015556 catabolic process Effects 0.000 claims description 5
- 238000006731 degradation reaction Methods 0.000 claims description 5
- 230000014759 maintenance of location Effects 0.000 claims description 3
- 230000008569 process Effects 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 238000012795 verification Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/02—System on chip [SoC] design
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Abstract
The embodiment of the invention relates to a method for solving the problem of chip time sequence deterioration caused by metal filling Meta l Fill. The method comprises the following steps: performing metal filling in a place and route step; determining whether time violations exist at each time sequence endpoint (time delay) on each time sequence path (time path) in the chip after metal filling; determining the timing path as a timing risk path (timing crit ical path) when there is a time violation; and generating a virtual barrier layer with a set width aiming at the time sequence risk path, and setting the virtual barrier layer along the time sequence risk path to replace the metal filling on the position occupied by the virtual barrier layer.
Description
Technical Field
The present invention relates to the field of chip design technology, and in particular, to a method for solving the problem of chip timing degradation caused by Metal filling.
Background
Chemical-mechanical polishing (Chemical-mechanical polishing, CMP) is a step in the semiconductor processing. However, during the wafer processing, the process step may generate a large concave area in the area where the interconnection metal line is not present, so that after the CMP process, the metal line and the isolation layer between the metal lines may generate a problem of roughness, which may cause signal delay of the chip.
To cope with this situation, the function of automatically inserting a Fill Metal Fill is provided in an electronic design automation (Electronic Design Automation, EDA) tool of an integrated circuit, which has been very commonly applied in integrated circuit back-end designs.
However, since the Fill Metal Fill is done after the timing analysis is signed after the design rule check (Design Rule Check, DRC) and consistency check (Layout Versus Schematic, LVS) at the end of the entire design cycle, the additional parasitic capacitance created by the added Metal level due to the Fill Metal Fill is ignored.
It has been shown that in the prior art 40nm process, the effect of these additional parasitic capacitances on the timing is approximately 0.12%, and this neglect has no effect on the final chip performance, whereas in the 28nm process, the effect of these parasitic capacitances is increased to 2.5%, and in the 16nm process, the average error is up to 4%, and in the more advanced 10nm, 7nm and below processes, the effect is even greater, up to even more than 5%. They can cause timing degradation of the final actual chip with serious consequences.
For this reason, chip design engineers have to re-analyze the whole chip with the addition of these new Metal patterns (i.e. after the Metal Fill is completed), including re-performing the extraction of the complete parasitic parameters, and then bringing these new parasitic parameters into the complete physical verification, timing verification, functional verification, and if new problems caused by the Metal Fill are found in the process, the design needs to be changed again, which will necessarily affect the whole design cycle.
Disclosure of Invention
The present invention provides a method for solving the problem of chip timing degradation caused by Metal filling Metal Fill, which identifies the timing path of the time violation (time alignment) after Metal Fill by performing Metal Fill in the step of Place & Route. And setting virtual barrier layers to replace metal filling on positions occupied by the virtual barrier layers aiming at paths with time sequence risks caused by the identified metal filling, so as to realize that the set areas where the paths are positioned are not filled with metal.
The embodiment of the invention provides a method for solving the problem of chip time sequence deterioration caused by Metal filling, which comprises the following steps:
performing metal filling in a place and route step;
determining whether time violations exist at each time sequence endpoint (time delay) on each time sequence path (time path) in the chip after metal filling;
determining the timing path as a timing risk path (timing criticalpath) when there is a time violation;
and generating a virtual barrier layer with a set width aiming at the time sequence risk path, and setting the virtual barrier layer along the time sequence risk path to replace the metal filling on the position occupied by the virtual barrier layer.
Preferably, the time violations include a setup time violation and a hold time violation.
Preferably, determining whether time violations exist at each timing endpoint on each timing path in the metal-filled chip specifically includes:
acquiring the establishment time and the holding time of each time sequence endpoint on each time sequence path in the chip;
determining first violation time corresponding to the establishment time violation and second violation time corresponding to the retention time violation of each time sequence endpoint according to the clock period of the chip;
determining, for each timing path, whether a time interval between the setup time and the first violation time of each timing endpoint satisfies a set timing margin (timing margin), and whether a time interval between a termination time and the second violation time after the hold time has elapsed from the setup time satisfies a set timing margin;
determining, for each timing path, whether a time interval between the setup time and the first violation time of each timing endpoint satisfies a set timing margin, and whether a time interval between a termination time and the second violation time after the hold time has elapsed from the setup time satisfies a set timing margin.
Further preferably, the set timing margin is 0.5ps.
Further preferably, the set timing margin is 5% of the clock period of the chip.
Further preferably, the set width is a user-defined specified width.
Further preferably, the set width is a minimum pitch allowed by the chip design rule.
Further preferably, the set width is 2 times of the minimum pitch allowed by the chip design rule.
According to the method for solving the problem of chip time sequence deterioration caused by Metal filling Metal Fill, the time sequence path with time violations (time alignment) after Metal Fill is identified by executing Metal Fill in the step of layout and routing. And setting virtual barrier layers to replace metal filling on positions occupied by the virtual barrier layers aiming at paths with time sequence risks caused by the identified metal filling, so as to realize that the set areas where the paths are positioned are not filled with metal. The method not only avoids the chip time sequence deterioration caused by metal filling, but also can effectively improve the design efficiency and shorten the design period.
Drawings
FIG. 1 is a flowchart of a method for solving the problem of chip timing degradation caused by Metal Fill in accordance with an embodiment of the present invention.
Detailed Description
The technical scheme of the invention is further described in detail through the drawings and the embodiments.
The embodiment of the invention provides a method for solving the problem of chip time sequence deterioration caused by Metal filling (Metal Fill), which mainly comprises the following steps:
a step 110 of performing Metal filling (Metal Fill) in the place and route step;
in particular, the execution of the metal fills may be performed by calling a corresponding functional module provided in the EDA tool.
Step 120, determining whether there is a time violation (time alignment) at each timing endpoint (timing nodes) on each timing path (timing path) in the chip after Metal filling (Metal Fill);
specifically, the time violations (time resolution) include setup time violations (setup time violation) and hold time violations (hold time violation).
For the setup time, data transfer from one register to the next register is guaranteed to reach the next register before the next register receives the clock trigger edge signal, in other words, the elapsed time on the data transfer path (data path) is guaranteed to be shorter than the time sequence path+one clock period (timing path+tclk), so that the correct transfer of data can be guaranteed, otherwise, a violation, namely, a setup time violation (setup time violation) occurs.
For the hold time, the data is held for a certain time relative to the time when the register receives the clock edge signal, in other words, the data transmission path (data path) is guaranteed to have a longer time than the time of the timing path (timing path), so as to guarantee that the correct transmission of the data is otherwise violated, namely, the hold time violation (hold time violation).
In the present invention, to avoid the risk of violations due to Metal Fill, a redundancy is added to the time violations, namely the timing margin (timing margin) mentioned below.
The method for determining whether a time violation exists may be specifically as follows:
s1, acquiring the setup time (setup time) and the hold time (hold time) of each time sequence endpoint (time) on each time sequence path (time) in a chip;
specifically, setup time (setup time) and hold time (hold time) can be obtained by functions provided by a Place & Route (Place & Route) tool.
S2, determining first violation time corresponding to the establishment time violation (setup time violation) and second violation time corresponding to the retention time violation (hold time violation) of each time sequence endpoint according to the clock period of the chip;
specifically, the first violation time is just the critical time that does not satisfy the timing path+one clock cycle (timingpath+tclk);
the second violation time, that is, the time that just does not satisfy the elapse of the data transmission path (data path), is longer than the time that elapses on the timing path (timing path).
S3, determining whether the time interval between the establishment time of each time sequence endpoint and the first violation time meets the set time sequence margin (timing margin) or not and whether the time interval between the termination time after the hold time passes from the establishment time and the second violation time meets the set time sequence margin (timing margin) or not for each time sequence path;
wherein the setup time is earlier than the first violation time and the expiration time after the hold time has elapsed from the setup time is later than the second violation time.
S4, determining whether the time interval between the establishment time of each time sequence endpoint and the first violation time meets the set time sequence margin (timing margin) or not and whether the time interval between the termination time after the hold time passes from the establishment time and the second violation time meets the set time sequence margin (timing margin) or not for each time sequence path;
s5, if the time interval is greater than or equal to the set time sequence margin, the time interval is considered to be satisfied; if the time interval is less than the set timing margin, it is deemed not to be satisfied.
The timing margin is set to a fixed value, for example 0.5ps, or defined as 5% of the clock period of the chip.
Step 130, when there is a time violation (timing), determining the timing path as a timing risk path (timing critical path);
if there is no time violation, then the flow of steps of the method is not continued.
In step 140, a dummy barrier is generated with a set width for the time-series risk path, and the dummy barrier is set along the time-series risk path to replace Metal Fill (Metal Fill) on the position occupied by the dummy barrier.
Specifically, the set width may be a user-defined specified width, or may be a minimum spacing (spacing) allowed by a chip design rule, or a minimum spacing of 2 times. The virtual barrier layers are symmetrically arranged on two sides of the time sequence risk path according to the width of the virtual barrier layers and are used for occupying physical positions so as to replace Metal filling (Metal filling) on the positions occupied by the virtual barrier layers, and Metal filling is not carried out in a set area near the time sequence risk path. It should be noted that these virtual barriers do not actually exist, but rather the virtual placements are implemented without any other impact on the design itself.
According to the method for solving the problem of chip time sequence deterioration caused by Metal filling (Metal filling), the time sequence path with time violations (time navigation) after Metal filling (Metal filling) is identified by executing Metal filling in the step of layout and routing. For paths with time sequence risks caused by the identified Metal filling, a virtual barrier layer is arranged to replace Metal filling (Metal filling) on the position occupied by the virtual barrier layer, so that the set areas where the paths are located are not filled with Metal. The method not only avoids the chip time sequence deterioration caused by Metal filling, but also can effectively improve the design efficiency and shorten the design period.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of function in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the scope of the invention, but to limit the invention to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (7)
1. A method for solving the problem of chip timing degradation caused by Metal Fill, the method comprising:
performing metal filling in a place and route step;
determining whether time violations exist at each time sequence endpoint (time delay) on each time sequence path (time path) in the chip after metal filling;
determining the timing path as a timing risk path (timing critical path) when there is a time violation;
generating a virtual barrier layer with a set width for a time sequence risk path, and setting the virtual barrier layer along the time sequence risk path to replace the metal filling on the position occupied by the virtual barrier layer;
the determining whether time violations exist at each time sequence endpoint on each time sequence path in the chip filled with the metal specifically comprises the following steps:
acquiring the establishment time and the holding time of each time sequence endpoint on each time sequence path in the chip;
determining first violation time corresponding to the establishment time violation and second violation time corresponding to the retention time violation of each time sequence endpoint according to the clock period of the chip;
determining, for each timing path, whether a time interval between the setup time and the first violation time of each timing endpoint satisfies a set timing margin (timing margin), and whether a time interval between a termination time and the second violation time after the hold time has elapsed from the setup time satisfies a set timing margin;
determining, for each timing path, whether a time interval between the setup time and the first violation time of each timing endpoint satisfies a set timing margin, and whether a time interval between a termination time and the second violation time after the hold time has elapsed from the setup time satisfies a set timing margin.
2. The method of claim 1, wherein the time violations comprise a setup time violation and a hold time violation.
3. The method of claim 1, wherein the set timing margin is 0.5ps.
4. The method of claim 1, wherein the set timing margin is 5%o of the clock period of the chip.
5. The method of claim 1, wherein the set width is a user-defined specified width.
6. The method of claim 1, wherein the set width is a minimum pitch allowed by the chip design rule.
7. The method of claim 1, wherein the set width is 2 times the minimum pitch allowed by the chip design rule.
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| CN202210209763.1A CN114580341B (en) | 2022-03-03 | 2022-03-03 | Method for solving chip time sequence deterioration caused by Metal filling Metal Fill |
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| CN202210209763.1A CN114580341B (en) | 2022-03-03 | 2022-03-03 | Method for solving chip time sequence deterioration caused by Metal filling Metal Fill |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008283087A (en) * | 2007-05-14 | 2008-11-20 | Sharp Corp | Design method of semiconductor integrated circuit, program for making the method executed, and semiconductor integrated circuit |
| CN110096722A (en) * | 2018-01-31 | 2019-08-06 | 三星电子株式会社 | The method of computer-readable medium and manufacture semiconductor device including program code |
| CN110717309A (en) * | 2019-10-10 | 2020-01-21 | 天津飞腾信息技术有限公司 | Redundant metal filling method, device, equipment and computer readable storage medium |
| CN112214960A (en) * | 2020-10-13 | 2021-01-12 | 天津飞腾信息技术有限公司 | Redundant metal filling method and system considering integrated circuit time sequence |
| US10943051B1 (en) * | 2019-09-10 | 2021-03-09 | International Business Machines Corporation | Metal fill shape removal from selected nets |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8397196B2 (en) * | 2011-05-03 | 2013-03-12 | Lsi Corporation | Intelligent dummy metal fill process for integrated circuits |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008283087A (en) * | 2007-05-14 | 2008-11-20 | Sharp Corp | Design method of semiconductor integrated circuit, program for making the method executed, and semiconductor integrated circuit |
| CN110096722A (en) * | 2018-01-31 | 2019-08-06 | 三星电子株式会社 | The method of computer-readable medium and manufacture semiconductor device including program code |
| US10943051B1 (en) * | 2019-09-10 | 2021-03-09 | International Business Machines Corporation | Metal fill shape removal from selected nets |
| CN110717309A (en) * | 2019-10-10 | 2020-01-21 | 天津飞腾信息技术有限公司 | Redundant metal filling method, device, equipment and computer readable storage medium |
| CN112214960A (en) * | 2020-10-13 | 2021-01-12 | 天津飞腾信息技术有限公司 | Redundant metal filling method and system considering integrated circuit time sequence |
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