CN114567973B - PCB packaging method for CQFP chip with non-metallized through holes - Google Patents
PCB packaging method for CQFP chip with non-metallized through holes Download PDFInfo
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- CN114567973B CN114567973B CN202210125707.XA CN202210125707A CN114567973B CN 114567973 B CN114567973 B CN 114567973B CN 202210125707 A CN202210125707 A CN 202210125707A CN 114567973 B CN114567973 B CN 114567973B
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 45
- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000000463 material Substances 0.000 claims description 17
- 229910052755 nonmetal Inorganic materials 0.000 claims description 8
- 238000005476 soldering Methods 0.000 claims description 3
- 230000001502 supplementing effect Effects 0.000 claims description 2
- 238000007689 inspection Methods 0.000 abstract description 2
- 230000007547 defect Effects 0.000 abstract 1
- 230000035515 penetration Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000035882 stress Effects 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000009469 supplementation Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3447—Lead-in-hole components
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Structure Of Printed Boards (AREA)
Abstract
The invention discloses a PCB packaging method of a CQFP chip with a non-metallized through hole, which comprises the following steps: determining the position of the non-metallized through holes; the size of the PCB package is related to the number of non-metallized through holes; relation between aperture of non-metallized through hole and diameter of perforated object; the basic requirements of non-metallized through-hole penetrations. The invention directly determines the relevant parameters and positions of the non-metallized through holes in the packaging design stage of the PCB, on one hand, the omission of non-metallized holes of some key components can be avoided, and on the other hand, the defect of discontinuous signal integrity caused by determining the hole points after the placement of the components of the PCB is completed can be avoided. In the process of laying out and wiring of the PCB, the PCB packaging structure with the non-metallized through holes ensures that each component needing to be drilled can be drilled normally, thus not only improving the inspection efficiency of an electronic process, but also reducing the error probability and the design difficulty of the laying out and wiring, and further improving the anti-interference capability and the reliability of the product.
Description
Technical Field
The invention relates to the technical field of PCB packaging, in particular to a PCB packaging method of a CQFP chip with a non-metallized through hole.
Background
With the continuous development of electronic technology, the use of printed circuit boards is also becoming more frequent and complex. The PCB packaging of the component is the core of the printed circuit board and is also an important component thereof. The improvement and perfection of the PCB packaging technology is an important mark for displaying the maturity and stability of the printed circuit board. At present, the PCB packaging technology has undergone up to decades of supplementation and perfection, and even in many large-scale enterprises, the full-time posts of a PCB packaging library and a schematic diagram symbol library are arranged to cope with the ever-changing and increasingly complex packaging requirements, so that the PCB packaging occupies a significant position in the field of electronic design. CQFP (Cearmci Quad FlPaack) the package is a sealed surface-mounted package, CQFP is an advanced device package, adopts a ceramic substrate and gold-plated leads, has the characteristics of small volume, light weight, high packaging density, good thermoelectric performance, suitability for surface mounting, high reliability and the like, and is widely applied to the fields of military, aerospace and aviation.
However, for some special components, the PCB package needs to meet not only the requirements of general electrical connection characteristics but also mechanical characteristics or thermal characteristics. Often, these mechanical or thermal properties are critical factors in the success or failure of the product. At present, the importance of PCB packaging is not strict whether in the common commercial market or the fields of civil use, aerospace and the like, so that various technical problems occur in the design process or due to unreasonable packaging, and the technical indexes and requirements required in the aerospace field cannot be met.
At present, in the packaging field of a PCB, the following methods are mainly available in the aspects of package design, analysis and the like:
patent application number 201710628841.0, entitled "a QFN chip PCB packaging method and PCB", discloses a QFN chip PCB packaging method, which determines a pin pad to be electrically connected with an intermediate pad, and electrically connects the pin pad with the intermediate pad through a wiring layer; and adjusting the size of the solder mask of the pin pad electrically connected with the intermediate pad and/or the size of the solder mask of the intermediate pad so that the distance between the solder mask of the pin pad and the solder mask of the intermediate pad is more than or equal to the set distance.
The basic learning and application of a PCB packaging library, a computer knowledge technology, the 14 th edition of 2018, and the 11 th edition disclose a method for manually drawing a PCB packaging model on the basis of DXP software, and the model design wizard of a software system is utilized to customize the PCB packaging meeting the design requirements of the user.
The design and optimization of a high-speed BGA package and PCB differential interconnection structure, modern electronic technology, volume 40, period 22 in 2017, discloses the specific influence of four aspects of a package and PCB interconnection area differential wiring mode, a signal layout mode, a signal hole/ground hole ratio, a wiring layer and a via stub on high-speed differential signal transmission performance and crosstalk.
The thermal stress analysis of different packaging structures on the same PCB, electronic elements and materials, in 2013, 32 volume, stage 2, are used for researching stress fields of QFP and PBGA on the same PCB under temperature cycle load, and comparing and analyzing the performances of different packaging structures. The results show that: under the temperature cyclic load, no matter what package assembly is, the closer to the edge of the PCB, the larger the stress value of the device is; under the same conditions, the stress value of the PBGA packaging device is higher than that of the QFP packaging device.
Patent application number 201710617180.1, entitled "method and apparatus for designing a PCB package", discloses a PCB package library with a forbidden area. The PCB packaging design method and the device provided by the invention are used for binding the forbidden coverage area in the device packaging library, and when the device packaging library is called for PCB design, the forbidden coverage area is bound in the graphic symbol of the called device. The forbidden area of the device can not be deleted independently, and the device can only be deleted entirely.
In summary, the prior art does not provide a PCB package with a non-metallized through hole for a CQFP chip, which can effectively avoid the problem of missing or staggering through holes of some components and the problem of signal integrity after opening holes.
Disclosure of Invention
The invention aims to provide a PCB packaging method of a CQFP chip with a non-metallized through hole.
In order to achieve the above purpose, the invention provides a PCB packaging method of a CQFP chip with a non-metallized through hole, comprising the following steps:
step S1, establishing a PCB package;
step S2, judging whether to perform nonmetal through hole arrangement;
step S3, determining the number and the positions of the nonmetallic through holes under the condition of carrying out the nonmetallic through holes;
wherein the relationship between the size of the PCB package and the number of non-metallized vias is determined by:
wherein: n is the number of non-metallized through holes, and the unit is one; l (L) max : edge of longest edgeThe length is given in cm.k, constant, k=1 cm;
s4, determining the relation between the aperture of the non-metallized through hole and the non-metallized perforated material;
and S5, generating the PCB package with the non-metallized through holes according to the perforation material of the non-metallized through holes.
Preferably, in the step S2, when the bonding force of the component pin soldering is insufficient to cope with high-strength mechanical impact, non-metallized through hole arrangement is performed, and/or; the components with the large-size package base are provided with non-metallized through holes and/or; when the height dimension of the component exceeds 2 times of the distance between the chip pins and the printed circuit board, fixing the non-metallized through holes and/or; and when the total weight of the component exceeds 2 times of the weight of the lead-out pins of the chip, fixing the non-metallized through holes.
Preferably, in the step S3, the positions of the non-metallized through holes are respectively disposed at two sides of the component.
Preferably, the non-metallized through hole positions are arranged at 1/2 point, 1/3 point and 1/4 point of the two longest sides of the component.
Preferably, in the step S3, the positions of the non-metallized through holes are set according to the shape and size of the PCB package.
Preferably, in the step S4, the number of non-metallized through holes is set according to the shape and size of the PCB package.
Preferably, in the step S5, the diameter of the non-metallized through hole is greater than or equal to 2 times the diameter of the perforated material.
Preferably, in the step S5, the diameter of the perforated material is determined according to the aperture of the non-metallized through hole; or determining the aperture of the non-metallized through holes according to the diameter of the perforated material.
Compared with the prior art, the invention has the following beneficial effects:
firstly, by adopting the method of packaging the components with the non-metallized through holes, the problem caused by the reduction or increase of the number of the non-metallized through holes due to misoperation of engineers is solved, and the error probability and the workload of PCB engineers are reduced.
Secondly, by adopting a method of packaging the components with the non-metallized through holes, the situation that a large number of wires are routed due to the need of avoiding the non-metallized through holes in the later period is avoided to a certain extent, the problem of incomplete signals possibly caused is avoided, and the purposes of high reliability and high stability are achieved.
Drawings
FIG. 1 is a schematic diagram of steps of a PCB packaging method of a CQFP chip with non-metallized through holes according to the present invention;
FIG. 2 is a schematic diagram of a PCB package with non-metallized through holes according to the present invention;
FIG. 3 is a diagram illustrating an example of a related non-metallized via in an embodiment of the invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 1, the invention provides a method for packaging a CQFP chip with a PCB with a non-metallized through hole, which is characterized by comprising the following steps:
step S1, establishing a PCB package;
step S2, judging whether to perform nonmetal through holes or not;
step S3, determining the number and the positions of the nonmetallic through holes under the condition of carrying out the nonmetallic through holes; the placement of the positions of the components cannot influence the functional performance and other characteristics of normal components.
Wherein the relationship between the size of the PCB package and the number of non-metallized vias is determined by:
wherein: n is the number of non-metallized through holes, and the unit is one; l (L) max : the length of the longest side is cm.k, a constant, k=1 cm;
s4, determining the relation between the aperture of the non-metallized through hole and the non-metallized perforated material; it is desirable that the non-metallized through holes not have any form of electrical connection to the printed circuit board.
And S5, generating the PCB package with the non-metallized through holes according to the perforation material of the non-metallized through holes. According to the basic requirements and specifications of perforated materials of the non-metallized holes, the non-metallized lines generally have the characteristics of non-conductivity, folding resistance, wear resistance, high temperature resistance, high humidity resistance, difficult introduction of redundancy and the like for specific use environments.
It will be appreciated by those skilled in the art that at the beginning of the build-up of a library of PCB packages for components, it is well established whether a non-metallized opening operation is required for this type of component package. And if the component packaging is required to be perforated, the operation of supplementing the non-metallized through holes is performed on the PCB packaging of the component according to the corresponding non-metallized through hole placement rule. And selecting proper non-metallization method and step according to the position of the non-metallization through hole.
In step S2, when the bonding force of the component pin soldering is insufficient to cope with high-strength mechanical impact, non-metallized through holes are formed; and/or; the components with large-size package bases are arranged in non-metallized through holes, such as components packaged by battery packs, high-stability crystal oscillators, large capacitors, CQFP, DIP and LCC; and/or; when the height of the component exceeds 2 times of the distance between the pins of the chip and the printed circuit board, fixing the non-metallized through holes; and/or; and when the total weight of the component exceeds 2 times of the weight of the lead-out pins of the chip, fixing the non-metallized through holes.
Further, in the step S3, the positions of the non-metallized through holes are respectively set at two sides of the component.
Further, the non-metallized through hole positions are arranged at 1/2 point, 1/3 point and 1/4 point of the two longest sides of the component.
Further, in the step S3, the position of the non-metallized through hole is set according to the shape and size of the PCB package.
Further, in the step S4, the number of non-metallized through holes is set according to the shape and size of the PCB package.
Further, in the step S5, the diameter of the perforated material is determined according to the aperture of the non-metallized through hole; or determining the aperture of the non-metallized through holes according to the diameter of the perforated material.
Further, in the step S5, the diameter of the non-metallized through hole is greater than or equal to 2 times the diameter of the perforated material.
As shown in fig. 2 and 3, based on the above method, in the process of layout and wiring of a PCB, the present invention can ensure that each component requiring opening can be opened normally through the PCB packaging structure with the non-metallized through holes, and the positions of the non-metallized through holes are considered at the beginning of design, thereby avoiding the problem of signal integrity that may be caused. By adding the non-metallized through holes in the PCB packaging, the inspection efficiency of an electronic craftsman can be improved, the error probability and the design difficulty of a layout and wiring designer are reduced, and a series of signal integrity problems caused by hole opening after the design is finished can be effectively avoided, so that the anti-interference capability and the reliability of the product are improved.
The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, it is within the scope of the appended claims and their equivalents to fall within the scope of the invention.
Claims (8)
1. A PCB packaging method of a CQFP chip with a non-metallized through hole is characterized by comprising the following steps:
step S1, establishing a PCB package;
step S2, judging whether to perform nonmetal through hole arrangement;
step S3, determining the number and the positions of the nonmetallic through holes under the condition of carrying out the nonmetallic through holes;
wherein the relationship between the size of the PCB package and the number of non-metallized vias is determined by:
wherein: n is the number of non-metallized through holes, and the unit is one; l (L) max : the length of the longest side is cm.k, a constant, k=1 cm;
s4, determining the relation between the aperture of the non-metallized through hole and the non-metallized perforated material;
s5, generating a PCB package with the non-metallized through holes according to the perforation materials of the non-metallized through holes;
and determining whether nonmetal opening operation is required to be performed on the type of component package at the beginning of the establishment of the PCB package library of the component, if so, performing operation of supplementing nonmetal through holes on the PCB package of the component according to corresponding nonmetal through hole placement rules, and selecting a proper nonmetal step according to the positions of the nonmetal through holes.
2. The method for packaging the PCB with the non-metallized through holes according to claim 1, wherein in the step S2, when the bonding force of the component pin soldering is insufficient to cope with high-strength mechanical impact, the non-metallized through holes are arranged, and/or; the components with the large-size package base are provided with non-metallized through holes and/or; when the height dimension of the component exceeds 2 times of the distance between the chip pins and the printed circuit board, fixing the non-metallized through holes and/or; and when the total weight of the component exceeds 2 times of the weight of the lead-out pins of the chip, fixing the non-metallized through holes.
3. The method for packaging a CQFP chip-self-provided PCB with non-metallized through holes according to claim 1, wherein in step S3, the non-metallized through holes are respectively disposed on two sides of the component.
4. The method of packaging a CQFP chip-self-carrying non-metallized via PCB of claim 3, wherein the non-metallized via locations are disposed at 1/2, 1/3, 1/4 points on the longest sides of the component.
5. The method for packaging a PCB with non-metallized through holes on a CQFP chip according to claim 1, wherein in step S3, the positions of the non-metallized through holes are set according to the shape and size of the PCB package.
6. The method for packaging a PCB with non-metallized through holes on a CQFP chip according to claim 1, wherein in step S4, the number of non-metallized through holes is set according to the shape and size of the PCB package.
7. The method for packaging a PCB with non-metallized through holes according to claim 1, wherein in the step S5, the diameter of the non-metallized through holes is 2 times or more the diameter of the perforated material.
8. The method for packaging the PCB with the non-metallized through holes according to claim 1, wherein in the step S5, the diameter of the perforation material is determined according to the aperture of the non-metallized through holes; or determining the aperture of the non-metallized through holes according to the diameter of the perforated material.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210125707.XA CN114567973B (en) | 2022-02-10 | 2022-02-10 | PCB packaging method for CQFP chip with non-metallized through holes |
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| CN202210125707.XA CN114567973B (en) | 2022-02-10 | 2022-02-10 | PCB packaging method for CQFP chip with non-metallized through holes |
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| CN114567973B true CN114567973B (en) | 2024-04-12 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN206542633U (en) * | 2017-02-17 | 2017-10-03 | 广州广电运通金融电子股份有限公司 | A kind of PCB encapsulating structures |
| US10455690B1 (en) * | 2017-03-28 | 2019-10-22 | Juniper Networks, Inc. | Grid array pattern for crosstalk reduction |
| CN111885849A (en) * | 2020-07-06 | 2020-11-03 | 福建新大陆通信科技股份有限公司 | QFP packaging chip welding method |
| CN111885850A (en) * | 2020-07-16 | 2020-11-03 | 上海无线电设备研究所 | Connecting and assembling method for F-shaped packaged power tube |
| CN212851159U (en) * | 2020-06-02 | 2021-03-30 | 长沙市全博电子科技有限公司 | Large-scale aluminium capacitor package who contains exhaust hole |
| CN113727543A (en) * | 2021-09-02 | 2021-11-30 | 合肥圣达电子科技实业有限公司 | Ceramic metal packaging shell for electronic component and preparation of ceramic material |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100244965B1 (en) * | 1997-08-12 | 2000-02-15 | 윤종용 | Method for manufacturing printed circuit board(PCB) and ball grid array(BGA) package |
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- 2022-02-10 CN CN202210125707.XA patent/CN114567973B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN206542633U (en) * | 2017-02-17 | 2017-10-03 | 广州广电运通金融电子股份有限公司 | A kind of PCB encapsulating structures |
| US10455690B1 (en) * | 2017-03-28 | 2019-10-22 | Juniper Networks, Inc. | Grid array pattern for crosstalk reduction |
| CN212851159U (en) * | 2020-06-02 | 2021-03-30 | 长沙市全博电子科技有限公司 | Large-scale aluminium capacitor package who contains exhaust hole |
| CN111885849A (en) * | 2020-07-06 | 2020-11-03 | 福建新大陆通信科技股份有限公司 | QFP packaging chip welding method |
| CN111885850A (en) * | 2020-07-16 | 2020-11-03 | 上海无线电设备研究所 | Connecting and assembling method for F-shaped packaged power tube |
| CN113727543A (en) * | 2021-09-02 | 2021-11-30 | 合肥圣达电子科技实业有限公司 | Ceramic metal packaging shell for electronic component and preparation of ceramic material |
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