CN114567157B

CN114567157B - Dead time control circuit integrated in dual-channel gate drive chip

Info

Publication number: CN114567157B
Application number: CN202111525066.9A
Authority: CN
Inventors: 柳婧; 傅俊寅; 黄辉; 王伟; 汪之涵
Original assignee: Shenzhen Bronze Sword Technology Co ltd
Current assignee: Shenzhen Bronze Sword Technology Co ltd
Priority date: 2021-12-14
Filing date: 2021-12-14
Publication date: 2024-11-29
Anticipated expiration: 2041-12-14
Also published as: CN114567157A

Abstract

The present application discloses a dead time control circuit integrated in a dual-channel gate driver chip, including a detection delay unit and a logic processing unit. The detection delay unit includes a first input terminal for inputting a first control signal, a second input terminal for inputting a second control signal, and a third input terminal for controlling the dead time mode. The detection delay unit is used to output a dead time mode signal according to different connection modes of the third input terminal, and is used to delay the two-way control signal to output two-way delayed control signals. The logic processing unit performs logic processing on the above signal to output a dual-way drive control signal with different dead time modes; wherein the third input terminal has three connection modes: connected to a power supply, suspended, and grounded through a resistor. The present application can switch different dead time modes by reusing only a single pin, meeting different application scenarios and reducing costs.

Description

Dead time control circuit integrated in dual-channel gate drive chip

Technical Field

The invention relates to the technical field of driving, in particular to a dead time control circuit integrated in a dual-channel grid driving chip.

Background

In order to switch the power transistor quickly and reduce switching power losses, a high current gate drive chip is typically placed between the output of the control device and the gate of the power transistor. The flexible gate drive chip can accommodate a variety of power supplies and motor drives, as well as drive several types of transistors, including silicon carbide MOSFETS. When the two-channel grid driving chip drives the power switch transistors of the half-bridge structure, in order to prevent the two transistors from being simultaneously turned on, a delay is added after one of the power switch transistors is driven to be turned off, so that the other switch transistor is ensured to be turned on after the switch transistor is completely turned off, and the delay is dead time.

The dead time control circuit block diagram in the gate driving chip is shown in fig. 1, wherein the gate driving chip circuit block diagram omits functions of filtering, protection, high voltage isolation, driving and the like, and only shows the working position of the dead time control circuit in the gate driving chip. The signal control device outputs two-way control signals INA and INB to enter a grid driving chip, the dead time control pin carries OUT signal processing on the two-way input control signals IN_a and IN_b IN a dead time control module circuit according to a time control signal DT of an external circuit to obtain two-way output signals OUT_a and OUT_b with expected dead time, and the grid driving chip finally outputs control driving signals OUTA and OUTB to drive a power transistor of a later stage.

However, the two-channel gate driving chip has different requirements on dead time according to different application scenes. In the prior art, a plurality of chip pins are generally designed to provide different mode functions, so that a designed circuit is complicated, the number of the pins of a chip is increased, and the packaging cost is increased.

Disclosure of Invention

In view of this, it is necessary to provide a dead time control circuit integrated in a dual-channel gate driving chip, which can switch different dead time modes by multiplexing only a single pin, so as to satisfy different application scenarios, thereby reducing cost.

The technical scheme provided by the invention for achieving the purpose is as follows:

The dead time control circuit integrated in the dual-channel gate driving chip comprises a detection delay unit (1) and a logic processing unit (2) electrically connected with the detection delay unit (1), wherein the detection delay unit (1) comprises a first input end (11) for inputting a first control signal, a second input end (12) for inputting a second control signal and a third input end (13) for controlling dead time, the detection delay unit (1) is used for outputting corresponding dead time mode signals according to different connection modes of the third input end (13), and is used for carrying out delay processing on the first control signal and the second control signal so as to correspondingly output the first delay control signal and the second delay control signal, and the logic processing unit (2) carries out logic processing on the first control signal, the second control signal, the first delay control signal, the second delay control signal and the dead time mode signal so as to output the first driving control signal and the second driving control signal with different dead time modes, wherein the third input end (13) has three corresponding dead time modes:

when the third input end (13) is connected with a high-voltage power supply of the grid driving chip, the first driving control signal and the second driving control signal do not have dead time, and the first driving control signal and the second driving control signal are allowed to be simultaneously effective;

mode two, when the third input end (13) is suspended, the first driving control signal and the second driving control signal have the fixed dead time with the minimum value;

Mode three, when the third input terminal (13) is grounded through a resistor, the first drive control signal and the second drive control signal have adjustable dead time.

Further, the detection delay unit (1) comprises a detection module (14) and a delay module (15), the third input end (13) provides different analog signals through different connection modes, the detection module (14) detects a dead time mode according to the analog signals and outputs a dead time mode signal to the logic processing unit (2) according to a detection result, and the delay module (15) carries out delay processing on the first control signal and the second control signal when the detection result is a mode three so as to output the first delay control signal and the second delay control signal to the logic processing unit (2).

Further, the detection module comprises a MOS tube (PM 1), a MOS tube (PM 2), a MOS tube (NM 1), a current source (A2), a current source (A3), a NOT gate (INV 1), a NOT gate (INV 2), an AND gate (INV 1) AND a comparator (CMP 1), wherein the grid electrode AND the drain electrode of the MOS tube (PM 1) are connected with the grid electrode of the MOS tube (PM 2), the source electrode of the MOS tube (PM 1) is connected with the source electrode of the MOS tube (PM 2) AND is electrically connected with a high-voltage power supply (VDDH) of a grid driving chip, the drain electrode of the MOS tube (PM 1) is connected with the drain electrode of the MOS tube (NM 1) through the current source (A1), the drain electrode of the MOS tube (PM 2) is grounded through the current source (A2), the drain electrode of the MOS tube (PM 2) is also connected with the input end of the NOT gate (INV 1), the output end of the NOT gate (INV 1) is connected with the first input end of the AND gate (PM 1), the MOS tube (NM 1) is electrically connected with the third input end of the MOS tube (NM 1) through the drain electrode (VDDA 1), the source of the MOS tube (NM 1) is further connected to the inverting input end of the comparator (CMP 1), the source of the MOS tube (NM 1) is further electrically connected with the delay module (15), the non-inverting input end of the comparator (CMP 1) is used for inputting a reference voltage with the voltage being VREF, the output end of the comparator (CMP 1) is electrically connected with the input end of the NOT gate (INV 2), the output end of the NOT gate (INV 2) is electrically connected with the second input end of the AND gate (AND 1), AND the output end of the NOT gate (INV 2) AND the output end of the AND gate (AND 1) are used for outputting dead zone mode signals.

Further, the delay module (15) comprises a MOS tube (NM 2), a MOS tube (NM 3), a current source (A4), a current source (A5), a comparator (CMP 2), a comparator (CMP 3), a capacitor (C1) and a capacitor (C2), wherein a grid electrode of the MOS tube (NM 2) is connected with a first input end (11) and is used for receiving the first control signal, a source electrode of the MOS tube (NM 2) is grounded, the source electrode of the MOS tube (NM 2) is also connected with a drain electrode of the MOS tube (NM 2) through the capacitor (C1), the drain electrode of the MOS tube (NM 2) is electrically connected with a low-voltage power supply (VDDL) through the current source (A4), the drain electrode of the MOS tube (NM 2) is also electrically connected with a non-inverting input end of the comparator (CMP 2), the grid electrode of the MOS tube (NM 3) is connected with a second input end (12) and is used for receiving the second control signal, the source electrode of the MOS tube (NM 3) is grounded, the source electrode of the MOS tube (NM 3) is also connected with the drain electrode of the MOS tube (NM 3) through the capacitor (C2), the drain electrode of the MOS tube (NM 3) is electrically connected with a low-voltage power supply (VDDL) of a grid driving chip through a current source (A5), the drain electrode of the MOS tube (NM 3) is also electrically connected with the non-inverting input end of the comparator (CMP 3), the inverting input end of the comparator (CMP 2) is electrically connected with the inverting input end of the comparator (CMP 3), the output end of the comparator (CMP 2) is used for outputting the first delay control signal, and the output end of the comparator (CMP 3) is used for outputting the second delay control signal.

The dead time control circuit integrated in the dual-channel grid driving chip switches three different dead time modes by multiplexing different external circuit connection modes of one input end (chip pin), is flexible and changeable, reduces the pin number and the packaging pin number of the chip, ensures lower chip packaging cost and simplifies external PCB circuit design.

Drawings

Fig. 1 is a block diagram of a dead time control circuit in a dual channel gate drive chip of the prior art.

Fig. 2 is a schematic circuit diagram of a dead time control circuit integrated in a dual-channel gate driving chip according to a preferred embodiment of the present invention.

FIG. 3 is a block diagram of a preferred embodiment of the detection delay unit of FIG. 2.

FIG. 4 is a circuit diagram of a preferred embodiment of the detection module and the delay module of FIG. 3.

Fig. 5 is a schematic diagram of signal waveforms in the embodiment provided in fig. 4.

Description of the main reference signs

Detection delay unit 1

A first input terminal 11

Second input terminal 12

Third input terminal 13

Detection module 14

Delay module 15

Logic processing unit 2

Capacitance C1, C2

MOS tubes PM1, PM2, NM1, NM2, NM3

Current sources A1, A2, A3, A4, A5

Comparators CMP1, CMP2, CMP3

NOT gate INV1, INV2

AND gate AND1

The invention will be further described in the following detailed description in conjunction with the above-described figures.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

Referring to fig. 2, the present invention provides a dead time control circuit integrated in a dual-channel gate driving chip. The circuit comprises a detection delay unit (1) and a logic processing unit (2) electrically connected with the detection delay unit (1). The detection delay unit (1) comprises a first input end (11) for inputting a first control signal, a second input end (12) for inputting a second control signal and a third input end (13) for controlling dead time. The first control signal and the second control signal are two paths of driving control signals of the two-channel grid driving chip. The detection delay unit (1) is used for outputting dead zone mode signals according to different connection modes of the third input end (13), and is used for carrying out delay processing on the first control signal and the second control signal so as to correspondingly output the first delay control signal and the second delay control signal. The logic processing unit (2) carries out logic processing on the first control signal, the second control signal, the first delay control signal, the second delay control signal and the dead zone mode signal to output a first driving control signal and a second driving control signal with different dead zone time modes, thereby achieving the purpose of controlling the two-channel dead zone time mode of the grid driving chip.

The third input terminal (13) has three connection modes, so that three modes for controlling dead time are realized:

Mode one, when the third input terminal (13) is connected with the high-voltage power supply of the grid driving chip, the first driving control signal and the second driving control signal have no dead time, and the first driving control signal and the second driving control signal are allowed to be simultaneously active (namely can overlap in time);

mode two, when the third input end (13) is suspended, the first driving control signal and the second driving control signal have a fixed dead time with minimum values and are not simultaneously effective (i.e. are not overlapped in time);

Mode three when the third input (13) is grounded through a resistor, the first and second drive control signals have adjustable dead times and are not active simultaneously (i.e., do not overlap in time).

Further, referring to fig. 3, the detection delay unit (1) includes a detection module (14) and a delay module (15), the third input end (13) provides different analog signals through different connection modes, and the detection module (14) detects a dead time mode according to the analog signals, so as to output a dead time mode signal to the logic processing unit (2) according to a detection result. And the delay module (15) delays the first control signal and the second control signal when the detection result is in a mode III so as to output the first delay control signal and the second delay control signal to the logic processing unit (2). In this embodiment, the dead zone mode signal is two digital signals.

Therefore, according to different application scenes of the dual-channel grid driving chip, the dual-channel grid driving chip can multiplex one input end (chip pin), namely three different dead time modes can be switched through different external circuit connection modes, the dual-channel grid driving chip is flexible and changeable, meanwhile, the circuit design is simplified, the pin number and the packaging pin number of the chip are reduced, and the chip packaging cost is lower.

Referring to fig. 4, in the present embodiment, the detection module (14) includes a MOS transistor (PM 1), a MOS transistor (PM 2), a MOS transistor (NM 1), a current source (A2), a current source (A3), a not gate (INV 1), a not gate (INV 2), an and gate (INV 1), and a comparator (CMP 1).

The grid and the drain electrode of the MOS tube (PM 1) are connected with the grid of the MOS tube (PM 2), the source electrode of the MOS tube (PM 1) is connected with the source electrode of the MOS tube (PM 2) and is electrically connected to a high-voltage power supply (VDDH) of a grid driving chip, and the drain electrode of the MOS tube (PM 1) is connected to the drain electrode of the MOS tube (NM 1) through the current source (A1). The drain electrode of the MOS tube (PM 2) is grounded through the current source (A2). The drain electrode of the MOS tube (PM 2) is also connected to the input end of the NOT gate (INV 1), AND the output end of the NOT gate (INV 1) is connected to the first input end of the AND gate (AND 1).

The drain electrode of the MOS tube (NM 1) is electrically connected with the third input end (13), and the third input end (13) is used for inputting a time control signal DT. In this embodiment, the time control signal DT is an analog signal. The grid electrode of the MOS tube (NM 1) is electrically connected with the low-voltage power supply (VDDL) of the grid driving chip, and the source electrode of the MOS tube (NM 1) is electrically connected with the low-voltage power supply (VDDL) of the grid driving chip through a current source (A3). The source electrode of the MOS tube (NM 1) is also connected to the inverting input end of the comparator (CMP 1). The source electrode of the MOS tube (NM 1) is also electrically connected with the delay module (15).

The non-inverting input terminal of the comparator (CMP 1) is used for inputting a reference voltage with VREF. The output end of the comparator (CMP 1) is electrically connected with the input end of the NOT gate (INV 2), the output end of the NOT gate (INV 2) is electrically connected with the second input end of the AND gate (AND 1), the output end of the NOT gate (INV 2) is used for outputting a dead zone mode signal D1, AND the output end of the AND gate (AND 1) is used for outputting a dead zone mode signal D2.

In this embodiment, the delay module (15) includes a MOS transistor (NM 2), a MOS transistor (NM 3), a current source (A4), a current source (A5), a comparator (CMP 2), a comparator (CMP 3), a capacitor (C1), and a capacitor (C2).

The grid electrode of the MOS tube (NM 2) is connected with a first input end (11) and is used for receiving a first control signal IN_a. The source electrode of the MOS tube (NM 2) is grounded, the source electrode of the MOS tube (NM 2) is also connected to the drain electrode of the MOS tube (NM 2) through the capacitor (C1), and the drain electrode of the MOS tube (NM 2) is electrically connected to a low-voltage power supply (VDDL) of the grid driving chip through a current source (A4). The drain electrode of the MOS tube (NM 2) is also electrically connected with the non-inverting input end of the comparator (CMP 2).

The grid of MOS pipe (NM 3) is connected second input (12) for receive second control signal IN_b, the source of MOS pipe (NM 3) ground connection, the source of MOS pipe (NM 3) still is connected IN the drain electrode of MOS pipe (NM 3) through electric capacity (C2), the drain electrode of MOS pipe (NM 3) passes through low-voltage power supply (VDDL) of electric current source (A5) connection IN grid drive chip. The drain electrode of the MOS tube (NM 3) is also electrically connected with the non-inverting input end of the comparator (CMP 3).

An inverting input of the comparator (CMP 2) is electrically connected to an inverting input of the comparator (CMP 3). The output end of the comparator (CMP 2) is used for outputting the first delay control signal D_a, and the output end of the comparator (CMP 3) is used for outputting the second delay control signal D_b.

The high voltage power supply (VDDH) and the low voltage power supply (VDDL) of the gate driving chip supply the power voltages VH and VL, respectively. The current supplied by the current source (A1), the current source (A2) and the current source (A3) are I1, I2 and I3 respectively.

The logic processing unit (2) is a digital logic circuit, and the logic processing unit (2) is configured to perform logic processing on the first control signal in_a, the second control signal in_b, the first delay control signal d_a, the second delay control signal d_b, the dead zone mode signal D1 and the dead zone mode signal D2 to output a first driving control signal out_a and a second driving control signal out_b. In this embodiment, the input and output logic truth table is as follows:

TABLE I truth table

In the present embodiment, the logic value of the valid signal is 1, the logic value of the invalid signal is 0, and in other embodiments, the logic value of the valid signal is 0, and the logic value of the invalid signal is 1.

Therefore, IN the mode one state provided IN the present embodiment, the signals D1 and D2 are both 1, and the signal out_a=in_a and out_b=in_b.

IN the mode two state, the signal D1 is 0 and the signal D2 is 1, and if in_a and in_b are both 1, the signals out_a and out_b are both 0, otherwise, the signals out_a=in_a and out_b=in_b.

IN the mode three state, the signals D1 and D2 are both 0, and if d_a is 0, the signal out_b is 0, otherwise the signal out_b=in_b, and if d_b is 0, the signal out_a is 0, otherwise the signal out_a=in_a.

The circuit principle provided by the present embodiment is described in detail below:

When the third input end (13), i.e. the input end of the time control signal DT, is connected with the high voltage power supply (VDDH) of the grid driving chip, the grid electrode of the MOS tube (NM 1) is connected with the low voltage power supply (VDDL), the source voltage VDT of the MOS tube (NM 1) is clamped below VL to protect the low voltage device of the later stage, at the moment, VDT is more than VREF, and the dead zone mode signal D2 output by the NOT gate (INV 2) is logic level 1. The two ends of the current source (A1) lose the voltage difference, no current flows, and the current mirror formed by the MOS tube (PM 1) and the MOS tube (PM 2) cannot form mirror current, so that the current source (A2) pulls the input end of the inverter (INV 1) to the ground. The dead zone mode signal D1 output by the AND gate (AND 1) is at logic level 1 at this time.

When the third input end (13) is suspended, the current source (A3) pulls up the source voltage VDT of the MOS transistor (NM 1) to be close to VDDL, at this time VDT > VREF, and the dead zone mode signal D2 output by the not gate (INV 2) is a logic level 1. The current mirror composed of the MOS tube (PM 1) AND the MOS tube (PM 2) mirrors the current I1 provided by the current source (A1), at the moment, I1> I2, the input end of the inverter (INV 1) is pulled up, AND the dead zone mode signal D1 output by the AND gate (AND 1) is a logic level 0.

When the third input end (13) is grounded through a resistor (the resistance value is R), the current source (A1) and the current source (A3) act together to form a voltage drop on the resistor, at this time, the source voltage vdt=r of the MOS transistor (NM 1) (i1+i3), VDT < VREF, and the dead zone mode signal D2 output by the not gate (INV 2) is a logic level 0. The situation at the input end of the inverter (INV 1) is the same as when floating, AND the dead zone mode signal D1 output by the AND gate (AND 1) is logic level 0.

In the present embodiment, the dead time control mode can be determined by the dead time mode signal D1 and the dead time mode signal D2, specifically, as shown in the following table two:

TABLE II dead time control mode correspondence table

IN the delay module (15), when the logic level of the first control signal in_a or the second control signal in_b is 1, the MOS transistor (NM 2) or the MOS transistor (NM 3) is turned on, and at this time, the non-inverting terminal of the comparator (CMP 2) or the comparator (CMP 3) is pulled to the ground, and the logic level of the first delay control signal d_a or the second delay control signal d_b is output as 0.

When the logic level of the first control signal in_a or the second control signal in_b is 0, the MOS tube (NM 2) or the MOS tube (NM 3) is turned off, the current source (I4) charges the capacitor (C1) or the current source (I5) charges the capacitor (C2), and the comparator (CMP 2) or the comparator (CMP 3) generates a turn-off delay flip signal, so that the delay time is longer when the voltage VDT of the inverting terminal is larger. The time from the logic level of the first control signal in_a or the second control signal in_b being 0 to the logic level of the first delay control signal d_a or the second delay control signal d_b being 1 is superimposed on the input control signal by the latter logic processing unit (2), and is the drive control signal having dead time.

Therefore, when the resistance R of the resistor connected to the third input terminal (13) is larger, the dead time is longer, wherein R < VREF/(I1+I3), when the third input terminal (13) is connected to the high voltage source (VDDH) and floating, the voltage of the source voltage VDT of the MOS transistor (NM 1) (the voltages of the inverting terminals of the two comparators) is similar to VDDL, the voltages of the non-inverting terminals of the comparator (CMP 2) and the comparator (CMP 3) cannot be larger than the non-inverting terminal, and the logic levels of the first delay control signal D_a and the second delay control signal D_b are kept to be 0.

In this way, the logic processing of the logic processing unit (2) at the later stage (refer to table 1) outputs the required first driving control signal out_a and the second driving control signal out_b (refer to fig. 5), when in the mode, the output control signal has no dead time and allows the two-way output signal to be valid at the same time, when in the mode two, the output control signal has no dead time to be valid at the same time, the dead time is fixed to be the minimum value (the dead time length at the moment is the signal transmission delay and is not delayed otherwise), when in the mode three, the length of the dead time can be adjusted by adjusting the resistance value of the external access resistor, the larger the resistance value is, the longer the dead time is, and the output signal is not valid at the same time.

The dead time control circuit integrated on the dual-channel grid driving chip judges a dead time control mode through time control signals DT corresponding to different external connection modes of a third input end (13) on the detection module (14) and outputs dead time mode signals according to judging results, and the dead time control circuit is further provided with a delay module (15) for carrying out delay processing on two paths of control signals according to the dead time mode signals so as to output delay control signals. Then, through logic processing of the logic processing unit (2), dead time is added for the two paths of control signals, and thus a control signal with the dead time is output. Therefore, only a single pin is multiplexed to switch different dead time modes and dead time lengths so as to meet different application scenes, and therefore cost is reduced.

The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.

Claims

1. The dead time control circuit integrated in the dual-channel gate driving chip is characterized by comprising a detection delay unit (1) and a logic processing unit (2) electrically connected with the detection delay unit (1), wherein the detection delay unit (1) comprises a first input end (11) for inputting a first control signal, a second input end (12) for inputting a second control signal and a third input end (13) for controlling dead time, the detection delay unit (1) is used for outputting corresponding dead time mode signals according to different connection modes of the third input end (13) and is used for carrying out delay processing on the first control signal and the second control signal so as to correspondingly output the first delay control signal and the second delay control signal, the logic processing unit (2) carries out logic processing on the first control signal, the second control signal, the first delay control signal, the second delay control signal and the dead time mode signal so as to output first driving control signals and second driving control signals with different time modes, and the third driving mode has dead time corresponding to the third driving mode (13):

2. The dead time control circuit integrated on a dual-channel gate driving chip according to claim 1, wherein the detection delay unit (1) comprises a detection module (14) and a delay module (15), the third input end (13) provides different analog signals through different connection modes, the detection module (14) detects a dead time mode according to the analog signals and outputs a dead time mode signal to the logic processing unit (2) according to a detection result, and the delay module (15) delays the first control signal and the second control signal when the detection result is a mode three so as to output the first delay control signal and the second delay control signal to the logic processing unit (2).

3. The dead time control circuit integrated on a dual-channel gate driving chip according to claim 2, wherein the detection block comprises a MOS transistor PM1, a MOS transistor PM2, a MOS transistor PM1, a current source A2, a current source A3, a non-gate INV1, an AND gate 1, AND a comparator CMP1, the gate AND drain of the MOS transistor PM1 are connected to the gate of the MOS transistor PM2, the source of the MOS transistor PM1 is connected to the source of the MOS transistor PM2, AND is electrically connected to the high voltage supply VDDH of the gate driving chip, the drain of the MOS transistor PM1 is connected to the drain of the MOS transistor NM1 through the current source A1, the drain of the MOS transistor PM2 is connected to the ground through the current source A2, the drain of the MOS transistor PM2 is also connected to the input of the non-gate 1, the output of the non-gate INV1 is connected to the first input terminal of the AND gate AND1, the drain of the MOS transistor PM1 is connected to the third input terminal (13 is connected to the voltage supply terminal of the third input terminal AND the gate) is connected to the voltage supply circuit, the output terminal of the non-gate AND input terminal of the MOS transistor PM1 is connected to the voltage comparator CMP1, AND the output terminal is connected to the voltage-delay circuit is connected to the input terminal of the non-gate 1 is connected to the input terminal of the non-gate voltage gate 1 through the current source circuit 2 through the current source A2, the output terminal of the non-gate AND the output terminal of the MOS transistor PM1 is connected to the input terminal of the voltage is connected to the input terminal of the voltage terminal 13.

4. The dead time control circuit integrated on a dual-channel gate driving chip as set forth in claim 3, wherein the delay module (15) comprises a MOS transistor NM2, a MOS transistor NM3, a current source A4, a current source A5, a comparator CMP2, a comparator CMP3, a capacitor C1 and a capacitor C2, a gate of the MOS transistor NM2 is connected to a first input terminal (11) for receiving the first control signal, a source of the MOS transistor NM2 is grounded, a source of the MOS transistor NM2 is further connected to a drain of the MOS transistor NM2 through the capacitor C1, a drain of the MOS transistor NM2 is further connected to a low voltage power supply VDDL through the current source A4, a drain of the MOS transistor NM2 is further connected to an in-phase input terminal of the comparator CMP2, a gate of the MOS transistor NM3 is connected to a second input terminal (12) for receiving the second control signal, a source of the MOS transistor NM3 is further connected to the drain of the capacitor C2, a source of the MOS transistor NM3 is further connected to the drain of the transistor NM3 through the capacitor C1, a drain of the MOS transistor NM3 is further connected to an in-phase-inverted voltage input terminal of the comparator CMP3, and the output signal is further connected to the in-phase-inverted voltage input terminal of the comparator CMP2, and the comparator CMP3 is further connected to the voltage-phase input terminal of the voltage comparator CMP 2.