CN114566556A - Processing method of semiconductor substrate layer, solar cell and preparation method of solar cell - Google Patents

Abstract

The invention provides a processing method of a semiconductor substrate layer, a solar cell and a preparation method thereof. The processing method of the semiconductor substrate layer includes: providing an initial semiconductor substrate layer; performing laser spot array scanning on the surface of the initial semiconductor substrate layer to form a plurality of uniformly arranged micro-damage points; and taking a number of the micro-damage points as At the raising point, the initial semiconductor substrate layer is subjected to a texturing process to form the semiconductor substrate layer. In the present invention, a large number of uniformly arranged micro-damage points are obtained by scanning the surface of the initial semiconductor substrate layer with a laser point array, which can be used as uniformly distributed raised points in the texturing process, which is conducive to the formation of small-sized and uniformly arranged micro-damage points. Anti-reflection structure, thereby reducing the reflectivity of the semiconductor substrate layer.

Description

A kind of processing method of semiconductor substrate layer, solar cell and preparation method thereof

technical field

The invention relates to the technical field of solar cells, in particular to a method for processing a semiconductor substrate layer, a solar cell and a preparation method thereof.

Background technique

At present, in the production process of crystalline silicon solar cells, in order to obtain higher photoelectric conversion efficiency, in addition to the high quality of the crystalline silicon material itself and its ability to form an ideal P-N junction and other inherent characteristics, it is also required that the cell surface has a good surface. Light trapping effect. The light trapping effect is usually achieved by surface texture, that is, an important process in the production of cell sheets - texturing. It achieves the purpose of improving the efficiency of the solar cell by increasing the light absorption of the cell, reducing the surface reflectivity, and increasing the short-circuit current of the solar cell.

Due to the excellent passivation performance of amorphous silicon, the open circuit voltage of heterojunction cells can reach more than 740mV, which is much higher than that of traditional crystalline silicon cells, and has broad application prospects. Since the thickness of the amorphous silicon film is only about 10 nm, and the size of the textured pyramid texture in the prior art is in the micrometer level, the size and uniformity of the textured pyramid have a great influence on the amorphous silicon film layer, and also Affects texturing reflectivity. At present, the textured reflectivity of the semiconductor substrate layer of the high-efficiency battery is basically 10%-12%, and the size of the pyramid is 1 μm-5 μm. Therefore, for heterojunction cells, smaller pyramid texture size and more uniform pyramid texture distribution are very important to enhance the passivation of amorphous silicon films and reduce texturing reflectivity.

SUMMARY OF THE INVENTION

Therefore, the technical problem to be solved by the present invention is to overcome the defect of the high reflectivity of the semiconductor substrate layer in the existing texturing technology, and further provide a processing method of the semiconductor substrate layer, a solar cell and a preparation method thereof.

The present invention provides a method for processing a semiconductor substrate layer, comprising: providing an initial semiconductor substrate layer; performing laser spot array scanning on the surface of the initial semiconductor substrate layer to form a number of uniformly arranged micro-damage points; The micro-damage points are raised points, and the initial semiconductor substrate layer is subjected to a texturing treatment to form the semiconductor substrate layer.

Optionally, the spot diameter of the laser used in the laser spot array scanning is 0.1 μm-1 μm, and the spot spacing is 1 μm-3 μm.

Optionally, the laser wavelength used for the laser spot array scanning is 500nm-1064nm.

Optionally, the etching depth scanned by the laser spot array is less than or equal to 0.5 μm.

Optionally, before performing the laser spot array scanning, a pretreatment process of removing the damaged layer is performed on the surface of the initial semiconductor substrate layer.

Optionally, the pretreatment process includes acid etching or alkali etching.

Optionally, the acid etching adopts a mixed solution of hydrofluoric acid solution and nitric acid solution.

Optionally, the volume ratio of the hydrofluoric acid solution and the nitric acid solution is 1:3-1:9.

Optionally, the concentration of hydrofluoric acid in the hydrofluoric acid solution is 45wt%-50wt%, and the concentration of nitric acid in the nitric acid solution is 60wt%-70wt%.

Optionally, the alkali corrosion adopts sodium hydroxide solution or potassium hydroxide solution.

Optionally, the concentration of the sodium hydroxide solution is 2wt%-15wt%, and the concentration of the potassium hydroxide solution is 2wt%-15wt%.

Optionally, the method further includes: removing the oxide layer formed on the surface of the initial semiconductor substrate layer after scanning the laser spot array and before performing the texturing treatment on the initial semiconductor substrate layer.

Optionally, in the step of removing the oxide layer on the surface of the initial semiconductor substrate layer, a hydrofluoric acid solution with a concentration of 1 wt % to 5 wt % is used for 5 seconds to 20 seconds.

Optionally, the texturing liquid used in the texturing treatment is an alkaline solution.

Optionally, the alkaline solution includes sodium hydroxide solution or potassium hydroxide solution.

Optionally, the concentration of the alkaline solution is 1wt%-5wt%.

Optionally, the temperature used in the texturing treatment is 80°C-90°C, and the time is 200 seconds-500 seconds.

Optionally, after the initial semiconductor substrate layer is subjected to the texturing treatment, the surface of the semiconductor substrate layer is cleaned.

The present invention also provides a method for preparing a solar cell, comprising: forming a semiconductor substrate layer, which is formed by the processing method for the semiconductor substrate layer of the present invention.

Optionally, a first intrinsic passivation layer is formed on one side surface of the semiconductor substrate layer; a second intrinsic passivation layer is formed on the other side surface of the semiconductor substrate layer; A first doped semiconductor layer is formed on a side surface of the passivation layer away from the semiconductor substrate layer; a second doped semiconductor layer is formed on a side surface of the second intrinsic passivation layer away from the semiconductor substrate layer.

The present invention also provides a solar cell, comprising a semiconductor substrate layer, and at least one side of the semiconductor substrate layer has several anti-reflection structures arranged in an array and uniformly distributed.

Optionally, the projected area of each of the anti-reflection structures on the semiconductor substrate layer is less than or equal to 9 μm ² .

Optionally, the height of the anti-reflection structure is 0.5 μm-3 μm.

Optionally, the height difference between the bottom surfaces of any two of the anti-reflection structures is less than or equal to 1 μm.

Optionally, the shape of the anti-reflection structure is a pyramid.

The technical scheme of the present invention has the following beneficial effects:

1. In the processing method of the semiconductor substrate layer provided by the technical solution of the present invention, an initial semiconductor substrate layer is provided first; laser spot array scanning is performed on the surface of the initial semiconductor substrate layer to form several micro-damage points evenly arranged; After the laser spot array is scanned, the oxide layer formed on the surface of the initial semiconductor substrate layer is removed; and the initial semiconductor substrate layer is subjected to a texturing treatment with a number of the micro-damage points as raised points to form the semiconductor substrate layer. substrate layer. A large number of uniformly arranged micro-damage points are obtained by scanning the surface of the initial semiconductor substrate layer with a laser point array, which can be used as uniformly distributed raised points in the texturing process. In the early stage of texture formation, the initial semiconductor substrate layer has uniform nucleation and high nucleation density, which is conducive to forming an anti-reflection structure with uniform size and small size, thereby reducing the reflectivity of the semiconductor substrate layer.

2. Further, the time for performing the texturing treatment on the initial semiconductor substrate layer is 200 seconds to 500 seconds. The anti-reflection structure with small size, uniform growth and close arrangement can be obtained by controlling the texturing time on the basis of using the laser spot array scanning to form the evenly arranged raising points. If the texturing time is too short, the coverage of the anti-reflection structure will be low, and if the texturing time is too long, the growth of the anti-reflection structure will be too large, both of which are not conducive to reducing the reflectivity of the semiconductor substrate layer.

Description of drawings

In order to illustrate the specific embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the specific embodiments or the prior art. Obviously, the accompanying drawings in the following description The drawings are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.

1 is a schematic flowchart of a method for processing a semiconductor substrate layer in an embodiment of the present invention;

FIG. 2 to FIG. 6 are schematic structural diagrams of the semiconductor substrate layer in the processing process according to the embodiment of the present invention.

Attached identification:

10-initial semiconductor substrate layer; 11-oxide layer; 12-micro-damage point; 13-semiconductor substrate layer; 14-anti-reflection structure.

Detailed ways

The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation or a specific orientation. construction and operation, and therefore should not be construed as limiting the invention. Furthermore, the terms "first", "second", and "third" are used for descriptive purposes only and should not be construed to indicate or imply relative importance.

In the description of the present invention, it should be noted that the terms "installed", "connected" and "connected" should be understood in a broad sense, unless otherwise expressly specified and limited, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be internal communication between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood in specific situations.

In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

Example 1

This embodiment provides a method for processing a semiconductor substrate layer, as shown in FIG. 1 , including the following steps:

Step S1: providing an initial semiconductor substrate layer;

Step S2: performing laser spot array scanning on the surface of the initial semiconductor substrate layer to form evenly arranged several micro-damage spots;

Step S3: after scanning the laser spot array, remove the oxide layer formed on the surface of the initial semiconductor substrate layer;

Step S4 : taking several of the micro-damage points as raising points, performing a texturing process on the initial semiconductor substrate layer to form the semiconductor substrate layer.

The following describes in detail with reference to FIGS. 2 to 6 .

Referring to Figure 2, an initial semiconductor substrate layer 10 is provided.

The material of the initial semiconductor substrate layer 10 includes single crystal silicon. In other embodiments, the material of the initial semiconductor substrate layer 10 is other semiconductor materials, such as polysilicon, germanium or silicon germanium. The material of the initial semiconductor substrate layer 10 may also be other semiconductor materials, which are not limited here.

In this embodiment, the surface of the initial semiconductor substrate layer 10 has a damaged area, and the damaged area is caused during the process of cutting the silicon rod raw material to form the initial semiconductor substrate layer 10 . In a specific embodiment, both the front side and the back side of the initial semiconductor substrate layer 10 have damaged regions.

In this embodiment, the surface of the initial semiconductor substrate layer 10 is first subjected to a pretreatment process of removing a damaged layer, where the damaged layer includes surface micro-cracks caused by dicing of silicon wafers. The purpose of the pretreatment process on the surface is to remove the damaged area. Since the initial semiconductor substrate layer 10 has a post-saw damage layer of about 10 μm-20 μm on the surface during the cutting process, it has a great impact on the texturing. If the damaged layer is removed, Insufficient may leave impurities left in the cutting process, and the anti-reflection structure 14 will be difficult to appear due to the damaged layer during texturing, and will continue to damage the surface of the initial semiconductor substrate layer 10 in the subsequent process, resulting in The various parameters of the battery do not meet the requirements, so they must be removed before texturing.

In one embodiment, the pretreatment process for removing the damaged layer on the surface of the initial semiconductor substrate layer 10 includes acid etching or alkali etching.

In one embodiment, the acid etching adopts a mixed solution of hydrofluoric acid solution and nitric acid solution, and the volume ratio of the hydrofluoric acid solution and the nitric acid solution is 1:3-1:9, such as 1:3, 1:6 or 1:9. The concentration of hydrofluoric acid in the hydrofluoric acid solution is 45wt%-50wt%, such as 45wt%, 48wt% or 50wt%. The concentration of nitric acid in the nitric acid solution is 60wt%-70wt%, such as 65wt%, 69wt% or 70wt%.

In one embodiment, the alkali corrosion adopts sodium hydroxide solution or potassium hydroxide solution. The concentration of the sodium hydroxide solution is 2wt%-15wt%, such as 2wt%, 5wt%, 10wt% or 15wt%; the concentration of the potassium hydroxide solution is 2wt%-15wt%, such as 2wt%, 5wt%, 10wt% or 15wt%. When choosing to corrode under the condition of high concentration sodium hydroxide solution or potassium hydroxide solution, the corrosion rate can reach 6μm/min-10μm/min. Since the corrosion rate is too fast at this time, attention should be paid to removing the damaged layer on the basis of The etching time is minimized to prevent the initial semiconductor substrate layer 10 from being over-etched.

In this embodiment, the initial semiconductor substrate layer 10 from which the damaged layer is removed is washed with water and then dried to keep the surface of the silicon wafer clean and dry.

Referring to FIG. 3 , laser spot array scanning is performed on the surface of the initial semiconductor substrate layer 10 to form a plurality of the micro-damage spots 12 that are evenly arranged. In order to obtain a textured surface with a uniform size of the anti-reflection structure, the laser point array scanning needs to be uniformly arranged, otherwise random pyramids will be formed at the non-scanning points, resulting in relative randomness in size and size.

The shaded area in FIG. 3 shows the oxide layer 11 formed on the surface of the initial semiconductor substrate layer 10 due to laser spot array scanning. The oxide layer 11 is an oxide layer formed by oxidizing the silicon semiconductor substrate during air exposure.

In this embodiment, the laser wavelength used in the laser spot array scanning is 500 nm-1064 nm, for example, 532 nm, 660 nm, 808 nm or 1064 nm.

In this embodiment, the spot diameter of the laser spot array scanning is 0.1 μm-1 μm, such as 0.1 μm, 0.3 μm, 0.5 μm or 1 μm, and the spot spacing is 1 μm-3 μm, such as 1 μm, 1.5 μm, 2 μm or 3 μm. In this embodiment, the purpose of the laser spot array scanning is to form the micro-damaged spots 12 as the raising spots for texturing, so the spot spacing of the laser spot array scanning should not be too large, which is more conducive to the formation of an anti-reflection structure with a smaller size 14.

In this embodiment, a large number of uniformly distributed micro-damage points 12 are obtained by performing laser point array scanning on the surface of the initial semiconductor substrate layer 10, which can be used as uniformly distributed raised points in the texturing process. In this way, in the early stage of texture formation, the surface of the initial semiconductor substrate layer 10 is uniformly nucleated and has a high nucleation density, which is conducive to forming the textured surface of the anti-reflection structure 14 with uniform size, thereby reducing the reflectivity of the semiconductor substrate layer 13 . On this basis, by adjusting the laser wavelength, spot diameter, spot spacing, and etching depth of the laser spot array scanning, the density of raised points can be effectively increased, thereby reducing the texturing time and improving the performance of the textured surface.

Referring to FIG. 4 , after the laser spot array scanning is performed, the oxide layer 11 formed on the surface of the initial semiconductor substrate layer 10 is removed.

In this embodiment, the surface of the initial semiconductor substrate layer 10 will be partially oxidized when heated during the laser spot array scanning process. Preferably, the oxide layer 11 formed on the surface of the initial semiconductor substrate layer 10 can be removed by pickling.

In one embodiment, in the step of removing the oxide layer 11 formed on the surface of the initial semiconductor substrate layer 10, a hydrofluoric acid solution with a concentration of 1wt%-5wt% is used to clean the surface of the initial semiconductor substrate layer 10 for 5 seconds-20 seconds, the concentration of the hydrofluoric acid solution is eg 1 wt %, 2 wt %, 3 wt % or 5 wt %, and the cleaning time is eg 5 seconds, 10 seconds or 20 seconds.

Referring to FIGS. 5 and 6 , the initial semiconductor substrate layer 10 is subjected to a texturing process by using a plurality of the micro-damage points 12 as raised points to form the semiconductor substrate layer 13 .

In this embodiment, the texturing liquid used in the texturing treatment is an alkaline solution. In one embodiment, the alkaline solution includes sodium hydroxide solution or potassium hydroxide solution. The concentration of the sodium hydroxide solution is 1wt%-5wt%, such as 1wt%, 2wt%, 3wt% or 5wt%; the concentration of the potassium hydroxide solution is 1wt%-5wt%, such as 1wt%, 2wt%, 3wt% or 5wt%. Since the materials of the initial semiconductor substrate layer 10 with different crystallographic orientations are etched at different rates in the alkaline solution, the difference can be used to etch the materials with the anti-reflection structures 14 on the different crystallographic orientations of the initial semiconductor substrate layer 10 material. Suede. The corrosivity of texturing liquid varies significantly with the concentration of sodium hydroxide or potassium hydroxide. If the concentration of the alkaline texturing solution is high, the chemical reaction between the alkaline texturing solution and the initial semiconductor substrate layer 10 will be accelerated, and the volume of the anti-reflection structure 14 will be larger after the same reaction time. When the concentration of the alkaline texturing solution exceeds a certain threshold, the corrosion strength of the solution is too strong, the anisotropy factor becomes smaller, and the texture becomes worse and worse until a similar "polishing" effect occurs. Therefore, if the concentration of the alkaline solution used in texturing is too small, the corrosion rate will be too slow; if the concentration of the alkaline solution used is too large, the corrosion will be too strong. Reflective suede.

In one embodiment, the temperature conditions for the texturing treatment on the initial semiconductor substrate layer 10 are 80° C.-90° C., and the working time is 200 seconds-500 seconds. On the basis of using laser dot array scanning to form evenly arranged raised dots, by controlling the texturing time, a small size (1 μm-2 μm), uniform growth, and closely arranged anti-reflection structure 14 can be obtained. If the texturing time is too short, the texture coverage is low; if the texturing time is too long, the anti-reflection structure 14 expands and merges outwards, and the volume gradually expands, which reduces the efficiency of the anti-reflection structure 14 . Neither is beneficial to reduce the reflectivity of the semiconductor substrate layer 13 .

In one embodiment, the height of the anti-reflection structure 14 is 0.5 μm-3 μm. The height of the anti-reflection structure 14 is small, which is favorable for forming the anti-reflection structure 14 with small size and high density.

In one embodiment, the projected area of each of the anti-reflection structures 14 on the semiconductor substrate layer 13 is less than or equal to 9 μm ² .

In one embodiment, the height difference between the bottom surfaces of any two anti-reflection structures 14 is less than or equal to 1 μm. The height difference of the bottom surface of the anti-reflection structure 14 reflects the uniformity of the surface of the semiconductor substrate layer 13 , and a smaller height difference of the bottom surface of the anti-reflection structure 14 indicates that the uniformity of the surface of the semiconductor substrate layer 13 is higher. it is good.

In one embodiment, the shape of the anti-reflection structure 14 is a pyramid, and uniform and relatively small-sized pyramids are beneficial to reducing the reflectivity of the textured surface.

In a specific embodiment, in the step of performing the texturing treatment on the initial semiconductor substrate layer 10, a potassium hydroxide solution with a concentration of 1wt%-3wt% is used, such as 2wt%, and the temperature is 84°C-86°C, such as 85 ℃; working time is 340 seconds to 360 seconds, such as 350 seconds, to obtain the semiconductor substrate layer 13 having the pyramid-shaped anti-reflection structure 14, the height of the pyramid-shaped anti-reflection structure 14 is 1 μm-2 μm, the reflection of the semiconductor substrate layer 13 The rate is 8%-10%, eg 9.5%. In the texturing process, corrosion generally starts from the damaged area first. The uniformly arranged micro-damage points 12 formed by the laser point array scanning can make the corrosion preferentially start from the preset position, which reduces the randomness of corrosion and is more conducive to obtaining A uniform anti-reflection structure 14 is grown. After the corrosion starts, bubbles will be generated on the surface of the initial semiconductor substrate layer 10. After the bubbles expand to a certain extent, the buoyancy is greater than the surface adhesion, and the bubbles will be separated from the surface of the initial semiconductor substrate layer 10. The surface of the semiconductor substrate layer 10 is contacted and corroded. Repeatedly, the surface of the initial semiconductor substrate layer 10 is corroded layer by layer, and a surface corrosion morphology related to the surface crystal orientation, texturing liquid concentration, texturing liquid viscosity, temperature, corrosion time and other factors is formed. For example: the higher the solubility of the alkali in the aforementioned texturing liquid concentration, the weaker the anisotropy; the higher the viscosity of the texturing liquid viscosity, the more unfavorable for the reaction to proceed; the temperature determines the rate of the reaction, and at the same time has an enhanced effect on the anisotropy Effect; the length of corrosion time determines the degree of corrosion. Similarly, whether it is a P-type semiconductor substrate layer or an N-type semiconductor substrate layer, the formation structure and formation mechanism of the surface crystal orientation are the same.

In a specific embodiment, single crystal silicon is used as the initial semiconductor substrate layer 10, and the dangling bond density of each crystal plane of the single crystal silicon is different, so that the etching of the single crystal silicon wafer in an alkaline solution produces anisotropy. From the perspective of the normal direction of the crystal plane in the microstructure of the material, due to the different areal densities of the three crystal planes (100), (110) and (111) of single crystal silicon, the texturing liquid engraves the three crystal planes. The etching speed is different, the etching speed of the (100) crystal plane is the largest, and the etching of the (111) crystal plane is the smallest, resulting in a small amount of etching (111) crystal plane is easily exposed on the surface, thereby forming a pyramid-shaped anti-reflection structure 14 .

In the prior art, the formation of the pyramid texture of the semiconductor substrate layer depends on and only depends on the state of the additive and the liquid medicine, and the position and size of the pyramid formed are relatively random. In this embodiment, a large number of uniformly arranged micro-damage points are obtained by scanning the surface of the initial semiconductor substrate layer with a laser point array as the raising points in the texturing process. A smaller pyramid texture surface with more uniform position and more consistent size is obtained, which reduces the reflectivity of the semiconductor substrate layer.

Example 2

The present embodiment provides a method for preparing a solar cell, comprising the following steps:

The semiconductor substrate layer 13 is formed by using the processing method of the semiconductor substrate layer 13 in Embodiment 1 of the present invention;

In this embodiment, taking the preparation method of a heterojunction solar cell as an example, the preparation method of the solar cell further includes:

A first intrinsic passivation layer is formed on one side surface of the semiconductor substrate layer 13; a second intrinsic passivation layer is formed on the other side surface of the semiconductor substrate layer 13;

A first doped semiconductor layer is formed on the surface of the first intrinsic passivation layer facing away from the semiconductor substrate layer 13 ; a surface of the second intrinsic passivation layer facing away from the semiconductor substrate layer 13 is formed forming a second doped semiconductor layer;

A first transparent conductive oxide layer is formed on the surface of the first doped semiconductor layer away from the semiconductor substrate layer 13 ; a first transparent conductive oxide layer is formed on the surface of the second doped semiconductor layer away from the semiconductor substrate layer 13 . Two transparent conductive oxide layers;

A first gate electrode is formed on the surface of the first transparent conductive oxide layer away from the semiconductor substrate layer 13 ; a second gate electrode is formed on the surface of the second transparent conductive oxide layer away from the semiconductor substrate layer 13 electrode.

Example 3

This embodiment also provides a solar cell, which includes a semiconductor substrate layer 13, and at least one side of the semiconductor substrate layer 13 has a plurality of anti-reflection structures 14 arranged in an array.

In one embodiment, the projected area of each of the anti-reflection structures 14 on the semiconductor substrate layer 13 is less than or equal to 9 μm ² , for example, 6 μm ² , 7 μm ² or 8 μm ² .

In one embodiment, the height of the anti-reflection structure 14 is 0.5 μm-3 μm.

In one embodiment, the height difference between the bottom surfaces of any two anti-reflection structures 14 is less than or equal to 1 μm. The height difference of the bottom surface of the anti-reflection structure 14 reflects the uniformity of the surface of the semiconductor substrate layer 13 , and a smaller height difference of the bottom surface of the anti-reflection structure 14 indicates that the uniformity of the surface of the semiconductor substrate layer 13 is higher. it is good.

In one embodiment, the shape of the anti-reflection structure 14 is a pyramid. The pyramid-shaped anti-reflection structures 14 with small size (height 1 μm-2 μm), uniform position, and close arrangement are beneficial to reduce the reflectivity of the semiconductor substrate layer 13 .

It should be understood here that the reason why the texture performance of large-sized pyramids (height greater than 5 μm) is inferior to that of small-sized pyramids is that the large-sized pyramids have higher reflectivity, which is not conducive to light trapping on the textured surfaces. Therefore, in this embodiment, the anti-reflection structure 14 of small size is selected to reduce the reflectivity after texturing.

In this embodiment, the solar cell further includes: a first intrinsic passivation layer located on one side surface of the semiconductor substrate layer 13 ; a second intrinsic passivation layer located on the other side surface of the semiconductor substrate layer 13 ; the first doped semiconductor layer located on the side surface of the first intrinsic passivation layer away from the semiconductor substrate layer 13; located on the side of the second intrinsic passivation layer away from the semiconductor substrate layer 13 the second doped semiconductor layer on the surface; the first transparent conductive oxide layer on the surface of the first doped semiconductor layer away from the semiconductor substrate layer 13; the second doped semiconductor layer away from the semiconductor a second transparent conductive oxide layer on one side surface of the substrate layer 13; a first gate electrode on the side surface of the first transparent conductive oxide layer away from the semiconductor substrate layer 13; on the second transparent conductive oxide layer A second gate electrode facing away from the side surface of the semiconductor substrate layer 13 .

Obviously, the above-mentioned embodiments are only examples for clear description, and are not intended to limit the implementation manner. For those of ordinary skill in the art, changes or modifications in other different forms can also be made on the basis of the above description. There is no need and cannot be exhaustive of all implementations here. And the obvious changes or changes derived from this are still within the protection scope of the present invention.

Claims (10)

1. A processing method for a semiconductor substrate layer, comprising the step of providing an initial semiconductor substrate layer, characterized in that, further comprising: Perform laser spot array scanning on the surface of the initial semiconductor substrate layer to form several micro-damage spots evenly arranged; Taking several of the micro-damage points as the raising points, the initial semiconductor substrate layer is subjected to a texturing treatment to form the semiconductor substrate layer. 2 . The method for processing a semiconductor substrate layer according to claim 1 , wherein the laser spot diameter used in the laser spot array scanning is 0.1 μm-1 μm, and the spot spacing is 1 μm-3 μm; 3 . Preferably, the laser wavelength used in the laser spot array scanning is 500nm-1064nm. 3 . The method for processing a semiconductor substrate layer according to claim 1 , wherein the etching depth of the laser spot array scanning is less than or equal to 0.5 μm. 4 . 4. The method for processing a semiconductor substrate layer according to claim 1, further comprising: performing a pretreatment process of removing a damaged layer on the surface of the initial semiconductor substrate layer before performing the laser spot array scanning; Preferably, the pretreatment process includes acid etching or alkali etching; Preferably, the acid corrosion adopts a mixed solution of hydrofluoric acid solution and nitric acid solution; Preferably, the volume ratio of the hydrofluoric acid solution and the nitric acid solution is 1:3-1:9; Preferably, the concentration of hydrofluoric acid in the hydrofluoric acid solution is 45wt%-50wt%, and the concentration of nitric acid in the nitric acid solution is 60wt%-70wt%; Preferably, the alkali corrosion adopts sodium hydroxide solution or potassium hydroxide solution; Preferably, the concentration of the sodium hydroxide solution is 2wt%-15wt%, and the concentration of the potassium hydroxide solution is 2wt%-15wt%. 5 . The method for processing a semiconductor substrate layer according to claim 1 , further comprising: removing the initial semiconductor layer after performing the laser spot array scanning and before performing a texturing treatment on the initial semiconductor substrate layer. 6 . The oxide layer formed on the surface of the substrate layer; Preferably, in the step of removing the oxide layer on the surface of the initial semiconductor substrate layer, a hydrofluoric acid solution with a concentration of 1 wt % to 5 wt % is used for 5 seconds to 20 seconds. 6. The method for treating a semiconductor substrate layer according to claim 1, wherein the texturing liquid used in the texturing treatment is an alkaline solution; Preferably, the alkaline solution includes sodium hydroxide solution or potassium hydroxide solution; Preferably, the concentration of the alkaline solution is 1wt%-5wt%; Preferably, the temperature used in the texturing treatment is 80°C-90°C, and the time is 200 seconds-500 seconds. 7 . The method for processing a semiconductor substrate layer according to claim 1 , further comprising: cleaning the surface of the semiconductor substrate layer after performing the texturing treatment on the initial semiconductor substrate layer. 8 . 8. A preparation method of a solar cell, characterized in that, comprising: forming a semiconductor substrate layer, the semiconductor substrate layer is formed by the processing method for a semiconductor substrate layer according to any one of claims 1-7; Preferably, it further includes: forming a first intrinsic passivation layer on one side surface of the semiconductor substrate layer; forming a second intrinsic passivation layer on the other side surface of the semiconductor substrate layer; A first doped semiconductor layer is formed on the side surface of the intrinsic passivation layer away from the semiconductor substrate layer; a second doped semiconductor layer is formed on the side surface of the second intrinsic passivation layer away from the semiconductor substrate layer . 9 . A solar cell, comprising a semiconductor substrate layer, characterized in that, at least one side of the semiconductor substrate layer has several anti-reflection structures arranged in an array and uniformly distributed. 10 . The solar cell according to claim 9 , wherein the projected area of each of the anti-reflection structures on the semiconductor substrate layer is less than or equal to 9 μm ² ; Preferably, the height of the anti-reflection structure is 0.5 μm-3 μm; Preferably, the height difference between the bottom surfaces of any two of the anti-reflection structures is less than or equal to 1 μm; preferably, the shape of the anti-reflection structures is a pyramid.

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