CN114566490B - Vertical layout MSM capacitor structure and its manufacturing method - Google Patents

Abstract

The vertical layout MSM capacitor structure and the manufacturing method thereof can be applied to various semiconductor integrated/packaging structures with small capacitance and miniaturization requirements. The dielectric layer of the capacitor is formed by vertically arranging MSM capacitor structure dielectric partition walls on the upper surface and the lower surface of the semiconductor dielectric substrate; the two parallel rectangular through grooves, blind grooves or buried grooves are embedded with metal electrode plates P1 and P2 forming homoepitaxy of the capacitor body, the two metal electrode plates extend to two ends of the dielectric partition wall S1 through metal layer microstrip connection lines etched on the surface of the semiconductor dielectric substrate to form an electrode structure led out from the MSM capacitor leading-out ends L1 and L2, and therefore an MSM capacitor equivalent circuit structure with vertical layout is formed.

Description

Vertical layout MSM capacitor structure and its manufacturing method

technical field

The invention relates to the field of microwave technology and wireless communication technology. It is an embedded integrated three-dimensional flat capacitor structure, especially a representative metal-semiconductor- Metal (MSM), that is, MSM=metal-semiconductor-metal vertical capacitor structure, also relates to a manufacturing method of the MSM capacitor.

Background technique

限制了平行金属极板/层的尺寸，造成容值扩充与小型化的必然矛盾。而第4)类金属-绝缘体-金属(MIM)电容形态虽然解决了容值扩充与小型化的矛盾，但MIM结构中绝缘体(I)层的制备成型势必为基于半导体的一体化三维集成技术引入额外的工艺和风险。因此，如何在保证不引入额外材料、制备工艺和风险的前提下，有效缩减电容XY平面布局尺寸，进而满足电路小型化和一体化高性能集成设计需求，成为当前亟待突破的关键技术。In the current 2D/2.5D/3D integrated circuit/package design, capacitors with different capacitance values and packages are widely used in functional links such as decoupling, bypass, DC blocking, resonance, and energy storage. The existing capacitor forms mainly include: 1) Electrolytic capacitors, tantalum capacitors, monolithic capacitors, ceramic capacitors, etc. traditionally installed on the surface of plates or packages; 2) Small and medium-sized capacitors installed inside the cavity for easy interconnection or gold wire bonding Capacitance chip capacitors; 3) Z-direction stacked MIM capacitors or wafer-level integrated capacitors based on three-dimensional stacking/packaging structures, such as low-temperature co-fired ceramic LTCC, high-temperature co-fired ceramic HTCC, printed circuit board PCB, silicon-based transfer Board/MEMS stack, glass-based interposer/MEMS stack, etc.; 4) Metal-insulator-metal MIM capacitors in vertical layout. Type 1) capacitor form is aimed at traditional board-level circuit requirements; Type 2), 3) and 4) capacitor form are mainly aimed at three-dimensional packaging/three-dimensional integrated miniaturization design requirements, such as system-in-package SiP, system-on-chip SoC, package Antenna AiP etc. However, compared with the extension in the Z direction, the main contradiction of chip or module miniaturization is still concentrated in the XY plane layout. Compared with type 1) capacitor forms, although types 2) and 3) can reduce the area occupied by the plane layout to a certain extent in the application field of small and medium capacitance values, and improve the miniaturization performance, the calculation formula of the plate capacitance

The size of parallel metal plates/layers is limited, resulting in the inevitable contradiction between capacity expansion and miniaturization. Although the fourth) metal-insulator-metal (MIM) capacitance configuration solves the contradiction between capacity expansion and miniaturization, the preparation and molding of the insulator (I) layer in the MIM structure is bound to be introduced into the semiconductor-based integrated three-dimensional integration technology. Additional Processes and Risks. Therefore, how to effectively reduce the XY plane layout size of capacitors without introducing additional materials, manufacturing processes and risks, so as to meet the needs of circuit miniaturization and integrated high-performance integrated design, has become a key technology that needs to be broken through.

Contents of the invention

The object of the present invention is to provide a metal-semiconductor-metal MSM capacitor structure with a simple structure and a vertical layout in view of the shortcomings of the above-mentioned prior art. On the basis of an integrated three-dimensional integration process, the high-precision design requirements of capacitors can be maintained. To this end, the present invention also relates to a method for preparing a metal-semiconductor-metal MSM capacitor structure as described below.

The above object of the present invention can be obtained by the following measures, a vertical layout MSM capacitor structure, comprising: a multi-layer semiconductor dielectric substrate stack structure, close to the surface of the semiconductor dielectric substrate, metal layers G1, G2 that are not connected to the capacitor plate , G1 and G2 can be metal surfaces of any shape, and they can be connected or not connected to each other. It is characterized in that: a specific position of the semiconductor dielectric substrate is formed with two flat metallized through slots, blind slots or buried slots that are vertical to its surface and separated by a dielectric partition wall S1, and the dielectric partition wall S1 constitutes the dielectric layer of the capacitor; the two Two parallel rectangular through grooves, blind grooves or buried grooves are inlaid with metal electrode plates P1 and P2 that form the homogeneous epitaxy of the capacitor body, and the two metal electrode plates P1 and P2 are connected by a metal layer microstrip etched on the surface of the semiconductor dielectric substrate. The line extends to both ends of the dielectric partition wall S1 to form an electrode structure drawn from the MSM capacitor lead-out terminals L1 and L2, wherein L1 and L2 can be located on the same surface or different surfaces of the semiconductor dielectric layer, thereby forming a vertically arranged MSM capacitor equivalent Circuit configuration.

A preparation method for making the vertical layout MSM capacitor structure is characterized in that it includes the following steps: making two flat metallized through slots, blind slots or buried slots parallel to each other vertically on the semiconductor dielectric substrate, and Form the dielectric partition wall S1 of the MSM capacitor insulation layer; according to the vertical layout MSM capacitor structure interconnection relationship, etch the lead-out microstrip transmission line of the capacitor lead-out end on the upper/lower metal layer of the dielectric partition wall S1 to form the MSM capacitor lead-out end L1 and L2, depositing an adhesion layer on the sidewall and bottom of the flat metallized through groove, blind groove or buried groove, and depositing a diffusion barrier layer on the sidewall and bottom of the flat metallized through groove, blind groove or buried groove; Deposit a seed layer on the diffusion barrier layer on the side wall and bottom of the flat metallized through groove, blind groove or buried groove; electroplate filling metal in the groove where the seed layer deposition is completed, if it is a hollow metallized groove on the side wall , then the electroplating filling operation will not be performed.

Compared with the prior art, the present invention has the following beneficial effects:

The present invention aims at the inherent form and characteristics of the actual circuit/packaging substrate, and makes two flat metallized through grooves, blind grooves or buried grooves that are perpendicular to the surface of the semiconductor dielectric substrate and separated by the dielectric partition wall S1 at a specific position. The partition wall S1 constitutes the dielectric layer of the capacitor; two parallel rectangular through grooves, blind grooves or buried grooves are inlaid with metal electrode plates P1 and P2 that constitute the homogeneous epitaxy of the capacitor body, and the two metal electrode plates P1 and P2 pass through the semiconductor medium The metal layer microstrip connection etched on the surface of the substrate is extended to both ends of the dielectric partition wall S1 to form a vertical layout MSM capacitor structure. In the field of small and medium capacitance requirements, it can truly achieve the integrated integration of embedded capacitors. In particular, in addition to interconnecting metal and semiconductor dielectric substrate materials, it is not necessary to introduce other materials and processes, so as to achieve the beneficial purpose of reducing costs and controlling risks. At the same time, it overcomes the problem that capacitors in the existing semiconductor integration/packaging structure cannot be integrated in three dimensions and effectively reduces the layout size in the XY direction.

Description of drawings

Fig. 1 is the front view of a kind of vertical layout MSM capacitance structure of the present invention;

Fig. 2 is the top view of Fig. 1;

Fig. 3 is a schematic diagram of the vertical layout capacitor structure of the present invention for a blind slot plate;

4 is a schematic diagram of a single capacitor series interconnection structure;

5 is a schematic diagram of a parallel interconnection structure of a single capacitor;

FIG. 6 is a schematic diagram of a series interconnection structure of double capacitors;

FIG. 7 is a schematic diagram of a parallel interconnection structure of double capacitors;

FIG. 8 is a schematic diagram of a multi-layer stacked structure of Embodiment 5 of the MSM capacitor structure of the present invention.

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

Detailed ways

Refer to Figure 1 and Figure 2. In the exemplary preferred embodiment described below, a vertical layout MSM capacitor structure includes: a multi-layer semiconductor dielectric substrate stack structure, which is closely attached to the surface of the semiconductor dielectric substrate, metal layers G1 and G2 that are not connected to the capacitor plate, G1 and G2 can be metal surfaces of any shape, and can be connected or not connected to each other. The specific position of the semiconductor dielectric substrate is formed with two flat metallized through slots, blind slots or buried slots that are vertical to the surface and separated by the dielectric partition wall S1. The dielectric partition wall S1 constitutes the dielectric layer of the capacitor; two parallel to each other Rectangular through slots, blind slots or buried slots are inlaid with metal electrode plates P1 and P2 that form the homogeneous epitaxy of the capacitor body. The two metal electrode plates P1 and P2 are connected to the dielectric through the metal layer microstrip etched on the surface of the semiconductor dielectric substrate. The two ends of the partition wall S1 extend to form an electrode structure drawn from the MSM capacitor lead-out terminals L1 and L2, wherein L1 and L2 can be located on the same surface or different surfaces of the semiconductor dielectric layer, thereby forming a vertically arranged MSM capacitor equivalent circuit structure.

In an optional embodiment, embodiment 1:

Vertical MSM capacitor structure Two flat metallized through slots, blind slots or buried slots are parallel to each other, and the side walls of the flat metallized through slots, blind slots or buried slots can be metallized hollow structures or fully filled with metal solid structure. The dielectric partition wall S1 can be a semiconductor dielectric layer sandwiched between two flat metallized through grooves, blind grooves or buried grooves and adjacent to the side walls. The semiconductor dielectric layer and the semiconductor dielectric substrate are of the same material and integrated Connect the terminal of the capacitor. L1 and L2 may be in the form of transmission lines such as microstrip lines, striplines, and coplanar waveguides. The metal layers G1 and G2 that are not connected to the capacitor plates can be used as ground or other purposes.

Example 2:

See Figure 3. The difference between this embodiment and Embodiment 1 is that the two parallel grooves are buried grooves, that is, one end of them does not extend to communicate with the metal layer. The difference between the process steps of this embodiment and the embodiment 1 is that the process step of converting from buried trenches to through trenches by using a chemical mechanical polishing (CMP) process on the back side can be omitted.

Example 3:

Fig. 4 and Fig. 5 are schematic front views of the vertical metal-semiconductor-metal MSM capacitor structure connected in series and in parallel in an actual circuit, that is, as a display of the actual layout usage of the capacitor structure. The series access method is characterized in that, as shown in Embodiment 1, the two capacitor lead-out ends are respectively connected to the grooves of two parallel metal plates, and the two lead-out ends can be located on the same metal layer or on different metal layers up and down. The parallel metal plate grooves are not connected. The parallel connection method is characterized in that the lead ends of the two capacitors are connected to one of the parallel metal plate grooves, the two lead ends can be located on the same metal layer, or on different metal layers up and down, and the other parallel metal plate groove is connected to ground end. This embodiment is an example of the layout in which a single vertical metal-semiconductor-metal MSM capacitor performs functions such as DC blocking, filtering, and resonance in an actual circuit.

Example 4:

Fig. 6 and Fig. 7 are the front view schematic diagram and the top view schematic diagram of the parallel interconnection of the two vertical metal-semiconductor-metal MSM capacitor structures connected in series in the actual circuit, that is, as a display of the actual layout usage of the capacitor structure . The feature of the series interconnection method is that each of the two capacitors provides a parallel metal plate groove, and they are connected to each other through the transmission structure. The metal layer at the bottom of the groove plate; the two leads are connected to the grooves of the respective remaining parallel metal plates, which can be located in the same metal layer or in different metal layers above and below. The parallel interconnection method is characterized in that each of the two capacitors provides a parallel metal plate groove, and they are connected to each other through the transmission structure. The metal layer at the bottom of the groove plate; the two lead ends are respectively connected to the grooves of the parallel metal plates that are connected to each other, and the two lead ends can be located in the same metal layer, or in different metal layers up and down. This embodiment is an example of a layout in which two or more vertical metal-semiconductor-metal MSM capacitors perform functions such as multi-stage filtering and parallel resonance in an actual circuit.

Example 5:

FIG. 8 is a schematic front view of the layout of the vertical metal-semiconductor-metal MSM capacitor structure in an actual multi-layer semiconductor dielectric stack structure, which is a demonstration of the actual layout usage of the capacitor structure. The capacitor structure in this embodiment may be any structural layout and lead-out form in Embodiments 1-4, or a combination of any capacitor structures in Embodiments 1-4. Each single-layer structure can be stacked in the form of direct bonding or indirect bonding, and the number of layers stacked up and down (N1≥0 or N2≥0, and an integer), stacking methods include but are not limited to thermocompression bonding, eutectic bonding Bonding, solid-liquid diffusion bonding and other bonding processes. This embodiment is an example of the morphological layout of the vertical metal-semiconductor-metal MSM capacitor structure in an actual integrated package design structure.

The present invention has been described in detail through specific embodiments above, but it is not intended to limit the present invention. Without departing from the principle, spirit and principles of the present invention, any modifications, equivalent replacements, deformations and improvements made by those skilled in the art shall fall within the protection scope of the present invention.

Claims (10)

1. A vertical layout MSM capacitor structure, comprising: a multi-layer semiconductor dielectric substrate stack structure, which is close to the surface of the semiconductor dielectric substrate, and the metal layers G1, G2, G1 and G2 which are not connected to the capacitor plate are connected or not connected to each other The metal surface of arbitrary shape is characterized in that: a specific position of the semiconductor dielectric substrate is provided with two flat metallized through grooves, blind grooves or buried grooves perpendicular to its surface and separated by a dielectric partition wall S1, and the dielectric partition wall S1 constitutes The dielectric layer of the capacitor; two parallel rectangular through grooves, blind grooves or buried grooves are inlaid with metal electrode plates P1 and P2 that form the homogeneous epitaxy of the capacitor body, and the two metal electrode plates P1 and P2 are etched through the surface of the semiconductor dielectric substrate The metal layer microstrip connection extends to both ends of the dielectric partition wall S1 to form an electrode structure drawn from the MSM capacitor terminals L1 and L2, where L1 and L2 are located on the same surface or different surfaces of the semiconductor dielectric layer, thus forming a vertical layout The equivalent circuit structure of the MSM capacitor. 2. vertical layout MSM capacitor structure as claimed in claim 1, is characterized in that: vertical MSM capacitor body structure two flat metallized through grooves, blind groove or buried groove are mutually parallel relation, flat metallized through groove, blind groove Either the side wall of the buried trench is a metallized hollow structure, or a solid structure fully filled with metal. 3. The vertical layout MSM capacitor structure according to claim 1, characterized in that: the dielectric partition wall S1 is a semiconductor dielectric layer sandwiched between two flat metallized through grooves, blind grooves or buried grooves and adjacent to the side walls, The semiconductor medium layer is made of the same material as the semiconductor medium substrate where it is located, and is integrally connected to the lead-out end of the capacitor. 4. vertical layout MSM capacitance structure as claimed in claim 1, is characterized in that: L1 and L2 are microstrip line, stripline, coplanar waveguide transmission line form, and the non-connected metal layer G1 and G2 of electric capacity plate are used For land. 5 . The vertical layout MSM capacitor structure according to claim 1 , wherein the two parallel grooves are buried grooves, one end of which is not extended to communicate with the metal layer. 6 . 6. The vertical layout MSM capacitor structure as claimed in claim 1, characterized in that: the two capacitor leads are respectively connected to the grooves of two parallel metal plates, the two lead ends are located at the same metal layer or at different metal layers up and down, and the ground terminal It is not connected to the grooves of the two parallel metal plates: the leads of the two capacitors are connected to one of the parallel metal plate grooves, and the other parallel metal plate groove is connected to the ground terminal. 7. The vertical layout MSM capacitor structure as claimed in claim 1, characterized in that: two capacitors each provide a parallel metal plate groove, and realize interconnection through the transmission structure, and the transmission structure that plays the role of interconnection is located in the groove The metal layer on the top of the pole plate or the metal layer on the bottom of the grooved pole plate; the two lead terminals are connected to the respective remaining parallel metal pole plate grooves, and are located on the same metal layer or on different metal layers above and below. 8. The vertical layout MSM capacitor structure as claimed in claim 1, characterized in that: two capacitors each provide a parallel metal plate groove, and realize interconnection through the transmission structure, and the transmission structure that plays the role of interconnection is located in the groove The metal layer on the top of the pole plate or the metal layer at the bottom of the groove plate; the two lead ends are respectively connected to the parallel metal plate grooves that have been connected to each other, and the two lead ends can be located on the same metal layer or on different metal layers up and down. 9. The vertical layout MSM capacitance structure as claimed in claim 1, is characterized in that: capacitance structure is with arbitrary structure layout and draw-out form, or the mutual combination form of arbitrary capacitance structure, each monolayer structure is by direct bonding or indirect bonding The stacking is completed in the form of stacking, the number of stacked layers N1≥0 or N2≥0, and take an integer, and the stacking methods include thermocompression bonding, eutectic bonding, and solid-liquid diffusion bonding bonding processes. 10. A preparation method for making the described vertical layout MSM capacitance structure of claim 1, is characterized in that, comprises the following steps: on described semiconductor medium substrate, make mutually parallel vertical layout two flat metallized through grooves, blind groove or buried groove, and constitute the dielectric partition wall S1 of the MSM capacitor insulation layer; according to the vertical layout MSM capacitor structure interconnection relationship, etch the lead-out microstrip transmission line of the capacitor lead-out end on the upper/lower metal layer of the dielectric partition wall S1 to form the described MSM capacitance leads L1 and L2, deposit an adhesion layer on the side walls and bottom of the flat metallized through groove, blind groove or buried groove, and deposit an adhesive layer on the side wall and bottom of the flat metallized through groove, blind groove or buried groove Depositing a diffusion barrier layer; depositing a seed layer on the diffusion barrier layer on the side walls and bottom of the flat metallized through groove, blind groove or buried groove; electroplating filling metal in the groove where the seed layer deposition is completed, if the side If the walls are metallized hollow grooves, the electroplating filling operation is not performed.

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