CN114566483A - Chip and electronic equipment - Google Patents

Abstract

Embodiments of the present application provide a chip and an electronic device, including: multilayer wiring layers arranged in a channel region; each wiring layer in the multilayer wiring layers is wired in one direction; wherein, the multilayer wiring layers A group of signal lines are arranged along the channel direction of the channel region in the first wiring layer in the device; the second wiring layer adjacent to the first wiring layer is set as a protective ground plane.

Description

A chip and electronic device

technical field

The present application relates to the field of chips, and in particular, to a chip and an electronic device.

Background technique

At present, the chip design method of a system-on-chip (SoC) chip or a media processing chip is a channel (channel) design. The channel-designed chip has a complex chip structure, a large number of integrated IPs, and a large number of IP types. Therefore, the design of the chip designed by the channel is very difficult, which is usually realized by reserving the channel on the chip and routing in the channel.

However, a large number of signal lines run in parallel in the narrow and long channel, and the mutual capacitance and mutual inductance between adjacent signal lines make the signal part of the voltage, current and other signals carried by itself couple to the adjacent signal lines during the transmission process. Crosstalk between signals is generated.

Currently, crosstalk between signals can be reduced by increasing the spacing between signal lines or adding protective ground lines between adjacent signal lines. However, the above methods increase the channel area of the chip, thereby increasing the manufacturing cost of the chip.

SUMMARY OF THE INVENTION

The embodiments of the present application provide a chip and an electronic device, which can reduce the crosstalk between signals without changing the channel area of the chip, thereby reducing the manufacturing cost of the chip.

The technical solution of the present application is realized as follows:

An embodiment of the present application provides a chip, the chip includes: multi-layer wiring layers arranged in a channel region; each wiring layer in the multi-layer wiring layers is wired in one direction;

Wherein, the first wiring layer in the multi-layer wiring layer is arranged with a group of signal lines along the channel direction of the channel region; the second wiring layer adjacent to the first wiring layer is set as a protective ground plane .

In the above chip, the wiring directions of the first wiring layer and the second wiring layer are perpendicular to each other.

In the above chip, the second wiring layer arranges a group of ground lines in a direction perpendicular to the channel direction.

In the above chip, the channel region includes a first channel sub-region and a second channel sub-region; the channel direction of the first channel sub-region is perpendicular to the channel direction of the second channel sub-region;

When the wiring direction of the first wiring layer is the same as the channel direction of the first channel sub-region, the first wiring region of the first wiring layer is arranged along the channel direction of the first channel sub-region A group of signal lines, the second wiring region of the first wiring layer is arranged with a group of ground lines along the channel direction of the first channel sub-region; the first wiring region corresponds to the first channel sub-region , the second wiring region corresponds to the second channel sub-region;

In the case where the wiring direction of the first wiring layer is the same as the channel direction of the second channel sub-region, the second wiring region arranges a group of signal lines along the channel direction of the second channel sub-region, The first wiring region arranges a group of ground lines along the channel direction of the second channel sub-region.

In the above chip, when the wiring direction of the first wiring layer is the same as the channel direction of the first channel sub-region, the third wiring region of the second wiring layer is along the direction of the first channel sub-region. A group of ground lines are arranged in the channel direction, and a group of signal lines are arranged in the fourth wiring region of the second wiring layer along the channel direction of the first channel sub-region; the third wiring region and the first channel subregion are arranged with a group of signal lines. One channel sub-region corresponds, and the fourth wiring region corresponds to the second channel sub-region;

In the case where the wiring direction of the first wiring layer is the same as the channel direction of the second channel sub-region, the fourth wiring region arranges a group of ground lines along the channel direction of the second channel sub-region, The third wiring region arranges a group of signal lines along the channel direction of the second channel sub-region.

In the above chip, a signal transmission hole is provided at the intersection of the signal lines of the first wiring layer and the second wiring layer;

When the wiring direction of the first wiring layer is the same as the channel direction of the first channel sub-region, the signal transmission hole conducts a group of signal lines arranged in the first wiring region and the a group of signal lines arranged in the fourth wiring area;

When the wiring direction of the first wiring layer is the same as the channel direction of the second channel sub-region, the signal transmission hole conducts a group of signal lines arranged in the second wiring region and the A group of signal lines arranged in the third wiring area.

In the above chip, the top layer of the multi-layer wiring layer is provided with a power supply point, each layer of the multi-layer wiring layer is arranged with a power supply line, and a power supply hole is provided at the intersection of the power supply lines of the adjacent wiring layers. .

In the above chip, the power supply point supplies power to the multi-layer wiring layers layer by layer through the power lines and power holes of each wiring layer.

In the above chip, the set of ground lines are arranged in parallel in the second wiring layer.

An embodiment of the present application provides an electronic device, where the electronic device includes the chip described in any one of the above.

An embodiment of the present application provides a chip and an electronic device. The chip includes: multilayer wiring layers arranged in a channel region; each wiring layer in the multilayer wiring layers is wired in one direction; The first wiring layer in the wiring layers arranges a group of signal lines along the channel direction of the channel region; the second wiring layer adjacent to the first wiring layer is set as a protective ground plane. Using the above chip implementation scheme, the first wiring layer in the multi-layer wiring layer is arranged to arrange a group of signal lines along the channel direction of the channel region, and the second wiring layer adjacent to the first wiring layer is set as a protective ground plane, The crosstalk of signals in the channel can be reduced by using the second wiring layer, and the manufacturing cost of the chip can be reduced without occupying the wiring resources and without increasing the chip area.

Description of drawings

Figure 1 is a schematic diagram of a channelless chip;

Fig. 2 is the chip schematic diagram of channel chip;

3 is a schematic diagram of the channel wiring of the channel chip;

FIG. 4 is a schematic diagram of the phase of the signal line of the channel chip;

FIG. 5 is a schematic diagram 1 of a channel wiring of the current channel chip;

FIG. 6 is a schematic diagram 2 of a channel wiring of the current channel chip;

FIG. 7 is a schematic structural diagram of a chip according to an embodiment of the present application;

FIG. 8 is a schematic diagram 1 of an exemplary multi-layer wiring layer provided by an embodiment of the application;

FIG. 9 is a second schematic diagram of a wiring layer of an exemplary L-type channel region provided by an embodiment of the present application;

FIG. 10 is an exemplary trench wiring diagram;

FIG. 11 is a schematic diagram of signal crosstalk of an exemplary conventional chip;

FIG. 12 is a schematic diagram of an exemplary signal crosstalk provided by an embodiment of the present application;

FIG. 13 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed ways

It should be understood that the specific embodiments described herein are merely illustrative of the present application. It is not intended to limit this application.

Chips can include two implementations according to different product characteristics: channel and channelless (no channel). Among them, the chip structure and clock structure of the channelless chip are relatively simple, and there are a large number of repeatedly instantiated IPs. As shown in Figure 1, the channelless chip is provided with a large number of repeated digital signal processing (Digital Signal Process, DSP) modules, and is also provided with Double-rate synchronous dynamic random access memory (Double Data Rate, DDR) modules, logic (logic device) modules, CPU modules and SERDES modules are closely connected in channelless chips, which are usually large in scale. Greatly saves chip area, such as data communication chips, video processing chips, artificial intelligence (AI) chips, etc.

The chip structure of the channel chip is relatively complex, and the number and types of integrated IP are various. The design of this type of chip is very difficult, and it is generally implemented by channel routing, such as SoC chips and media processing chips. As shown in FIG. 2 , the channel chip includes a Graphics Processing Unit (GPU) module, a DDR module, a Universal Serial Bus (USB) module, and a Neural-network Processing Unit (NPU) module , peri module, high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIE) module, CPU module and MDM module, the above modules are arranged on both sides of the channel of the channel chip, and the above-mentioned signal lines are arranged in the channel to realize the above Communication and control between modules. For the channel wiring of the channel chip, as shown in FIG. 3 , seven signal lines are arranged in parallel in the channel region, and a BUF unit is arranged at the same position of each signal line. The BUF unit is used to maintain the waveform when transmitting signals and solve the signal attenuation during the transmission process. The crosstalk between the signals is shown in Figure 4. The NET_aggressor_a signal line and the NET_aggressor_c signal line have the greatest influence on the NET_victim signal line. When the lines are all on the rising edge, the crosstalk is completely superimposed.

In order to reduce the signal crosstalk in the channel area of the channel chip, you can widen the spacing of the signal lines. Referring to Figure 3 and Figure 5, only 3 signal lines can be arranged in parallel in the channel area of the same width. ; Or the routing method of adding protective ground lines between adjacent signal lines, referring to Figure 3 and Figure 6, only 3 signal lines can be arranged in parallel in the channel area of the same width. However, the above measures are all at the cost of sacrificing the channel space to reduce the crosstalk. The larger the area of the channel chip, the higher the manufacturing cost of the chip.

In order to solve the above problems, the present application proposes a chip and a signal transmission method in the chip, which are specifically described by the following embodiments.

An embodiment of the present application provides a chip 1. As shown in FIG. 7, the chip 1 includes: multilayer wiring layers arranged in a channel region; each wiring layer in the multilayer wiring layers is in one direction wiring;

Wherein, the first wiring layer in the multi-layer wiring layer is arranged with a group of signal lines along the channel direction of the channel region; the second wiring layer adjacent to the first wiring layer is set as a protective ground plane .

In the embodiment of the present application, the chip may be a chip designed by a channel such as an SoC chip, a media processing chip, or the like.

It should be noted that the number of wiring layers in the chip can be determined according to factors such as the chip type, channel width, signal line spacing, and the number of modules on the chip. limited.

In the embodiment of the present application, the number of the second wiring layers is one or two, and when the first wiring layer is on the top or bottom layer of the multilayer wiring layer, the number of the second wiring layers adjacent to the first wiring layer is one ; When the first wiring layer is not on the top or bottom layer of the wiring layer, the number of the second wiring layers adjacent to the first wiring layer is two, and the specific number of the second wiring layers is in multiple layers according to the first wiring layer. The position of the wiring layer is determined, which is not specifically limited in this embodiment of the present application.

It should be noted that the bottom layer of the multi-layer wiring layer is a layer of wiring layers adjacent to the device layer of the chip. It can be understood that the top layer of the multi-layer wiring layer is the layer of wiring layers farthest from the device layer.

In the embodiments of the present application, the channel direction of the channel region may be lateral and/or longitudinal, that is, the channel region may be a lateral channel region, a vertical channel region, or a combination of a lateral channel portion and a vertical channel portion The channel region can be specifically set according to the actual situation, which is not specifically limited in this embodiment of the present application.

In an optional embodiment, as shown in FIG. 8 , for the lateral channel, a group of signal lines are arranged laterally on the wiring layer of the Mn layer, and the wiring layer of the Mn+1 layer and the Mn- The wiring layer of layer 1 is respectively provided with a protective ground plane.

In the embodiment of the present application, a group of signal lines are arranged in parallel in the channel region, wherein the number of signal lines is multiple, and each signal line is provided with a group of relay units, which are used to maintain the signal line during the data transmission process. waveform to reduce attenuation during data transmission.

Optionally, the wiring directions of the first wiring layer and the second wiring layer are perpendicular.

It should be noted that since each wiring layer is wired in one direction, and the wiring directions of the first wiring layer and the second wiring layer are perpendicular, if the first wiring layer is set to be wired along the channel direction, the second wiring layer The wiring is carried out in the direction perpendicular to the channel direction.

It should be noted that since the wiring directions of the first wiring layer and the second wiring layer are perpendicular, that is, the multilayer wiring layers follow the wiring form of horizontal wiring-vertical wiring-horizontal wiring, or vertical wiring-horizontal wiring-vertical wiring. Route the wiring layer by layer.

Further, for the lateral channel, a set of signal lines are arranged laterally on the wiring layer of the Mn layer, and a protective ground plane is respectively provided on the wiring layer of the Mn+1 layer and the wiring layer of the Mn-1 layer. Then a group of signal lines are still arranged laterally on the wiring layer of the Mn+2 layer and the wiring layer of the Mn-2 layer, and a protective ground plane is respectively set on the wiring layer of the Mn+3 layer and the wiring layer of the Mn-3 layer. And so on, until the layout and wiring of the multi-layer wiring layers are completed.

Optionally, a group of ground lines are arranged in the second wiring layer along a direction perpendicular to the channel direction.

In the embodiment of the present application, since the wiring direction between the second wiring layer and the first wiring layer is vertical, the way of setting the protective ground plane on the second wiring layer can be to arrange a group of ground planes along the direction perpendicular to the channel direction. ground wire.

It should be noted that, the number of a group of ground wires can be determined according to the degree of anti-crosstalk between signals or other parameters, which is not specifically limited in the embodiment of this application. It can be understood that the more the number of a group of ground wires, the The higher the degree of anti-crosstalk between signals.

Optionally, the group of ground wires are arranged in parallel in the second wiring layer.

For a horizontal channel, a group of signal lines are arranged horizontally on the first wiring layer, and a group of ground lines are arranged vertically on the second wiring layer; for a vertical channel, a group of signal lines are arranged vertically on the first wiring layer , a group of ground wires are arranged laterally on the second wiring layer.

Optionally, the channel region includes a first channel sub-region and a second channel sub-region; the channel direction of the first channel sub-region is perpendicular to the channel direction of the second channel sub-region;

When the wiring direction of the first wiring layer is the same as the channel direction of the first channel sub-region, the first wiring region of the first wiring layer is arranged along the channel direction of the first channel sub-region A group of signal lines, the second wiring region of the first wiring layer is arranged with a group of ground lines along the channel direction of the first channel sub-region; the first wiring region corresponds to the first channel sub-region , the second wiring region corresponds to the second channel sub-region;

In the case where the wiring direction of the first wiring layer is the same as the channel direction of the second channel sub-region, the second wiring region arranges a group of signal lines along the channel direction of the second channel sub-region, The first wiring region arranges a group of ground lines along the channel direction of the second channel sub-region.

It should be noted that, in practical applications, the direction of the channel region of the chip can be determined according to the specific arrangement of each functional module in the chip, and the type of the channel region can be a horizontal channel, a vertical channel, or an L-shaped channel. The case of a combined channel region in which a lateral channel sub-region and a vertical channel sub-region are combined, such as a channel. For the combined channel region, the channel region is divided into a first channel subregion and a second channel subregion, wherein the channel directions of the first channel subregion and the second channel subregion are perpendicular, that is, when the first channel subregion is When the channel direction of the second channel sub-region is horizontal, the channel direction of the second channel sub-region is vertical; when the channel direction of the first channel sub-region is vertical, the channel direction of the second channel sub-region is horizontal.

It should be noted that the number of the first channel sub-region is at least one, the number of the second channel sub-region is at least one, and the first channel sub-region and the second channel sub-region are alternately connected.

In the embodiment of the present application, for the combined channel region, each wiring layer in the multi-layer wiring layer is correspondingly divided into two regions, and for the first wiring layer, it is divided into the first wiring layer region and a second wiring region, wherein the first wiring layer corresponds to the first channel sub-region, and the second wiring layer corresponds to the second channel sub-region. In the case where the wiring direction of the first wiring layer is the same as the channel direction of the first channel sub-region, the first wiring region arranges a group of signal lines along the channel direction of the first channel sub-region, and the second wiring region is arranged along the channel direction of the first channel sub-region. A group of ground lines are arranged in the channel direction of the first channel sub-region; correspondingly, in the case where the wiring direction of the first wiring layer is set to be the same as the channel direction of the second channel sub-region, the first wiring region is arranged along the second channel sub-region. A group of ground lines are arranged in the channel direction of the channel sub-region, and a group of signal lines are arranged in the second wiring region along the channel direction of the second channel sub-region.

Exemplarily, the wiring direction of the first wiring layer is set as horizontal wiring, and when the channel direction of the first channel sub-region is horizontal and the channel direction of the second channel sub-region is vertical, the corresponding A group of signal lines are arranged laterally in the first wiring region, and a group of ground lines are arranged laterally in the second wiring region corresponding to the second channel sub-region; when the channel direction of the first channel sub-region is vertical, the second channel sub-region When the channel direction is lateral, a set of ground lines is laterally arranged in the first wiring region, and a set of signal lines is laterally arranged in the second wiring region.

Optionally, when the wiring direction of the first wiring layer is the same as the channel direction of the first channel sub-region, the third wiring region of the second wiring layer is along the groove of the second channel sub-region. A group of ground lines are arranged in the channel direction, and a group of signal lines are arranged in the fourth wiring region of the second wiring layer along the channel direction of the second channel sub-region; the third wiring region and the first corresponding to the channel sub-region, and the fourth wiring region corresponds to the second channel sub-region;

In the case where the wiring direction of the first wiring layer is the same as the channel direction of the second channel sub-region, a group of ground lines are arranged in the fourth wiring region along the channel direction of the first channel sub-region, The third wiring region arranges a group of signal lines along the channel direction of the first channel sub-region.

It should be noted that, for the combined channel region, the second wiring layer adjacent to the first wiring layer is also divided into a third wiring region and a fourth wiring region, wherein the third wiring region corresponds to the first channel sub-region , the fourth wiring region corresponds to the second channel sub-region. Accordingly, the first channel sub-regions correspond to the first wiring region and the third wiring region, respectively, and the second channel sub-regions correspond to the second wiring region and the fourth wiring region, respectively. In the case where the wiring direction of the first wiring layer is the same as the channel direction of the first channel sub-region, the wiring direction of the second wiring layer is the same as the channel direction of the second channel sub-region, and in this case, the third wiring region A group of ground lines are arranged along the channel direction of the second channel sub-region, and a group of signal lines are arranged along the channel direction of the second channel sub-region in the fourth wiring region; When the channel direction of the channel sub-region is the same, the wiring direction of the second wiring layer is the same as the channel direction of the first channel sub-region, and at this time, the third wiring region is arranged along the channel direction of the first channel sub-region A group of signal lines, the fourth wiring region arranges a group of ground lines along the channel direction of the first channel sub-region.

Exemplarily, if the wiring direction of the first wiring layer is set as horizontal wiring, then the wiring direction of the second wiring layer is vertical wiring. When the channel direction of the first channel sub-region is horizontal, the channel direction of the second channel sub-region is horizontal. When it is vertical, a group of ground lines are arranged vertically in the third wiring region corresponding to the first channel subregion, and a group of signal lines are arranged vertically in the fourth wiring region corresponding to the second channel subregion; when the first channel subregion When the channel direction of the second channel sub-region is horizontal, a group of signal lines are arranged vertically in the third wiring region, and a group of ground lines are arranged vertically in the fourth wiring region.

As shown in FIG. 9 , for the L-type channel region, two wiring layers of wiring layer 1 and wiring layer 2 are arranged thereon, and wiring layer 1 includes wiring area 10 and wiring area 11 (divided by the dotted line in FIG. 9 ). ), the wiring layer 2 includes a wiring area 20 and a wiring area 21 (divided by the dotted line in FIG. 9 ), the wiring area 10 and the wiring area 20 correspond to the channel sub-region 1 of the L-type channel area, and the wiring area 11 and the wiring area 21 corresponds to the channel sub-region 2 of the L-type channel region; wherein, the channel direction of the channel sub-region 1 is horizontal, the channel direction of the channel sub-region 2 is vertical, and the wiring direction of the wiring layer 1 is horizontal, then the wiring layer The wiring direction of 2 is vertical, then a group of signal lines (long horizontal lines in the wiring area 10 in FIG. 9) are arranged horizontally in the wiring area 10, and a group of ground lines are arranged vertically in the wiring area 20 (the wiring area in FIG. 9). 20); the wiring area 11 is arranged with a set of ground lines horizontally (the short dashed lines in the wiring area 11 in FIG. 9), and the wiring area 21 is arranged with a group of signal lines vertically (the wiring area 21 in FIG. 9). long vertical bar).

Optionally, a signal transmission hole is set at the intersection of the signal lines of the first wiring layer and the second wiring layer;

When the wiring direction of the first wiring layer is the same as the channel direction of the first channel sub-region, the signal transmission hole conducts a group of signal lines arranged in the first wiring region and the a group of signal lines arranged in the fourth wiring area;

When the wiring direction of the first wiring layer is the same as the channel direction of the second channel sub-region, the signal transmission hole conducts a group of signal lines arranged in the second wiring region and the A group of signal lines arranged in the third wiring area.

In the embodiment of the present application, for the combined channel region, a signal transmission hole is provided in the form of punching holes at the intersection of signal lines of two adjacent wiring layers, and the signal transmission holes are used to conduct conduction between two adjacent layers. Corresponding signal lines between the wiring layers, so that the signal to be transmitted can be transmitted between two adjacent wiring layers, thereby realizing the purpose of transmitting the signal to be transmitted to the target functional module on the chip through the combined channel region.

It should be noted that the chip includes functional modules distributed on both sides of the channel area. Referring to FIG. 2, the functional modules include a GPU module, a DDR module, a USB module, an NPU module, a PERI module, a PCIE module, a CPU module and an MDM module. The signal lines arranged in the multi-layer wiring layers are respectively connected to the functional modules, and the signals can be transmitted between the functional modules through the signal lines arranged in the multi-layer wiring layers, thereby realizing the in-chip communication and control process.

In an optional embodiment, when the wiring direction of the first wiring layer is the same as the channel direction of the first channel sub-region, the first wiring region of the first wiring layer and the fourth wiring layer of the second wiring layer Signal lines are arranged in the wiring area. At this time, the signal transmission hole conducts a group of signal lines arranged in the first wiring area and a group of signal lines arranged in the fourth wiring area; Transfer between a wiring area and a fourth wiring area.

In another optional embodiment, when the wiring direction of the first wiring layer is the same as the channel direction of the second channel sub-region, the second wiring region of the first wiring layer and the first wiring layer of the second wiring layer The signal lines are arranged in the three wiring areas, and the signal transmission hole conducts a group of signal lines arranged in the second wiring area and a group of signal lines arranged in the third wiring area; area and the third routing area.

Optionally, a power supply point is provided on the top layer of the multi-layer wiring layers, power lines are arranged on each wiring layer in the multi-layer wiring layers, and power holes are provided at the intersections of the power lines of adjacent wiring layers.

In the embodiment of the present application, the power supply layout is performed on the multi-layer wiring layers according to the preset power supply plan. And a power supply hole is arranged at the intersecting position of the power supply lines of the adjacent wiring layers.

Optionally, the power supply point supplies power to the multi-layer wiring layers layer by layer through power lines and power holes of the wiring layers of each layer.

Further, the specific layout and wiring method of the above-mentioned wiring layer is only a part of the implementation process of the chip layout and wiring, and the chip is laid out and wired based on the specific layout and wiring method of the above-mentioned wiring layer until the physical design of the chip is completed. The layout and wiring form is not discussed in detail in this application.

It can be understood that the first wiring layer in the multi-layer wiring layer is arranged to arrange a group of signal lines along the channel direction of the channel region, and the second wiring layer adjacent to the first wiring layer is set as a protective ground plane, which can be The second wiring layer is used to reduce the crosstalk of signals in the channel without occupying the wiring resources and increasing the chip area, thereby reducing the manufacturing cost of the chip.

Exemplarily, as shown in FIG. 10 , there are 5 signal lines out_22_5_NET, out_23_5_NET, out_24_5_NET, out_25_5_NET and out_26_5_NET in the channel region. For the existing layout and wiring method, the middle of the 4 signal lines on both sides is out_24_5_NET. There is crosstalk. After spice simulation without any processing, the crosstalk value of each signal line pair out_24_5_NET is shown in Figure 11; after adding a single-layer protective ground plane, a spice square matrix is performed, and the crosstalk value of each signal line pair out_24_5_NET is shown in Figure 12; according to 11 and 12, it can be seen that the layout and wiring method of adding a protective ground plane proposed in this application can greatly reduce the signal crosstalk between signal lines in the chip.

Based on the foregoing embodiments, the embodiments of the present application further provide an electronic device, and FIG. 13 is a schematic structural diagram of an electronic device proposed by the embodiments of the present application. As shown in FIG. 13 , in the embodiment of the present application, the electronic device 2 includes the above-mentioned chip 1 .

It should be noted that, in the embodiments of the present application, the electronic device 2 may be a terminal such as a smart phone or a tablet computer, and the chip 1 is provided therein. The specific electronic device 2 is not limited in this embodiment of the present application.

It should be noted that, in the embodiments of the present application, the electronic device 2 may include not only the chip 1 but also devices such as a display screen and a battery to provide corresponding functions, which are not limited in the embodiments of the present application.

It should be noted that, herein, the terms "comprising", "comprising" or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements, It also includes other elements not expressly listed or inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application. , should be covered within the scope of protection of this application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims (10)

1. A chip, characterized in that the chip comprises: multi-layer wiring layers arranged in a channel region; each wiring layer in the multi-layer wiring layers is wired in one direction; Wherein, the first wiring layer in the multi-layer wiring layer is arranged with a group of signal lines along the channel direction of the channel region; the second wiring layer adjacent to the first wiring layer is set as a protective ground plane . 2 . The chip according to claim 1 , wherein the wiring directions of the first wiring layer and the second wiring layer are perpendicular. 3 . 3 . The chip according to claim 1 , wherein a group of ground lines are arranged in the second wiring layer along a direction perpendicular to the channel direction. 4 . 4 . The chip according to claim 1 , wherein the channel region comprises a first channel sub-region and a second channel sub-region; the channel direction of the first channel sub-region is the same as that of the second channel sub-region. The channel direction of the sub-region is vertical; When the wiring direction of the first wiring layer is the same as the channel direction of the first channel sub-region, the first wiring region of the first wiring layer is arranged along the channel direction of the first channel sub-region A group of signal lines, the second wiring region of the first wiring layer is arranged with a group of ground lines along the channel direction of the first channel sub-region; the first wiring region corresponds to the first channel sub-region , the second wiring region corresponds to the second channel sub-region; In the case where the wiring direction of the first wiring layer is the same as the channel direction of the second channel sub-region, the second wiring region arranges a group of signal lines along the channel direction of the second channel sub-region, The first wiring region arranges a group of ground lines along the channel direction of the second channel sub-region. 5. chip according to claim 4, is characterized in that, When the wiring direction of the first wiring layer is the same as the channel direction of the first channel sub-region, the third wiring region of the second wiring layer is arranged along the channel direction of the first channel sub-region a group of ground lines, the fourth wiring region of the second wiring layer is arranged with a group of signal lines along the channel direction of the first channel sub-region; the third wiring region corresponds to the first channel sub-region , the fourth wiring region corresponds to the second channel sub-region; In the case where the wiring direction of the first wiring layer is the same as the channel direction of the second channel sub-region, the fourth wiring region arranges a group of ground lines along the channel direction of the second channel sub-region, The third wiring region arranges a group of signal lines along the channel direction of the second channel sub-region. 6 . The chip according to claim 5 , wherein signal transmission holes are provided at the intersections of the signal lines of the first wiring layer and the second wiring layer; 6 . When the wiring direction of the first wiring layer is the same as the channel direction of the first channel sub-region, the signal transmission hole conducts a group of signal lines arranged in the first wiring region and the a group of signal lines arranged in the fourth wiring area; When the wiring direction of the first wiring layer is the same as the channel direction of the second channel sub-region, the signal transmission hole conducts a group of signal lines arranged in the second wiring region and the A group of signal lines arranged in the third wiring area. 7 . The chip according to claim 1 , wherein a power supply point is provided on the top layer of the multi-layer wiring layers, and power lines are arranged in each wiring layer of the multi-layer wiring layers, and are wired in adjacent ones. 8 . A power hole is set at the intersection of the power lines of the layer. 8 . The chip according to claim 7 , wherein the power supply point supplies power to the multi-layer wiring layers layer by layer through the power supply lines and power supply holes of the wiring layers of each layer. 9 . 9 . The chip of claim 3 , wherein the group of ground wires are arranged in parallel in the second wiring layer. 10 . 10. An electronic device, wherein the electronic device comprises the chip according to any one of claims 1-9.

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