CN114566423A - Silicon III-V semiconductor epitaxial structure and preparation method thereof - Google Patents

Abstract

The embodiment of the invention provides a silicon III-V semiconductor epitaxial structure and a preparation method thereof, wherein the method comprises the following steps: growing an adaptation layer on a silicon substrate directly or indirectly; growing a III-V semiconductor target epitaxial structure directly or indirectly on the adaptation layer; wherein the adaptation layer comprises a ternary system III-arsenide adaptation layer or a binary system III-V compound adaptation layer. The method has simple growth process, easy regulation and control and no special requirement on growth equipment. In particular, the thin thickness of the matching layer required to reduce threading dislocation density makes it possible to subsequently optimize the III-V semiconductor epitaxial structure by increasing the number and thickness of layers, facilitating the fabrication of high performance III-V semiconductor devices on silicon.

Description

III-V semiconductor epitaxial structure on silicon and preparation method thereof

technical field

The invention relates to the field of semiconductor integration, in particular to a III-V group semiconductor epitaxial structure on silicon and a preparation method thereof.

Background technique

The silicon-based microelectronics technology represented by integrated circuits has been highly developed and made great progress since its inception in the 1950s. Great convenience. With the further development of the information society and the advent of the era of big data, people's demands for data transmission rate and information processing speed are also getting higher and higher. Today's integrated circuits are unable to maintain Moore's Law, and Moore's Law is facing the danger of failure.

With the development of silicon-based photonics, using light as the carrier of information transmission can not only overcome the defects of electrical interconnection, but also give full play to the advantages of low loss and high speed of information transmission in the optical interconnection system. However, silicon is an indirect bandgap material with extremely low luminous efficiency, making it difficult to be used as a gain medium. For this reason, silicon-based light sources have become the biggest obstacle to the development of silicon-based photonics.

Researchers have carried out a lot of work on silicon-based light sources, but still have not made a complete breakthrough. Among the realization schemes of silicon-based light sources, the monolithic integration of III-V semiconductor light sources on silicon is the most promising, but there are lattice mismatches, thermal mismatches and polarity mismatches between silicon and III-V semiconductor materials. The problem of matching seriously affects the performance of silicon-based light sources, especially the high density of threading dislocations in III-V semiconductor materials on silicon will greatly reduce the life of silicon-based light sources (for example, the current silicon-based GaAs system quantum The lifetime of the trap laser is only a few hundred hours). At present, to reduce the threading dislocation density in monolithically integrated III-V semiconductor materials on silicon, mainly on the basis of two-step growth and three-step growth, thermal cycle annealing, dislocation barrier layers or dislocations are introduced. Filter layers, patterned substrates and other traditional solutions such as blocking threading dislocations, changing the upward propagation direction of + threading dislocations, and their combinations have certain effects, but they have failed to combine III-V semiconductor materials on silicon. The threading dislocation density is reduced to an ideal range.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide a III-V semiconductor epitaxial structure on silicon and a preparation method thereof, so as to solve the problems in the prior art.

An embodiment of the present invention provides a method for preparing a III-V semiconductor epitaxial structure on silicon, including: growing an adaptation layer directly or indirectly on a silicon substrate; directly or indirectly growing a III-V group on the adaptation layer A semiconductor target epitaxial structure; wherein, the adaptation layer comprises a ternary system III group arsenide adaptation layer or a binary system III-V group compound adaptation layer.

According to a method for preparing a III-V semiconductor epitaxial structure on silicon according to an embodiment of the present invention, indirectly growing an adaptation layer on a silicon substrate includes: after growing a group III phosphide buffer layer on the silicon substrate, The adaptation layer is grown on the III-phosphide buffer layer.

According to a method for preparing a III-V semiconductor epitaxial structure on silicon according to an embodiment of the present invention, directly growing a III-V semiconductor target epitaxial structure on the adaptation layer includes: growing a crystal lattice on the adaptation layer A III-V group target semiconductor epitaxial structure with matching constants, or a III-V group target semiconductor epitaxial structure with a lattice mismatch of the adaptation layer between -5.2% and -7.8%; on the adaptation layer Indirectly growing a III-V semiconductor target epitaxial structure, comprising: after growing a III-V group compound transition layer on the adaptation layer, growing the III-V group semiconductor target on the III-V group compound transition layer Epitaxial structure.

与

之间的III-V族化合物外延层；或者所述适配层的材料为In_x1Ga_1-x1As(0.15≤x1≤1)或In_x2Al_1-x2As(0.13≤x2≤1)；所述三元系III族砷化物适配层的组分优化值结合待生长的III-V族半导体目标外延结构予以确定。According to a method for preparing a III-V semiconductor epitaxial structure on silicon according to an embodiment of the present invention, the adaptation layer has a zinc blende crystal structure, and the lattice constant is between

and

The III-V compound epitaxial layer between them; or the material of the adaptation layer is In _x1 Ga _1-x1 As (0.15≤x1≤1) or Inx2 Al _{1-x2 As} (0.13≤x2≤1); The composition optimization value of the ternary group III arsenide adaptation layer is determined in combination with the target epitaxial structure of the III-V group semiconductor to be grown.

与

之间。According to an embodiment of the present invention, a method for preparing a III-V semiconductor epitaxial structure on silicon, the III-V semiconductor target epitaxial structure is a single-layer or multi-layer structure, and the lattice constant is between

and

between.

According to a method for preparing a group III-V semiconductor epitaxial structure on silicon according to an embodiment of the present invention, the group III phosphide buffer layer is composed of any one or more of GaP, AlGaP or AlP, wherein Al composition in the AlGaP layer is y1, the Ga component is y2, and y1+y2=1, 0<y1, y2<1, the lattice mismatch between the group III phosphide buffer layer and silicon is between 0.368% and 0.372%.

According to a method for preparing a III-V semiconductor epitaxial structure on silicon according to an embodiment of the present invention, growing a III-phosphide buffer layer on a silicon substrate includes:

Grow a 5-50nm GaP buffer layer at a low temperature of 350-450℃;

Grow a GaP buffer layer of 0-150nm at a high temperature of 500-750℃;

Growing the adaptation layer on the Group III phosphide buffer layer includes:

A In _0.15 Ga _0.85 As adaptation layer with a thickness of 0.5 to 30 nm and an In composition of 0.15 was grown at 400 to 500 °C;

A III-V compound transition layer is grown on the adaptation layer, including:

A low-temperature GaAs buffer layer with a thickness of 10nm-100nm is grown at 400-550℃ as a transition layer;

Growing the III-V semiconductor target epitaxial structure on the III-V compound transition layer includes:

GaAs and a material system suitable for GaAs are grown at 580-730 ℃, and the preparation of the target epitaxial structure of GaAs series semiconductor on silicon is completed.

According to a method for preparing a III-V semiconductor epitaxial structure on silicon according to an embodiment of the present invention, the adaptation layer is directly grown on the silicon substrate, including:

Growing an InP adaptation layer with a thickness of 0.5-30 nm at 400-500 °C;

Directly growing a III-V semiconductor target epitaxial structure on the adaptation layer, including:

InP and a material system suitable for InP are grown at 580-730 ℃, and the preparation of the target epitaxial structure of InP-based semiconductor on silicon is completed.

According to a method for preparing a III-V semiconductor epitaxial structure on silicon according to an embodiment of the present invention, growing a III-phosphide buffer layer on a silicon substrate includes:

Growth of 5-50nm AlP buffer layer at low temperature of 350-450℃;

Continue to grow AlP buffer layer of 0-150nm at high temperature of 500-750℃;

Growing the adaptation layer on the Group III phosphide buffer layer includes:

growing an In _0.73 Ga _0.27 As adaptation layer with a thickness of 0.5-30 nm at 400-500 ℃;

Growth of III-V semiconductor target epitaxial structures on the adaptation layer, including:

GaAs and a material system suitable for GaAs are grown at 400-750 ℃, and the preparation of the target epitaxial structure of GaAs series semiconductor on silicon is completed.

The embodiment of the present invention also provides a III-V semiconductor epitaxial structure on silicon, which is prepared by any of the above-mentioned methods for preparing a III-V semiconductor epitaxial structure on silicon. The silicon III-V semiconductor epitaxial structure, For preparing silicon-based photonics devices or silicon-based electronic devices, the silicon-based photonics devices include: silicon-based III-V semiconductor lasers, silicon-based III-V superluminescent diodes, silicon-based III-V group luminescence Diodes, silicon-based III-V optical amplifiers, silicon-based III-V photodetectors, or silicon-based III-V passive devices.

The III-V semiconductor epitaxial structure on silicon and the preparation method thereof provided by the embodiments of the present invention have simple growth process, easy regulation, and no special requirements for growth equipment. In particular, the thickness of the adaptation layer required to reduce the threading dislocation density is thin, making it possible to optimize the III-V semiconductor epitaxial structure by increasing the number and thickness of the layers, which is beneficial for high-performance III-V semiconductors on silicon. device preparation.

Description of drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained according to these drawings without creative efforts.

Fig. 1 is the atomic arrangement cross-sectional schematic diagram of the adaptation layer and its lower layer;

2 is a schematic flowchart of a method for preparing a III-V semiconductor epitaxial structure on silicon provided by an embodiment of the present invention;

3 is a schematic diagram of an epitaxial structure of a GaAs-based semiconductor on silicon incorporating an adaptation layer provided by an embodiment of the present invention;

4 is a schematic diagram of an epitaxial structure of an InP-based semiconductor on silicon incorporating an adaptation layer provided by an embodiment of the present invention;

5 is a schematic diagram of an epitaxial structure of a GaAs-based semiconductor on silicon that introduces double-interface resident defects according to an embodiment of the present invention;

6 is a schematic diagram of an epitaxial structure of a GaSb-based semiconductor on silicon incorporating an adaptation layer provided by an embodiment of the present invention;

7 is a schematic flowchart of a method for fabricating a III-V semiconductor epitaxial structure on silicon provided by another embodiment of the present invention.

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments These are some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

The following describes the III-V semiconductor-on-silicon epitaxial structure and the preparation method thereof according to the embodiments of the present invention with reference to FIG. 1 to FIG. 7 .

Figure 1 is a schematic cross-sectional view of the atomic arrangement of the adaptation layer and its lower layer. Wherein, 101 is an adaptation layer, 102 is an interface resident defect, and 103 is a lower layer (specifically refers to a silicon substrate or a group III phosphide buffer layer). FIG. 1 is a schematic longitudinal cross-sectional view of the adaptation layer 101 and its lower layer 103 . There are interface resident defects 102 at the interface between the adaptation layer 101 and its lower layer 103 (there are two interface resident defects 102 in FIG. 1 ), and the interface resident defects 102 The reason for this is that the adaptation layer 101 and its lower layer 103 have a large lattice mismatch degree. If the lattice mismatch degree between the adaptation layer 101 and its lower layer 103 is α, naturally, the adaptation layer 101 and its lower layer The interface formed by 103 is a plane, and x and y represent the two directions perpendicular to each other in the plane, then in the x direction of the adaptation layer 101 next to the interface, a dangling bond will be generated with a period of 1/α atoms , that is, an interface resident defect 02. Further, when the lattice mismatch degree α of the adaptation layer 101 and its lower layer 103 is 11.1%, then in the x direction of the adaptation layer 101 adjacent to the interface, every 9 atoms of the adaptation layer material in a row are generated behind A dangling bond, that is, an interface resident defect (as shown in Figure 1). Since the cross-section is composed of a series of parallel planes, the interface resident defects generated by each plane are combined and aligned in the y-direction. Similarly, according to the principle of symmetry, in the y direction of the adaptation layer 101 adjacent to the interface, a defect is also generated behind every 9 atoms of the adaptation layer material in a column, and these defects are combined together to align in the x direction. Arranged in a row. That is to say, defects with both row (x-direction) and column (y-direction) periods are generated in the adaptation layer 101 immediately adjacent to the interface. And these defects only exist at the interface, do not propagate upward, that is, "reside" at the interface. Due to the existence of periodic interface resident defects, the stress caused by lattice mismatch between the adaptation layer 101 and its underlying layer 103 is effectively released, and the density of threading dislocations formed at the interface due to lattice mismatch is significantly reduced.

FIG. 2 is a schematic flowchart of a method for preparing a III-V semiconductor epitaxial structure on silicon provided by an embodiment of the present invention. As shown in FIG. 2 , an embodiment of the present invention provides a III-V semiconductor epitaxial structure on silicon. Methods of preparation, including:

201. Grow an adaptation layer directly or indirectly on a silicon substrate; the adaptation layer includes a ternary group III arsenide adaptation layer or a binary system III-V group compound adaptation layer.

202. Directly or indirectly grow a III-V semiconductor target epitaxial structure on the adaptation layer.

At present, the common variant epitaxy (also known as heteroepitaxy) scheme basically reduces the amount of material in the top variant epitaxial layer by blocking the threading dislocation or changing the upward propagation direction of the threading dislocation during the propagation of the threading dislocation. the threading dislocation density. It is well known that threading dislocations occur at the hetero-interface between the substrate and the hetero-epitaxial layer. The physical mechanism of the threading dislocation is that there is a certain degree of lattice mismatch between the epitaxial layer and the substrate, and the greater the degree of lattice mismatch is. , the more strain energy accumulated in the growth process of the metamorphic epitaxial layer on the substrate, the higher the threading dislocation density generated at the hetero interface between the metamorphic epitaxial layer and the substrate in order to release the strain energy. That is, the heterointerface of two materials with a significant mismatch in lattice constants is the source of threading dislocations. Therefore, for metamorphic epitaxy with a large lattice mismatch, such as growing III-V semiconductors on silicon, the density of threading dislocations generated at the hetero interface between the silicon substrate and the III-V semiconductors is very high. For the growth of III-V semiconductors on silicon, since the first growing III-V low-temperature nucleation layer on the silicon substrate cannot have any effective control measures for threading dislocations, if only the threading dislocations propagate upwards Common schemes to reduce dislocation density (such as thermal cycle annealing, dislocation blocking or dislocation filter layers, patterned substrates, etc.) are used, which ultimately lead to top variant epitaxy due to the limited ability of these common schemes to control threading dislocations The effect of reducing the density of threading dislocations in the layer is not ideal.

However, the embodiment of the present invention breaks the above-mentioned conventional thinking and technical limitations, and moves the position of controlling the threading dislocation density to the hetero interface, that is, the threading dislocation density is greatly reduced from the source. To this end, the embodiments of the present invention introduce a group III arsenide semiconductor "adaptation layer" when growing a III-V semiconductor epitaxial structure on silicon, and the adaptation layer is directly or indirectly grown on the silicon substrate, the so-called "adaptive layer" here "Indirect" includes growing a III-phosphide buffer layer on a silicon substrate with a lattice mismatch between 0.368% and 0.372% (basically, it can be considered as lattice matching), and then growing on the III-phosphide buffer layer. Growth adaptation layer. The core function of the adaptation layer is to use a sufficiently high degree of lattice mismatch with the underlying silicon or group III phosphide buffer layer to generate non-upward at the interface with the underlying silicon or group III phosphide buffer layer. Periodic interface resident defects that penetrate but can relieve stress between the III-V semiconductor target epitaxial structure and silicon.

It is well known that interfacial stress is released by interfacial defects and interfacial threading dislocations. Under the condition of constant total stress, the more stress released by the adaptation layer, the less stress is left for interfacial threading dislocations. Since the adaptation layer has released some or even most of the stress, the residual stress released by the generation of threading dislocations has been greatly reduced compared with the case where the adaptation layer is not introduced, so the final effect of introducing the adaptation layer is greatly reduced. Threading dislocation density in III-V semiconductor target epitaxial structures grown on top of the adaptation layer. In addition, the present invention can still introduce conventional solutions such as a stress release layer or a dislocation blocking layer in the epitaxial growth above the adaptation layer to further reduce the threading dislocation density.

In addition, the adaptation layer in the embodiment of the present invention includes, but is not limited to, a ternary system III group III arsenide adaptation layer and a binary system III-V group compound adaptation layer with adjustable composition. It can be selected from InGaAs or InAlAs semiconductor materials with tunable composition of ternary system and InP semiconductor material of binary system. The change of composition makes the lattice constant of the adaptation layer change accordingly. It is precisely because the composition is tunable that it can be combined The composition of the target epitaxial structure to be grown is optimized to ensure that there are few or no defects in the adaptation layer, and at the same time, it is also ensured that there are few or no defects in the semiconductor epitaxial structure. The composition variation range defined by the embodiments of the present invention ensures that periodic interface resident defects are generated at the interface between the adaptation layer and the underlying silicon or group III phosphide buffer layer, and the adaptation layer can also be combined with III-V semiconductor epitaxy. Periodic interface resident defects are generated at the interface of the structure, and the III-V semiconductor epitaxial structure with various lattice constants is flexibly compatible upward, that is to say, it is only necessary to simply adjust the composition of the adaptation layer to grow on it. It is a kind of III-V semiconductor epitaxial structure with different lattice constants and very low internal threading dislocation density, so the adaptation layer has a wide range of applications.

与

之间。As an optional embodiment, the III-V semiconductor target epitaxial structure is a single-layer or multi-layer structure, and the lattice constant is between

and

between.

Specifically, the material constituting the target epitaxial structure of the III-V semiconductor can be any one of GaAs, InGaAs, InAlAs, GaAsSb, InP, InAs and GaSb, etc., or can be a material system suitable for these materials respectively .

The preparation method of the III-V semiconductor epitaxial structure on silicon according to the embodiment of the present invention has the advantages of simple growth process, easy regulation and no special requirements for growth equipment. In particular, the thickness of the adaptation layer required to reduce the threading dislocation density is thin, making it possible to optimize the III-V semiconductor epitaxial structure by increasing the number and thickness of the layers, which is beneficial for high-performance III-V semiconductors on silicon. device preparation.

Based on the content of the foregoing embodiments, as an optional embodiment, indirectly growing the adaptation layer on the silicon substrate includes: after growing the group III phosphide buffer layer on the silicon substrate, then growing the group III phosphide buffer layer on the silicon substrate. The adaptation layer is grown on the layer.

Specifically, a group III phosphide buffer layer is first grown on a silicon substrate, then an adaptation layer is grown on the group III phosphide buffer layer, and then a III-V semiconductor target epitaxial structure is grown directly on the adaptation layer.

Based on the contents of the foregoing embodiments, as an optional embodiment, indirectly growing a III-V semiconductor target epitaxial structure on the adaptation layer includes: growing a III-V compound transition layer on the adaptation layer Then, the III-V group semiconductor target epitaxial structure is grown on the III-V group compound transition layer.

Specifically, the adaptation layer is directly grown on the silicon substrate, then the transition layer of the III-V group compound is grown on the adaptation layer, and then the target epitaxial structure of the III-V group semiconductor is grown.

The III-V compound transition layer is located between the adaptation layer and the III-V semiconductor target epitaxial structure, and the introduction of a conventional stress release mechanism and/or a dislocation blocking mechanism in the transition layer can continue to reduce the III-V semiconductor target epitaxy Stress between the structure and the silicon substrate.

Based on the combination of the above-mentioned indirect growth adaptation layer and the indirect growth of the III-V semiconductor target epitaxial structure, an alternative embodiment is to first grow the III phosphide buffer layer on the silicon substrate, and then grow the III phosphide buffer layer on the silicon substrate. The adaptation layer is grown, and then the transition layer of the III-V group compound is grown on the adaptation layer, and then the target epitaxial structure of the III-V group semiconductor is grown.

Based on the content of the foregoing embodiments, as an optional embodiment, directly growing the III-V semiconductor target epitaxial structure on the adaptation layer includes: growing a III-V semiconductor with matching lattice constants on the adaptation layer -V group target semiconductor epitaxial structure, or III-V group target semiconductor epitaxial structure with the lattice mismatch degree of the adaptation layer between -5.2% and -7.8%.

When the III-V semiconductor target epitaxial structure is directly grown on the adaptation layer, if the lattice mismatch between the III-V target semiconductor epitaxial structure and the adaptation layer is between -5.2% and -7.8%, the Periodic interface resident defects are generated at the interface between the adaptation layer and the III-V group semiconductor target epitaxial structure, and the stress between the III-V group semiconductor target epitaxial structure and the adaptation layer is released. However, if the lattice mismatch between the III-V group semiconductor epitaxial structure and the adaptation layer is 0, that is, the lattice constants of the adaptation layer and the III-V group semiconductor target epitaxial structure are exactly the same, then the adaptation layer and the adaptation layer have the same lattice constant. Naturally no stress is generated between the III-V semiconductor target epitaxial structures.

与

之间的III-V族化合物外延层。Based on the content of the foregoing embodiment, as an optional embodiment, the adaptation layer has a sphalerite crystal structure, and the lattice constant is between

and

between the III-V compound epitaxial layers.

That is, the lattice mismatch between the adaptation layer and silicon is between +5.2% and +11.5%, including but not limited to, the ternary system III arsenide adaptation layer with adjustable composition and the binary system Group III arsenide adaptation layer. Periodic interface resident defects are generated at the interface between the adaptation layer and the silicon substrate or the group III phosphide buffer layer, thereby releasing the stress between the adaptation layer and the silicon substrate.

When the III-V semiconductor target epitaxial structure is directly grown on the adaptation layer, if the lattice mismatch between the III-V target semiconductor epitaxial structure and the adaptation layer is between -5.2% and -7.8%, the Periodic interface resident defects are generated at the interface between the adaptation layer and the III-V semiconductor target epitaxial structure, releasing the stress between the III-V semiconductor target epitaxial structure and the adaptation layer; and if the III-V semiconductor target epitaxial structure is The lattice mismatch between the epitaxial structure and the adaptation layer is 0, that is, the lattice constant of the adaptation layer and the III-V semiconductor target epitaxial structure are exactly the same, then the adaptation layer and the III-V semiconductor target epitaxial structure Naturally there is no stress between them.

Based on the content of the foregoing embodiment, as an optional embodiment, the material of the adaptation layer is In _x1 Ga _1-x1 As (0.15≤x1≤1) or Inx2 Al _{1-x2 As} (0.13≤x2≤1) 1). The composition optimization value of the ternary group III arsenide adaptation layer is determined in combination with the target epitaxial structure of the III-V group semiconductor to be grown to obtain an adaptation layer with optimized composition.

The material of the ternary group III arsenide adaptation layer with adjustable composition is In _x1 Ga _1-x1 As (0.15≤x1≤1) or Inx2 Al _{1-x2 As} (0.13≤x2≤1), and the The composition optimization value of the ternary group III arsenide adaptation layer is determined in combination with the target epitaxial structure of the III-V group semiconductor to be grown to obtain an adaptation layer with optimized composition.

与

之间。具体地，构成III-V族半导体目标外延结构的材料可以是GaAs、InGaAs、InAlAs、GaAsSb、InP、InAs和GaSb等材料中的任何一种，也可以是分别与这些材料相适配的材料体系。Based on the content of the above embodiment, as an optional embodiment, the III-V semiconductor target epitaxial structure is a single-layer or multi-layer structure, and the lattice constant is between

and

between. Specifically, the material constituting the target epitaxial structure of the III-V semiconductor can be any one of GaAs, InGaAs, InAlAs, GaAsSb, InP, InAs and GaSb, etc., or can be a material system that is suitable for these materials respectively .

Based on the content of the above embodiment, as an optional embodiment, the group III phosphide buffer layer is composed of any one or more of GaP, AlGaP or AlP, wherein the Al component in the AlGaP layer is y1, and the Ga group is y1. Divided into y2, and y1+y2=1, 0<y1, y2<1, the lattice mismatch between the group III phosphide buffer layer and silicon is between 0.368% and 0.372%.

Specifically, the group III phosphide buffer layer may be a single-layer structure composed of any one of GaP, AlGaP, and AlP, or a multi-layer structure composed of two or three materials of GaP, AlGaP, and AlP, Among them, several AlGaP layers of different compositions may be included.

Based on the content of the foregoing embodiments, as an optional embodiment, growing a group III phosphide buffer layer on a silicon substrate includes:

Grow a 5-50nm GaP buffer layer at a low temperature of 350-450℃;

Grow a GaP buffer layer of 0-150nm at a high temperature of 500-750℃;

Growing the adaptation layer on the Group III phosphide buffer layer includes:

A In _0.15 Ga _0.85 As adaptation layer with a thickness of 0.5 to 30 nm and an In composition of 0.15 was grown at 400 to 500 °C;

A III-V compound transition layer is grown on the adaptation layer, including:

A low-temperature GaAs buffer layer with a thickness of 10nm-100nm is grown at 400-550℃ as a transition layer;

Growing the III-V semiconductor target epitaxial structure on the III-V compound transition layer includes:

GaAs and a material system suitable for GaAs are grown at 580-730 ℃, and the preparation of the target epitaxial structure of GaAs series semiconductor on silicon is completed.

Based on the content of the foregoing embodiment, as an optional embodiment, the adaptation layer is directly grown on the silicon substrate, including:

Growing an InP adaptation layer with a thickness of 0.5-30 nm at 400-500 °C;

Directly growing a III-V semiconductor target epitaxial structure on the adaptation layer, including:

InP and a material system suitable for InP are grown at 580-730 ℃, and the preparation of the target epitaxial structure of InP-based semiconductor on silicon is completed.

Based on the content of the foregoing embodiments, as an optional embodiment, growing a group III phosphide buffer layer on a silicon substrate includes:

Growth of 5-50nm AlP buffer layer at low temperature of 350-450℃;

Continue to grow AlP buffer layer of 0-150nm at high temperature of 500-750℃;

Growing the adaptation layer on the Group III phosphide buffer layer includes:

growing an In _0.73 Ga _0.27 As adaptation layer with a thickness of 0.5-30 nm at 400-500 ℃;

Growth of III-V semiconductor target epitaxial structures on the adaptation layer, including:

GaAs and a material system suitable for GaAs are grown at 400-750 ℃, and the preparation of the target epitaxial structure of GaAs series semiconductor on silicon is completed.

Based on the contents of the foregoing embodiments, as an optional embodiment, the silicon substrate is a pure silicon substrate or a silicon-on-insulator (SOI) substrate. Further optionally, a pattern can be etched on the surface of the silicon substrate.

与

之间。具体地，构成III-V族半导体目标外延结构的材料可以是GaAs、InGaAs、InAlAs、GaAsSb、InP、InAs和GaSb等材料中的任何一种，也可以是分别与这些材料相适配的材料体系。The III-V semiconductor target epitaxial structure is a single-layer or multi-layer structure, and the lattice constant is between

and

between. Specifically, the material constituting the target epitaxial structure of the III-V semiconductor can be any one of GaAs, InGaAs, InAlAs, GaAsSb, InP, InAs and GaSb, etc., or can be a material system that is suitable for these materials respectively .

Epitaxial growth can be performed using molecular beam epitaxy (MBE) and/or metal organic chemical vapor deposition (MOCVD) equipment.

The embodiment of the present invention also provides a III-V semiconductor epitaxial structure on silicon prepared by any of the above method embodiments. The III-V semiconductor epitaxial structure on silicon is used for preparing silicon-based photonics devices or silicon-based electronic devices, and the silicon-based photonics devices include silicon-based III-V semiconductor lasers, silicon-based III-V ultra Radiation light-emitting diodes, silicon-based III-V light-emitting diodes, silicon-based III-V optical amplifiers, silicon-based III-V photodetectors, or silicon-based III-V passive devices.

In conjunction with the above-mentioned method embodiments, the following specific examples are used to further illustrate the embodiments of the present invention. It should be noted that the following examples are used to describe the embodiments of the present invention in combination with the prior art, rather than limiting the methods of the embodiments of the present invention.

Example 1:

The following description is to use the MOCVD epitaxial growth method to prepare the GaAs-based semiconductor epitaxial structure on silicon, but it is not limited to MOCVD. In this example, the group III phosphide uses GaP material, the group III arsenide uses InGaAs material, the MOCVD carrier gas is high-purity hydrogen, the group III organic source is high-purity trimethylgallium and trimethylindium, and the group V source is High-purity arsine, phosphine, the reaction chamber pressure is 100 Torr.

3 is a schematic diagram of an epitaxial structure of a GaAs-based semiconductor on silicon incorporating an adaptation layer provided by an embodiment of the present invention, including:

Silicon substrate 301; GaP low temperature nucleation layer 302 arranged on the silicon substrate 301; GaP high temperature buffer layer 303 arranged on the GaP low temperature buffer layer 302; In _0.15 Ga _0.85 As arranged on the GaP high temperature buffer layer 303 The matching layer 305; the periodic interface resident defect 304 arranged at the interface of the GaP high temperature buffer layer 303 and the In _0.15 Ga _0.85 As adaptation layer 305; the low temperature GaAs buffer layer 306 arranged on the In _0.15 Ga _0.85 As adaptation layer 305 ; the n-type GaAs ohmic contact layer 307 arranged on the low temperature GaAs buffer layer 306; the n-type Al _0.4 Ga _0.6 As lower confinement layer 308 _arranged on the n-type GaAs ohmic contact layer 307 _; Al _0.1 Ga _0.9 As lower waveguide layer 309 on the lower confinement layer 308 ; GaAs quantum well active region 310 arranged on the Al _0.1 Ga _0.9 As lower waveguide layer 309 ; Al _0.1 arranged on the GaAs quantum well active region 310 _Ga0.9As upper waveguide layer 311; p-type _Al0.4Ga0.6As upper _confinement layer 312 disposed on _Al0.1Ga0.9As upper waveguide layer ₃₁₁ ; p-type _Al0.4Ga0.6As upper _confinement layer 312 disposed GaAs ohmic contact layer 313;. In this example, the materials of each layer are shown in Figure 3, and the specific preparation steps are as follows:

Growing a GaP low temperature nucleation layer on a clean single crystal silicon substrate may include: cleaning the single crystal silicon substrate by a wet chemical cleaning method, placing the cleaned single crystal silicon substrate in a MOCVD growth chamber, and then The silicon substrate was heated to 220 °C for 30 minutes in a hydrogen atmosphere; then it was heated to 950 °C for 15 minutes in a mixed gas atmosphere of hydrogen and phosphine; finally, the temperature was lowered to 450 °C to grow a 5nm low-temperature nucleation layer of GaP. The ratio of the source to the three-family source is 20;

Growing a GaP high-temperature buffer layer on the GaP low-temperature nucleation layer may include: first, the temperature is raised to 675° C. for 10 minutes, and a GaP high-temperature buffer layer of 20 nm is grown, wherein the ratio of the Group V source to the Group III source is 10;

Growing the In _0.15 Ga _0.85 As adaptation layer on the GaP high temperature buffer layer may include: first maintaining the atmosphere of trimethyl gallium for 15 minutes, then reducing the temperature to 470° C., growing 1 nm In _0.15 Ga of In composition 0.15 _0.85 As adaptation layer; in the growth process of this layer, in order to generate high-quality and periodic interface resident defects (as shown in Figure 1), it is necessary to ensure a relatively slow growth rate, and the growth rate is 0.3 molecular layers per second. The ratio of the source to the three-family source is 10;

Growing a low-temperature GaAs buffer layer on the In _0.15 Ga _0.85 As adaptation layer may include: at a temperature of 400-550 ℃, setting the ratio of the As source to the III-group Ga source to 50, and growing 30 nm GaAs;

A material system suitable for GaAs is grown on the low-temperature GaAs buffer layer, which can be a GaAs-based quantum well laser structure, including the following steps:

At 680°C, grow an n-type GaAs ohmic contact layer with a thickness of 1 μm with a doping concentration of 2×10 ¹⁸ /cm ³ ;

At 680℃, grow an n-type Al _0.4 Ga _0.6 As lower confinement layer with a thickness of 1.5 μm, and the doping concentration is 2×10 ¹⁸ /cm ³ ;

At 680℃, the undoped Al _0.1 Ga _0.9 As lower waveguide layer was grown with a thickness of 100 nm;

At 680℃, the undoped GaAs quantum well active region with a thickness of 10nm was grown;

At 680°C, a 100nm-thick undoped Al _0.1 Ga _0.9 As upper waveguide layer was grown;

At 680℃, a p-type Al _0.4 Ga _0.6 As upper confinement layer with a thickness of 1.5 μm was grown with a doping concentration of 2×10 ¹⁸ /cm ³ ;

At 680°C, a p-type GaAs ohmic contact layer with a thickness of 200 nm was grown with a doping concentration of 2×10 ¹⁹ /cm ³ .

Example 2:

The following description is to use the MOCVD epitaxial growth method to prepare the InP-based semiconductor epitaxial structure on silicon, but it is not limited to MOCVD. In this example, the group III arsenide uses InGaAs material, the MOCVD carrier gas is high-purity hydrogen, the group III organic source is high-purity trimethylgallium, trimethylindium, the group V source is high-purity arsine, phosphine, The reaction chamber pressure was 100 Torr.

4 is a schematic diagram of an epitaxial structure of an InP-based semiconductor on silicon incorporating an adaptation layer provided by an embodiment of the present invention, and the structure includes:

Silicon substrate 401; adaptation layer 402 disposed on silicon substrate 401; periodic interface resident defect 403 disposed at the interface between substrate 401 and adaptation layer 402; InP semiconductor epitaxy disposed on adaptation layer 402 Structure 404 . In this example, the materials of each layer are shown in Figure 4, and the specific preparation steps are as follows:

Directly growing the InP adaptation layer on the cleaned single crystal silicon substrate may include: cleaning the single crystal silicon substrate by a wet chemical cleaning method, placing the cleaned single crystal silicon substrate in a MOCVD growth chamber, and then The silicon substrate is heated to 220°C for 30 minutes in a hydrogen atmosphere; then heated to 950°C for 15 minutes in a mixed gas atmosphere of hydrogen and phosphine; finally, the temperature is lowered to 450°C to grow an InP adaptation layer, which may include: The atmosphere of trimethylgallium was maintained for 15 minutes, and then the temperature was lowered to 470 °C to grow a 1 nm InP adaptation layer; during the growth of this layer, in order to generate high-quality, periodic interface resident defects (as shown in Figure 1) , it is necessary to ensure a relatively slow growth rate, the growth rate is 0.3 molecular layers per second, and the ratio of the five-group source to the three-group source is 10;

Growing a material system suitable for InP on the In _0.53 Ga _0.47 As adaptation layer may include: growing an InP epitaxial layer with a thickness of 100 nm at 680° C., and then continuing to grow other materials on the InP epitaxial layer.

Example 3:

The following description is to use the MOCVD epitaxial growth method to prepare the GaAs-based semiconductor epitaxial structure on silicon, but it is not limited to MOCVD. In this example, the group III phosphide uses Al _0.2 Ga _0.8 P material, the group III arsenide uses the InAs material, the MOCVD carrier gas is high-purity hydrogen, the group III organic source is high-purity trimethyl gallium, trimethyl indium, Group V sources are high-purity arsine and phosphine, and the pressure in the reaction chamber is 100 Torr.

5 is a schematic diagram of an epitaxial structure of a GaAs-based semiconductor on silicon that introduces dual-interface resident defects according to an embodiment of the present invention, and the structure includes:

Silicon substrate 501; a group III phosphide low temperature nucleation layer 502 disposed on the silicon substrate 501; a group III phosphide high temperature buffer layer 503 disposed on the group III phosphide low temperature buffer layer 502; disposed on the group III phosphide The adaptation layer 505 on the high temperature buffer layer 503; the periodic interface resident defect 504 disposed at the interface of the III phosphide high temperature buffer layer 503 and the adaptation layer 505; the GaAs-based semiconductor epitaxial structure disposed on the adaptation layer 505 507; Periodic interface resident defects 506 disposed on the adaptation layer 505 at the interface with the GaAs-based semiconductor epitaxial structure 507. In this example, the materials of each layer are shown in Figure 5, and the specific preparation steps are as follows:

Growing an AlP low-temperature nucleation layer on a clean single-crystal silicon substrate may include: cleaning the single-crystal silicon substrate by a wet chemical cleaning method, placing the cleaned single-crystal silicon substrate in a MOCVD growth chamber, and then The silicon substrate was heated to 220°C for 30 minutes in a hydrogen atmosphere; then heated to 950°C for 15 minutes in a mixed gas atmosphere of hydrogen and phosphine; finally, the temperature was lowered to 450°C to grow a 5nm AlP low-temperature nucleation layer. The ratio of the source to the three-family source is 20;

Growing an AlP high-temperature buffer layer on the AlP low-temperature nucleation layer may include: first, the temperature is raised to 675° C. for 10 minutes, and a 20 nm AlP high-temperature buffer layer is grown, wherein the ratio of the Group V source to the Group III source is 10;

Growing an In _0.73 Ga _0.27 As adaptation layer with an In composition of 0.73 on the AlP high temperature buffer layer may include: first maintaining the atmosphere of trimethyl gallium for 15 minutes, then reducing the temperature to 470 °C, and growing 50 nm of In _0.73 Ga _0.27 As adaptation layer; in the growth process of this layer, in order to generate high-quality, periodic interface resident defects (as shown in Figure 1), it is necessary to ensure a relatively slow growth rate, the growth rate is 0.3 molecular layers per second, five The ratio of clan source to three clan source is 10;

Growing a material system suitable for GaAs on the In _0.73 Ga _0.27 As adaptation layer may include: first maintaining the atmosphere of trimethyl gallium for 15 minutes, and then maintaining the temperature at 470 ° C, growing 1 nm can produce interface retention GaAs layer with defects; in the growth process of this layer, in order to generate high-quality, periodic interface resident defects (as shown in Figure 1), it is necessary to ensure a relatively slow growth rate, and the growth rate is 0.3 molecular layers per second. The ratio of the source to the Group III source is 10; then the temperature is raised to 680° C. to grow a GaAs epitaxial layer with a thickness of 100 nm, after which other materials can be grown on the GaAs epitaxial layer.

Example 4:

The following description is to use the MOCVD epitaxial growth method to prepare the GaSb-based semiconductor epitaxial structure on silicon, but it is not limited to MOCVD. In this example, the group III phosphide is made of Al _0.2 Ga _0.8 P material, the group III arsenide is made of InAs material, the MOCVD carrier gas is high-purity hydrogen, and the group III organic source is high-purity trimethyl gallium, trimethyl indium, Group V sources are high-purity arsine and phosphine, and the pressure in the reaction chamber is 100 Torr.

6 is a schematic diagram of an epitaxial structure of a GaSb-based semiconductor on silicon incorporating an adaptation layer provided by an embodiment of the present invention, and the structure includes:

Silicon substrate 601; a group III phosphide low temperature nucleation layer 602 disposed on the silicon substrate 601; a group III phosphide high temperature buffer layer 603 disposed on the group III phosphide low temperature buffer layer 602; disposed on the group III phosphide The adaptation layer 605 on the high temperature buffer layer 603 ; the periodic interface resident defect 604 disposed at the interface between the group III phosphide high temperature buffer layer 603 and the adaptation layer 605 ; the GaSb-based semiconductor epitaxial structure disposed on the adaptation layer 605 606. In this example, the materials of each layer are shown in Figure 6, and the specific preparation steps are as follows:

Growing an Al _0.2 Ga _0.8 P low-temperature nucleation layer on a clean single-crystal silicon substrate may include: cleaning the single-crystal silicon substrate by a wet chemical cleaning method, and placing the cleaned single-crystal silicon substrate into a MOCVD growth chamber In the chamber, the silicon substrate was heated to 220 °C for 30 minutes in a hydrogen atmosphere; then heated to 950 °C for 15 minutes in a mixed gas atmosphere of hydrogen and phosphine; finally, the temperature was lowered to 450 °C to grow 5 nm Al _0.2 Ga _0.8 P low-temperature nucleation layer, the ratio of the fifth group source to the third group source is 20;

Growing the Al _0.2 Ga _0.8 P high-temperature buffer layer on the Al _0.2 Ga _0.8 P low-temperature nucleation layer may include: first, the temperature is raised to 675° C. for 10 minutes, and a 20 nm Al _0.2 Ga _0.8 P high-temperature buffer layer is grown, wherein the Group V source and The ratio of the three sources is 10;

Growing an InAs adaptation layer on the Al _0.2 Ga _0.8 P high temperature buffer layer may include: first maintaining the atmosphere of trimethyl gallium for 15 minutes, then reducing the temperature to 470°C, and growing a 0.5 nm InAs adaptation layer; this layer During the growth process, in order to generate high-quality and periodic interface resident defects (as shown in Figure 1), it is necessary to ensure a relatively slow growth rate, the growth rate is 0.3 molecular layers per second, and the ratio of the five-group source to the three-group source is 10;

Growing a material system suitable for GaSb on the InAs adaptation layer may include: growing a GaSb epitaxial layer with a thickness of 100 nm at 680° C., and then continuing to grow other materials on the GaSb epitaxial layer.

FIG. 7 is a schematic flowchart of a method for preparing a III-V semiconductor epitaxial structure on silicon provided by another embodiment of the present invention, and details can be found in the above method embodiments.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand: it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or some technical features thereof are equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. a preparation method of III-V group semiconductor epitaxial structure on silicon is characterized in that, comprising: Directly or indirectly growing the adaptation layer on the silicon substrate; directly or indirectly growing a III-V semiconductor target epitaxial structure on the adaptation layer; Wherein, the adaptation layer includes a ternary system III group arsenide adaptation layer or a binary system III-V group compound adaptation layer. 2. the preparation method of the III-V semiconductor epitaxial structure on silicon according to claim 1, is characterized in that, on the silicon substrate, the indirect growth adaptation layer comprises: After growing the III-phosphide buffer layer on the silicon substrate, the adaptation layer is grown on the III-phosphide buffer layer. 3. the preparation method of the III-V semiconductor epitaxial structure on silicon according to claim 1 or 2, is characterized in that, Directly growing a III-V group semiconductor target epitaxial structure on the adaptation layer includes: growing a III-V group target semiconductor epitaxial structure with matching lattice constants on the adaptation layer, or the adaptation layer has a lattice loss The III-V target semiconductor epitaxial structure with the proportion between -5.2% and -7.8%; The indirect growth of the III-V semiconductor target epitaxial structure on the adaptation layer includes: after growing the III-V compound transition layer on the adaptation layer, growing the III-V compound transition layer on the III-V compound transition layer. The III-V semiconductor target epitaxial structure is described. 4. The method for preparing a III-V semiconductor epitaxial structure on silicon according to claim 1 or 2, wherein the adaptation layer has a zinc blende crystal structure, and the lattice constant is between

and

between III-V compound epitaxial layers; Or the material of the adaptation layer is In _x1 Ga _1-x1 As or In _x2 Al _1-x2 As; the composition optimization value of the ternary group III arsenide adaptation layer is combined with the III-V group to be grown The semiconductor target epitaxial structure is determined; Among them, 0.15≤x1≤1, 0.13≤x2≤1. 5. The method for preparing a III-V semiconductor epitaxial structure on silicon according to claim 1 or 2, wherein the III-V semiconductor target epitaxial structure is a single-layer or multi-layer structure, and has a lattice constant between

and

between. 6. The method for preparing a III-V semiconductor epitaxial structure on silicon according to claim 2, wherein the III-phosphide buffer layer is composed of any one or more of GaP, AlGaP or AlP, wherein In the AlGaP layer, the Al composition is y1, the Ga composition is y2, and y1+y2=1, 0<y1, y2<1, the lattice mismatch between the group III phosphide buffer layer and silicon is 0.368% ~0.372%. 7. the preparation method of III-V semiconductor epitaxial structure on silicon according to claim 3, is characterized in that: Growth of a group III phosphide buffer layer on a silicon substrate, including: Grow a 5-50nm GaP buffer layer at a low temperature of 350-450℃; Grow a GaP buffer layer of 0-150nm at a high temperature of 500-750℃; Growing the adaptation layer on the Group III phosphide buffer layer includes: A In _0.15 Ga _0.85 As adaptation layer with a thickness of 0.5 to 30 nm and an In composition of 0.15 was grown at 400 to 500 °C; A III-V compound transition layer is grown on the adaptation layer, including: A low-temperature GaAs buffer layer with a thickness of 10nm-100nm is grown at 400-550℃ as a transition layer; Growing the III-V semiconductor target epitaxial structure on the III-V compound transition layer includes: GaAs and a material system suitable for GaAs are grown at 580-730 ℃, and the preparation of the target epitaxial structure of GaAs series semiconductor on silicon is completed. 8. The method for preparing a III-V semiconductor epitaxial structure on silicon according to claim 1, wherein the adapting layer is directly grown on the silicon substrate, comprising: Growing an InP adaptation layer with a thickness of 0.5-30 nm at 400-500 °C; Directly growing a III-V semiconductor target epitaxial structure on the adaptation layer, including: InP and a material system suitable for InP are grown at 580-730 ℃, and the preparation of the target epitaxial structure of InP-based semiconductor on silicon is completed. 9. the preparation method of III-V semiconductor epitaxial structure on silicon according to claim 2, is characterized in that: Growth of a group III phosphide buffer layer on a silicon substrate, including: Growth of 5-50nm AlP buffer layer at low temperature of 350-450℃; Continue to grow AlP buffer layer of 0-150nm at high temperature of 500-750℃; Growing the adaptation layer on the Group III phosphide buffer layer includes: growing an In _0.73 Ga _0.27 As adaptation layer with a thickness of 0.5-30 nm at 400-500 ℃; Growth of III-V semiconductor target epitaxial structures on the adaptation layer, including: GaAs and a material system suitable for GaAs are grown at 400-750 ℃ to complete the preparation of the target epitaxial structure of GaAs series semiconductor on silicon. 10. A III-V semiconductor epitaxial structure on silicon, characterized in that, it is prepared by the preparation method of the III-V semiconductor epitaxial structure on silicon described in any one of claims 1-9; The III-V semiconductor epitaxial structure on silicon is used to prepare a silicon-based photonics device or a silicon-based electronic device, and the silicon-based photonics device includes: Silicon-based III-V semiconductor lasers, silicon-based III-V superluminescent diodes, silicon-based III-V light-emitting diodes, silicon-based III-V optical amplifiers, silicon-based III-V photodetectors, or silicon-based III-V photodetectors - Group V passive devices.

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