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CN114556550A - Double-sided cooling power package structure - Google Patents

Double-sided cooling power package structure Download PDF

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Publication number
CN114556550A
CN114556550A CN202180004154.6A CN202180004154A CN114556550A CN 114556550 A CN114556550 A CN 114556550A CN 202180004154 A CN202180004154 A CN 202180004154A CN 114556550 A CN114556550 A CN 114556550A
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CN
China
Prior art keywords
package structure
cooling
cooling substrate
power package
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202180004154.6A
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Chinese (zh)
Inventor
资重兴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Luxemburg Dahl International Ltd By Share Ltd
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Lite On Semiconductor Corp
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Filing date
Publication date
Application filed by Lite On Semiconductor Corp filed Critical Lite On Semiconductor Corp
Publication of CN114556550A publication Critical patent/CN114556550A/en
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The invention provides a double-sided cooling power packaging structure which comprises a first cooling substrate, a second cooling substrate, at least one semiconductor chip and a plurality of first conductive strips. The second cooling substrate is arranged opposite to the first cooling substrate. The semiconductor wafer is bonded to one of the first cooling substrate and the second cooling substrate. The first conductive strips are disposed between the first and second cooled substrates, wherein each first conductive strip includes a first portion, a second portion, and a bendable portion connecting the first and second portions. The bendable portion forms a closed loop at an edge of the first portion. One of the first and second portions is in direct contact with the semiconductor wafer, while the other of the first and second portions extends away from the semiconductor wafer.

Description

双面冷却功率封装结构Double-sided cooling power package structure

技术领域technical field

本发明涉及一种功率封装结构，且特别是涉及一种双面冷却功率封装结构。The present invention relates to a power packaging structure, and in particular, to a double-sided cooling power packaging structure.

背景技术Background technique

功率器件一般在操作期间会产生大量的热，因此散热问题是待改善的主要议题之一。Power devices generally generate a lot of heat during operation, so heat dissipation is one of the main issues to be improved.

近来，一种双面冷却功率封装结构已被广泛应用为有效的散热器(heat sink)。例如，在功率器件的两面上设置两个散热器，因此能提高散热效率。Recently, a double-sided cooling power package structure has been widely used as an effective heat sink. For example, two heat sinks are provided on both sides of the power device, so that the heat dissipation efficiency can be improved.

然而，如果双面冷却功率封装结构因为热膨胀系数的差异而遭遇压应力以及/或是热应力，则其可能会被破裂或损坏However, if the double-sided cooled power package structure experiences compressive and/or thermal stress due to differences in thermal expansion coefficients, it may be cracked or damaged

发明内容SUMMARY OF THE INVENTION

本发明是针对一种双面冷却功率封装结构，能解决压应力以及/或是热应力所导致的问题。The present invention is directed to a double-sided cooling power package structure, which can solve the problems caused by compressive stress and/or thermal stress.

本发明的双面冷却功率封装结构包括第一冷却基板、第二冷却基板、至少一半导体晶片以及多个第一导电带(conduction ribbons)。所述第二冷却基板与所述第一冷却基板相对设置。所述半导体晶片接合在第一冷却基板和第二冷却基板其中一个上。所述第一导电带设置在第一冷却基板与第二冷却基板之间，其中每个第一导电带包括第一部分、第二部分以及连接所述第一部分和所述第二部分的可弯曲部分(bendable portion)。所述可弯曲部分在所述第一部分的边缘形成闭环(closed loop)。第一部分和第二部分中的一个与所述半导体晶片直接接触，而第一部分和第二部分中的另一个远离所述半导体晶片延伸。The double-sided cooling power package structure of the present invention includes a first cooling substrate, a second cooling substrate, at least one semiconductor chip, and a plurality of first conduction ribbons. The second cooling substrate is disposed opposite to the first cooling substrate. The semiconductor wafer is bonded to one of the first cooling substrate and the second cooling substrate. The first conductive strips are disposed between the first cooling substrate and the second cooling substrate, wherein each first conductive strip includes a first portion, a second portion, and a bendable portion connecting the first portion and the second portion (bendable portion). The bendable portion forms a closed loop at the edge of the first portion. One of the first portion and the second portion is in direct contact with the semiconductor wafer, while the other of the first portion and the second portion extends away from the semiconductor wafer.

在本发明的一实施例中，所述第一导电带是不连续结构。In an embodiment of the present invention, the first conductive strip is a discontinuous structure.

在本发明的一实施例中，所述第一导电带是连续结构。In an embodiment of the present invention, the first conductive strip is a continuous structure.

在本发明的一实施例中，所述第一部分与所述半导体晶片直接接触。In an embodiment of the invention, the first portion is in direct contact with the semiconductor wafer.

在本发明的一实施例中，所述第一部分经由第一焊料连结至所述半导体晶片。In an embodiment of the invention, the first portion is attached to the semiconductor die via a first solder.

在本发明的一实施例中，所述半导体晶片接合在所述第一冷却基板上，且每个第一导电带的所述第二部分与所述第二冷却基板直接接触。In one embodiment of the invention, the semiconductor wafer is bonded to the first cooling substrate, and the second portion of each first conductive strip is in direct contact with the second cooling substrate.

在本发明的一实施例中，所述半导体晶片接合在所述第一冷却基板上，且每个第一导电带的所述第二部分经由第二焊料连结至所述第二冷却基板。In one embodiment of the invention, the semiconductor die is bonded on the first cooling substrate, and the second portion of each first conductive strip is attached to the second cooling substrate via a second solder.

在本发明的一实施例中，所述第二部分与所述半导体晶片直接接触。In an embodiment of the invention, the second portion is in direct contact with the semiconductor wafer.

在本发明的一实施例中，所述第二部分经由第一焊料连结至所述半导体晶片。In an embodiment of the invention, the second portion is attached to the semiconductor die via a first solder.

在本发明的一实施例中，所述半导体晶片接合在所述第一冷却基板上，且每个第一导电带的所述第一部分与所述第二冷却基板直接接触。In one embodiment of the invention, the semiconductor wafer is bonded to the first cooling substrate, and the first portion of each first conductive strip is in direct contact with the second cooling substrate.

在本发明的一实施例中，所述半导体晶片接合在所述第一冷却基板上，且每个第一导电带的所述第二部分经由第二焊料连结至所述第二冷却基板。In one embodiment of the invention, the semiconductor die is bonded on the first cooling substrate, and the second portion of each first conductive strip is attached to the second cooling substrate via a second solder.

在本发明的一实施例中，所述封装结构还包括多个金属预成型体设置在所述第二冷却基板与所述半导体晶片之间，其中所述金属预成型体与所述第二冷却基板直接接触，且第一部分和第二部分中的一个设置在所述金属预成型体与所述半导体晶片之间。In an embodiment of the present invention, the package structure further includes a plurality of metal preforms disposed between the second cooling substrate and the semiconductor wafer, wherein the metal preforms and the second cooling The substrates are in direct contact, and one of the first portion and the second portion is disposed between the metal preform and the semiconductor wafer.

在本发明的一实施例中，所述封装结构还包括至少一第二导电带设置在所述第一冷却基板与所述第二冷却基板之间，其中所述第二导电带具有与每个第一导电带相同的形状，且所述第二导电带不接触所述半导体晶片。In an embodiment of the present invention, the package structure further includes at least one second conductive strip disposed between the first cooling substrate and the second cooling substrate, wherein the second conductive strip has a The first conductive strips are of the same shape, and the second conductive strips do not contact the semiconductor wafer.

在本发明的一实施例中，所述第二导电带与所述第一导电带是不连续结构。In an embodiment of the present invention, the second conductive strip and the first conductive strip are discontinuous structures.

在本发明的一实施例中，所述第二导电带与所述第一导电带是连续结构。In an embodiment of the present invention, the second conductive strip and the first conductive strip are continuous structures.

在本发明的一实施例中，所述第一冷却基板与所述第二冷却基板是直接覆铜陶瓷(Direct bonded copper，DBC)基板。In an embodiment of the present invention, the first cooling substrate and the second cooling substrate are direct bonded copper (DBC) substrates.

基于上述，本发明在双面冷却功率封装结构中提供了一种特定的导电带。具体而言，所述导电带的可弯曲部分在热压缩过程中会发生弹性变形，因此能吸收不同材料之间的热压缩与热应力所产生的应力。因此，可改善封装结构和半导体晶片的坚固性(robustness)。此外，本发明在工艺成本(仅需一次或两次回流焊接步骤)和理想的散热性能方面也具有优势。Based on the above, the present invention provides a specific conductive tape in the double-sided cooling power package structure. Specifically, the bendable portion of the conductive tape is elastically deformed during the thermal compression process, and thus can absorb the stress generated by thermal compression and thermal stress between different materials. Therefore, the robustness of the package structure and the semiconductor wafer can be improved. In addition, the present invention also has advantages in terms of process cost (only one or two reflow soldering steps are required) and ideal heat dissipation performance.

为使前述内容更易于理解，以下结合附图对数个实施例进行详细说明。In order to make the foregoing content easier to understand, several embodiments are described in detail below with reference to the accompanying drawings.

附图说明Description of drawings

所附附图提供对本发明的进一步理解，并且被并入并构成说明书的一部分。所附附图显示了本发明的示例性实施例并且与描述一起用于解释本发明的原理。The appended drawings provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate exemplary embodiments of the invention and together with the description serve to explain the principles of the invention.

图1A是依照本发明的第一实施例的一种双面冷却功率封装结构的侧视示意图。1A is a schematic side view of a double-sided cooling power package structure according to the first embodiment of the present invention.

图1B是图1A的双面冷却功率封装结构中的第一导电带的立体图。FIG. 1B is a perspective view of the first conductive strip in the double-sided cooling power package structure of FIG. 1A .

图2是依照本发明的第二实施例的一种双面冷却功率封装结构的侧视示意图。2 is a schematic side view of a double-sided cooling power package structure according to a second embodiment of the present invention.

图3是依照本发明的第三实施例的一种双面冷却功率封装结构的侧视示意图。3 is a schematic side view of a double-sided cooling power package structure according to a third embodiment of the present invention.

图4是依照本发明的第四实施例的一种双面冷却功率封装结构的侧视示意图。4 is a schematic side view of a double-sided cooling power package structure according to a fourth embodiment of the present invention.

图5是依照本发明的第五实施例的一种双面冷却功率封装结构的侧视示意图。5 is a schematic side view of a double-sided cooling power package structure according to a fifth embodiment of the present invention.

图6是依照本发明的第六实施例的一种双面冷却功率封装结构的侧视示意图。6 is a schematic side view of a double-sided cooling power package structure according to a sixth embodiment of the present invention.

图7是依照本发明的第七实施例的一种双面冷却功率封装结构的侧视示意图。7 is a schematic side view of a double-sided cooling power package structure according to a seventh embodiment of the present invention.

图8是依照本发明的第八实施例的一种双面冷却功率封装结构的侧视示意图。8 is a schematic side view of a double-sided cooling power package structure according to an eighth embodiment of the present invention.

图9是依照本发明的第九实施例的一种双面冷却功率封装结构的侧视示意图。9 is a schematic side view of a double-sided cooling power package structure according to a ninth embodiment of the present invention.

附图标号说明Explanation of reference numerals

10、20、30、40、50、60、70、80、90：双面冷却功率封装结构10, 20, 30, 40, 50, 60, 70, 80, 90: Double-sided cooling power package structure

100：第一冷却基板100: First cooling substrate

100a、102a：上金属层100a, 102a: upper metal layer

100b、102b：下金属层100b, 102b: lower metal layer

100c、102c：介电板100c, 102c: Dielectric plate

102：第二冷却基板102: Second cooling substrate

104：半导体晶片104: Semiconductor wafers

106：第一导电带106: First Conductive Strip

106a、400a、800a：第一部分106a, 400a, 800a: Part 1

106b、400b、800b：第二部分106b, 400b, 800b: Part II

106c、400c、800c：可弯曲部分106c, 400c, 800c: Bendable part

108、200、602、700、802、902：焊料108, 200, 602, 700, 802, 902: Solder

400、800：第二导电带400, 800: Second conductive tape

600、900：金属预成型体600, 900: Metal Preforms

E：边缘E: edge

h：高度差h: height difference

t1、t2：厚度t1, t2: thickness

具体实施方式Detailed ways

以下将参考实施例和附图来充分理解本发明。然而，本发明仍可以按照多种不同形式来实施，且不应被解释为限于下文描述的实施例。在附图中，为了清楚起见，器件及其相对尺寸可能不按比例缩放。为便于理解，以下实施例中相同的器件可采用相同的附图标记表示。The present invention will be fully understood below with reference to the examples and the accompanying drawings. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments described below. In the drawings, devices and their relative sizes may not be to scale for clarity. For ease of understanding, the same components in the following embodiments may be denoted by the same reference numerals.

图1A是依照本发明的第一实施例的一种双面冷却功率封装结构的侧视示意图。图1B是图1A的双面冷却功率封装结构中的第一导电带的立体图。1A is a schematic side view of a double-sided cooling power package structure according to the first embodiment of the present invention. FIG. 1B is a perspective view of the first conductive strip in the double-sided cooling power package structure of FIG. 1A .

请参照图1A与图1B，第一实施例的双面冷却功率封装结构10包括第一冷却基板100、第二冷却基板102、至少一半导体晶片104以及多个第一导电带106。所述第二冷却基板102与所述第一冷却基板100相对设置。在本实施例中，所述第一冷却基板100与所述第二冷却基板102例如是直接覆铜陶瓷(DBC)基板。第一冷却基板100至少包括上金属层100a、下金属层100b以及位在上金属层100a与下金属层100b之间的介电板100c。第二冷却基板102至少包括上金属层102a、下金属层102b以及位在上金属层102a与下金属层102b之间的介电板102c。所述半导体晶片104经由一焊料108接合在第一冷却基板100上，但本发明并不限于此；在另一实施例中，半导体晶片104是通过超声波压缩(ultrasonic compression，UC)接合在第一冷却基板100上。所述半导体晶片104例如是IGBT、MOSFET、快速恢复二极管(FRD)或宽带隙晶片。所述第一导电带106设置在第一冷却基板100与第二冷却基板102之间，其中每个第一导电带106包括第一部分106a、第二部分106b以及连接所述第一部分106a和所述第二部分106b的可弯曲部分(bendable portion)106c。第一导电带106以与图1A-1B所示的相同几何形状沿Y方向延伸。导电带106的材料例如铜。具体而言，第一实施例中有两条第一导电带106，且为连续结构，其中连接部是其第二部分106b，而且由于采用连续结构，预期可进一步提高所述双面冷却功率封装结构10的载流量(current capacity)和热容量(thermal capacity)。所述可弯曲部分106c于第一部分106a的边缘E形成闭环(closedloop)，且可弯曲部分106c为可弹性变形的结构，因此当双面冷却功率封装结构10受到热膨胀或压缩应力的影响时，可吸收应力或压力。在本实施例中，所述第一部分106a通过UC接合与半导体晶片104直接接触，但本发明并不限于此；在另一实施例中，第一部分106a可通过焊料(未示出)接合至半导体晶片104。所述第二部分106b远离所述半导体晶片104延伸，且每个第一导电带106的第二部分106b直接接触第二冷却基板102。由于第一导电带106与下金属层102b的材料可相同，所以所述第二部分106b与第二冷却基板102的接合方法包括UC接合或激光焊接等。然而本发明并不限于此；在另一实施例中，第二部分106b可通过焊料(未示出)接合至第二冷却基板102。另外，每个第一导电带106的尺寸可根据需求改变；例如，第一导电带106的厚度t1、半导体晶片104的厚度t2以及第二部分106b和第一部分106a之间的高度差h可以根据需要而改变。Referring to FIGS. 1A and 1B , the double-sided cooling power package structure 10 of the first embodiment includes a first cooling substrate 100 , a second cooling substrate 102 , at least one semiconductor chip 104 and a plurality of first conductive strips 106 . The second cooling substrate 102 is disposed opposite to the first cooling substrate 100 . In this embodiment, the first cooling substrate 100 and the second cooling substrate 102 are, for example, direct copper clad ceramic (DBC) substrates. The first cooling substrate 100 at least includes an upper metal layer 100a, a lower metal layer 100b, and a dielectric plate 100c located between the upper metal layer 100a and the lower metal layer 100b. The second cooling substrate 102 at least includes an upper metal layer 102a, a lower metal layer 102b, and a dielectric plate 102c located between the upper metal layer 102a and the lower metal layer 102b. The semiconductor wafer 104 is bonded to the first cooling substrate 100 via a solder 108, but the invention is not limited thereto; in another embodiment, the semiconductor wafer 104 is bonded to the first cooling substrate 100 by ultrasonic compression (UC). on the cooling substrate 100 . The semiconductor wafer 104 is, for example, an IGBT, a MOSFET, a fast recovery diode (FRD) or a wide band gap wafer. The first conductive strips 106 are disposed between the first cooling substrate 100 and the second cooling substrate 102, wherein each first conductive strip 106 includes a first portion 106a, a second portion 106b and connects the first portion 106a and the A bendable portion 106c of the second portion 106b. The first conductive strip 106 extends in the Y direction with the same geometry as shown in Figures 1A-1B. The material of the conductive strip 106 is, for example, copper. Specifically, there are two first conductive strips 106 in the first embodiment, and it is a continuous structure, wherein the connecting part is the second part 106b thereof, and due to the continuous structure, it is expected that the double-sided cooling power package can be further improved The current capacity and thermal capacity of the structure 10 . The bendable portion 106c forms a closed loop at the edge E of the first portion 106a, and the bendable portion 106c is an elastically deformable structure. Therefore, when the double-sided cooling power package structure 10 is affected by thermal expansion or compressive stress, it can Absorb stress or pressure. In this embodiment, the first portion 106a is in direct contact with the semiconductor wafer 104 by UC bonding, but the invention is not limited thereto; in another embodiment, the first portion 106a may be bonded to the semiconductor by solder (not shown) wafer 104 . The second portion 106b extends away from the semiconductor wafer 104 and the second portion 106b of each first conductive strip 106 directly contacts the second cooling substrate 102 . Since the materials of the first conductive strip 106 and the lower metal layer 102b may be the same, the bonding method of the second portion 106b and the second cooling substrate 102 includes UC bonding or laser welding. However, the present invention is not limited thereto; in another embodiment, the second portion 106b may be joined to the second cooling substrate 102 by solder (not shown). In addition, the dimensions of each first conductive strip 106 may vary as desired; for example, the thickness t1 of the first conductive strip 106, the thickness t2 of the semiconductor wafer 104, and the height difference h between the second portion 106b and the first portion 106a may be based on change as needed.

图2是依照本发明的第二实施例的一种双面冷却功率封装结构的侧视示意图，其中使用与第一实施例相同的附图标记来表示相同或近似的构件。相同或近似的构件内容也可参照上述第一实施例的相关说明，不再赘述。2 is a schematic side view of a double-sided cooling power package structure according to a second embodiment of the present invention, wherein the same reference numerals as in the first embodiment are used to denote the same or similar components. For the content of the same or similar components, reference may also be made to the relevant descriptions of the above-mentioned first embodiment, which will not be repeated.

请参照图2，第一与第二实施例的差异在于半导体晶片104与每个第一导电带106的第一部分106a之间设置有一个额外的焊料200。如果焊料200的成分与焊料108的成分相同，则第二实施例的双面冷却功率封装结构20的制造过程中可以进行单一回流焊接工艺(reflow process)。举例来说，先将焊料108施加在第一冷却基板100上，再将半导体晶片104附着在焊料108上，然后将额外的焊料200施加在第一部分106a上，层压所述第一冷却基板100和所述第二冷却基板102，以将半导体晶片104接合到焊料200，并且执行上述单一回流焊接工艺。在另一实施例中，如果焊料200的成分与焊料108的成分不同，则焊料108可以具有比焊料200更高的熔点，并且可以在制造第二实施例的双面冷却功率封装结构20的过程中进行二次回流焊接工艺。举例来说，先将焊料108施加在第一冷却基板100上，再将半导体晶片104附着在焊料108上，然后进行第一回流焊接工艺，并于第一回流焊接工艺后将额外的焊料200施加在第一部分106a上，再层压所述第一冷却基板100和所述第二冷却基板102，以将半导体晶片104接合到焊料200，并执行第二回流焊接工艺。由于焊料108的熔点高于焊料200的熔点，因此焊料108在第二回流焊接工艺期间不会熔化变形。Referring to FIG. 2 , the difference between the first and second embodiments is that an additional solder 200 is disposed between the semiconductor wafer 104 and the first portion 106 a of each of the first conductive strips 106 . If the composition of the solder 200 is the same as that of the solder 108, a single reflow process can be performed during the fabrication of the double-sided cooling power package structure 20 of the second embodiment. For example, the first cooling substrate 100 is laminated by applying the solder 108 on the first cooling substrate 100, attaching the semiconductor die 104 to the solder 108, and then applying additional solder 200 on the first portion 106a. and the second cooling substrate 102 to bond the semiconductor wafer 104 to the solder 200, and perform the single reflow soldering process described above. In another embodiment, if the composition of the solder 200 is different from the composition of the solder 108, the solder 108 may have a higher melting point than the solder 200 and may be cooled during the process of manufacturing the double-sided cooling power package structure 20 of the second embodiment A secondary reflow soldering process is carried out. For example, the solder 108 is applied on the first cooling substrate 100, the semiconductor chip 104 is attached to the solder 108, then a first reflow process is performed, and additional solder 200 is applied after the first reflow process On the first portion 106a, the first cooling substrate 100 and the second cooling substrate 102 are again laminated to bond the semiconductor wafer 104 to the solder 200, and a second reflow soldering process is performed. Since the melting point of the solder 108 is higher than the melting point of the solder 200, the solder 108 is not melted and deformed during the second reflow process.

图3是依照本发明的第三实施例的一种双面冷却功率封装结构的侧视示意图，其中使用与第一实施例相同的附图标记来表示相同或近似的构件。相同或近似的构件内容也可参照上述第一实施例的相关说明，不再赘述。3 is a schematic side view of a double-sided cooling power package structure according to a third embodiment of the present invention, wherein the same reference numerals as in the first embodiment are used to denote the same or similar components. For the content of the same or similar components, reference may also be made to the relevant descriptions of the above-mentioned first embodiment, which will not be repeated.

请参照图3，第三实施例的双面冷却功率封装结构30中的第一导电带106是不连续结构，其中不同的第一导电带106的第二部分106b是分开的。因此，根据电路的容量，半导体晶片104以及第一导电带106的位置可以改变。在另一实施例中，双面冷却功率封装结构30中的第一导电带106可以是连续结构和不连续结构的组合。Referring to FIG. 3 , the first conductive strips 106 in the double-sided cooling power package structure 30 of the third embodiment are discontinuous structures, wherein the second portions 106b of different first conductive strips 106 are separated. Therefore, depending on the capacity of the circuit, the positions of the semiconductor wafer 104 and the first conductive strip 106 may vary. In another embodiment, the first conductive strip 106 in the double-sided cooling power package structure 30 may be a combination of continuous and discontinuous structures.

图4是依照本发明的第四实施例的一种双面冷却功率封装结构的侧视示意图，其中使用与第一实施例相同的附图标记来表示相同或近似的构件。相同或近似的构件内容也可参照上述第一实施例的相关说明，不再赘述。4 is a schematic side view of a double-sided cooling power package structure according to a fourth embodiment of the present invention, wherein the same or similar components are denoted by the same reference numerals as in the first embodiment. For the content of the same or similar components, reference may also be made to the relevant descriptions of the above-mentioned first embodiment, which will not be repeated.

请参照图4，第一与第四实施例的差异在于第四实施例的双面冷却功率封装结构40中还有第二导电带400。第二导电带400设置在所述第一冷却基板100与所述第二冷却基板102之间，其中所述第二导电带400具有与每个第一导电带106相同的形状，但尺寸上可能有一点差异。举例来说，第二导电带400包括第一部分400a、第二部分400b以及连接第一部分400a和第二部分400b的可弯曲部分400c，其中第一部分400a与第一冷却基板100直接接触，而第二部分400b与第二冷却基板102直接接触。所述第二导电带400不接触半导体晶片104，因此根据电路或拓扑的设计，其可为电流和热量提供额外的路径。在本实施例中，所述第二导电带400与所述第一导电带106是连续结构，其中第二部分400b连接到一个第二部分106b。Referring to FIG. 4 , the difference between the first and fourth embodiments is that there is a second conductive strip 400 in the double-sided cooling power package structure 40 of the fourth embodiment. A second conductive strip 400 is disposed between the first cooling substrate 100 and the second cooling substrate 102, wherein the second conductive strip 400 has the same shape as each of the first conductive strips 106, but may be dimensionally There is a little difference. For example, the second conductive strip 400 includes a first portion 400a, a second portion 400b, and a bendable portion 400c connecting the first portion 400a and the second portion 400b, wherein the first portion 400a is in direct contact with the first cooling substrate 100, and the second portion 400a is in direct contact with the first cooling substrate 100. The portion 400b is in direct contact with the second cooling substrate 102 . The second conductive strip 400 does not contact the semiconductor wafer 104 and thus may provide additional paths for current and heat depending on the design of the circuit or topology. In this embodiment, the second conductive strip 400 and the first conductive strip 106 are continuous structures, wherein the second portion 400b is connected to one second portion 106b.

图5是依照本发明的第五实施例的一种双面冷却功率封装结构的侧视示意图，其中使用与第四实施例相同的附图标记来表示相同或近似的构件。相同或近似的构件内容也可参照上述第四实施例的相关说明，不再赘述。5 is a schematic side view of a double-sided cooling power package structure according to a fifth embodiment of the present invention, wherein the same reference numerals as the fourth embodiment are used to denote the same or similar components. For the content of the same or similar components, reference may also be made to the relevant descriptions of the above-mentioned fourth embodiment, which will not be repeated.

请参照图5，第五与第四实施例的差异在于第五实施例的双面冷却功率封装结构50中的第二导电带400与第一导电带106是不连续结构，其中第二部分106b和400b是分开的。因此，根据电路的容量，可以改变半导体晶片104的位置以及第一导电带106与第二导电带400的位置。Referring to FIG. 5 , the difference between the fifth embodiment and the fourth embodiment is that the second conductive strip 400 and the first conductive strip 106 in the double-sided cooling power package structure 50 of the fifth embodiment are discontinuous structures, wherein the second portion 106 b and 400b are separate. Therefore, depending on the capacity of the circuit, the position of the semiconductor wafer 104 and the positions of the first conductive strip 106 and the second conductive strip 400 can be changed.

图6是依照本发明的第六实施例的一种双面冷却功率封装结构的侧视示意图，其中使用与第一实施例相同的附图标记来表示相同或近似的构件。相同或近似的构件内容也可参照上述第一实施例的相关说明，不再赘述。6 is a schematic side view of a double-sided cooling power package structure according to a sixth embodiment of the present invention, wherein the same reference numerals as in the first embodiment are used to denote the same or similar components. For the content of the same or similar components, reference may also be made to the relevant descriptions of the above-mentioned first embodiment, which will not be repeated.

请参照图6，第一与第六实施例的差异在于第六实施例的双面冷却功率封装结构60中还有多个金属预成型体600。所述金属预成型体600设置在第二冷却基板102与半导体晶片104之间，且金属预成型体600较佳是对应形成于每个半导体晶片104的中央。所述金属预成型体600例如通过激光焊接或UC接合(也称为超声波焊接)如超声波热压接合(thermalultrasonic compression)，与第二冷却基板102的下金属层102b直接接触。此外，第一导电带106的第一部分106a设置在金属预成型体600与半导体晶片104之间，而第一部分106a可通过焊料602接合至金属预成型体600。在一实施例中，金属预成型体600的厚度小于或等于第二部分106b和第一部分106a之间的高度差。由于金属预成型体600例如由具有优异热传导性的铜制得，因此半导体晶片104产生的热可通过金属预成型体600有效地传递至第二冷却基板102。Referring to FIG. 6 , the difference between the first and sixth embodiments is that there are a plurality of metal preforms 600 in the double-sided cooling power package structure 60 of the sixth embodiment. The metal preform 600 is disposed between the second cooling substrate 102 and the semiconductor wafer 104 , and the metal preform 600 is preferably formed corresponding to the center of each semiconductor wafer 104 . The metal preform 600 is in direct contact with the lower metal layer 102b of the second cooling substrate 102, eg, by laser welding or UC bonding (also called ultrasonic welding) such as thermal ultrasonic compression. Additionally, the first portion 106a of the first conductive strip 106 is disposed between the metal preform 600 and the semiconductor wafer 104 , and the first portion 106a may be bonded to the metal preform 600 by solder 602 . In one embodiment, the thickness of the metal preform 600 is less than or equal to the height difference between the second portion 106b and the first portion 106a. Since the metal preform 600 is made of, for example, copper having excellent thermal conductivity, the heat generated by the semiconductor wafer 104 can be efficiently transferred to the second cooling substrate 102 through the metal preform 600 .

图7是依照本发明的第七实施例的一种双面冷却功率封装结构的侧视示意图，其中使用与第一实施例相同的附图标记来表示相同或近似的构件。相同或近似的构件内容也可参照上述第一实施例的相关说明，不再赘述。7 is a schematic side view of a double-sided cooling power package structure according to a seventh embodiment of the present invention, wherein the same reference numerals as in the first embodiment are used to denote the same or similar components. For the content of the same or similar components, reference may also be made to the relevant descriptions of the above-mentioned first embodiment, which will not be repeated.

请参照图7，第七实施例的双面冷却功率封装结构70同样包括第一冷却基板100、第二冷却基板102、至少一半导体晶片104以及多个第一导电带106。然而，第一导电带106的第二部分106b通过焊料700连结至半导体晶片104，但本发明不限于此。在另一实施例中，可通过超声波压缩(UC)接合，将半导体晶片104接合在第二部分106b上。第一导电带106的第一部分106a则与第二冷却基板102直接接触。由于第一导电带106和下金属层102b的材料可以相同，因此第一部分106a与第二冷却基板102的接合方法包括UC接合或激光焊接等。然而本发明并不限于此；在另一实施例中，第一部分106a可通过其他焊料(未示出)接合至第二冷却基板102。Referring to FIG. 7 , the double-sided cooling power package structure 70 of the seventh embodiment also includes a first cooling substrate 100 , a second cooling substrate 102 , at least one semiconductor chip 104 and a plurality of first conductive strips 106 . However, the second portion 106b of the first conductive strip 106 is attached to the semiconductor wafer 104 by the solder 700, but the invention is not limited thereto. In another embodiment, the semiconductor wafer 104 may be bonded to the second portion 106b by ultrasonic compression (UC) bonding. The first portion 106a of the first conductive strip 106 is in direct contact with the second cooling substrate 102 . Since the materials of the first conductive strip 106 and the lower metal layer 102b may be the same, the bonding method of the first portion 106a and the second cooling substrate 102 includes UC bonding or laser welding. However, the present invention is not limited thereto; in another embodiment, the first portion 106a may be joined to the second cooling substrate 102 by other solders (not shown).

图8是依照本发明的第八实施例的一种双面冷却功率封装结构的侧视示意图，其中使用与第七实施例相同的附图标记来表示相同或近似的构件。相同或近似的构件内容也可参照上述第七实施例的相关说明，不再赘述。8 is a schematic side view of a double-sided cooling power package structure according to an eighth embodiment of the present invention, wherein the same reference numerals as the seventh embodiment are used to denote the same or similar components. For the content of the same or similar components, reference may also be made to the related descriptions of the above seventh embodiment, which will not be repeated.

请参照图8，第八与第七实施例的差异在于第八实施例的双面冷却功率封装结构80中还包括第二导电带800。第二导电带800设置在所述第一冷却基板100与所述第二冷却基板102之间，其中所述第二导电带800具有与第一导电带106相同的形状，但尺寸上可能有一点差异。举例来说，第二导电带800包括第一部分800a、第二部分800b以及连接第一部分800a和第二部分800b的可弯曲部分800c。第一部分106a与800a可通过焊料802接合至第二冷却基板102。第二导电带800不接触半导体晶片104，因此根据电路或拓扑的设计，其可为电流和热量提供额外的路径。在本实施例中，所述第二导电带800与所述第一导电带106是不连续结构，其中第二部分800b与106b是分开的。或者，第二导电带800与第一导电带106是连续结构，或是连续结构和不连续结构的组合。Referring to FIG. 8 , the difference between the eighth embodiment and the seventh embodiment is that the double-sided cooling power package structure 80 of the eighth embodiment further includes a second conductive strip 800 . A second conductive strip 800 is disposed between the first cooling substrate 100 and the second cooling substrate 102, wherein the second conductive strip 800 has the same shape as the first conductive strip 106, but may be a little bit larger in size difference. For example, the second conductive strip 800 includes a first portion 800a, a second portion 800b, and a bendable portion 800c connecting the first portion 800a and the second portion 800b. The first portions 106a and 800a may be bonded to the second cooling substrate 102 by solder 802 . The second conductive strip 800 does not contact the semiconductor wafer 104 and thus may provide additional paths for current and heat depending on the design of the circuit or topology. In this embodiment, the second conductive strip 800 and the first conductive strip 106 are discontinuous structures, wherein the second portions 800b and 106b are separated. Alternatively, the second conductive strip 800 and the first conductive strip 106 are continuous structures, or a combination of continuous and discontinuous structures.

图9是依照本发明的第九实施例的一种双面冷却功率封装结构的侧视示意图，其中使用与第七实施例相同的附图标记来表示相同或近似的构件。相同或近似的构件内容也可参照上述第七实施例的相关说明，不再赘述。9 is a schematic side view of a double-sided cooling power package structure according to a ninth embodiment of the present invention, wherein the same reference numerals as those of the seventh embodiment are used to denote the same or similar components. For the content of the same or similar components, reference may also be made to the related descriptions of the above seventh embodiment, which will not be repeated.

请参照图9，第九与第七实施例的差异在于第九实施例的双面冷却功率封装结构90中还有多个金属预成型体900。所述金属预成型体900设置在第二冷却基板102与半导体晶片104之间，其中金属预成型体900与第二冷却基板102的下金属层102b直接接触。所述金属预成型体9可通过UC接合或激光焊接等形成。此外，第一导电带106的第二部分106b设置在金属预成型体900与半导体晶片104之间，而第二部分106b可通过焊料902接合至金属预成型体900。由于金属预成型体900例如由具有优异热传导性的铜制得，因此半导体晶片104产生的热可通过金属预成型体900有效地传递至第二冷却基板102，进而有利于双面冷却功率封装结构90的散热。Referring to FIG. 9 , the difference between the ninth embodiment and the seventh embodiment is that there are a plurality of metal preforms 900 in the double-sided cooling power package structure 90 of the ninth embodiment. The metal preform 900 is disposed between the second cooling substrate 102 and the semiconductor wafer 104 , wherein the metal preform 900 is in direct contact with the lower metal layer 102 b of the second cooling substrate 102 . The metal preform 9 may be formed by UC bonding, laser welding, or the like. Furthermore, the second portion 106b of the first conductive strip 106 is disposed between the metal preform 900 and the semiconductor wafer 104 , and the second portion 106b may be bonded to the metal preform 900 by solder 902 . Since the metal preform 900 is made of, for example, copper having excellent thermal conductivity, the heat generated by the semiconductor wafer 104 can be efficiently transferred to the second cooling substrate 102 through the metal preform 900 , thereby facilitating the double-sided cooling of the power package structure 90 cooling.

综上所述，根据本发明的双面冷却功率封装结构可以通过特定的导电带吸收不同材料之间的热压缩与热应力所产生的应力。具体而言，导电带的可弯曲部分在热压缩过程中会发生弹性变形，从而提高封装和半导体晶片的坚固性。此外，本发明在工艺成本(仅需一次或两次回流焊接步骤)方面以及通过导电带的理想散热性能方面也具有优势。To sum up, the double-sided cooling power package structure according to the present invention can absorb the stress caused by thermal compression and thermal stress between different materials through specific conductive strips. Specifically, the flexible portion of the conductive tape elastically deforms during thermal compression, thereby improving the robustness of the package and semiconductor wafer. In addition, the present invention has advantages in terms of process cost (only one or two reflow soldering steps are required) and in terms of ideal heat dissipation through the conductive tape.

对本领域技术人员显而易见的是，在不脱离本发明的范围或精神的情况下，可以对所公开的实施例进行各种修改和变化。鉴于前述内容，本发明旨在涵盖落在所附权利要求及其等同物的范围内的修改和变化。It will be apparent to those skilled in the art that various modifications and variations of the disclosed embodiments can be made without departing from the scope or spirit of the invention. In view of the foregoing, the present invention is intended to cover modifications and changes within the scope of the appended claims and their equivalents.

Claims (16)

1. A dual-sided cooling power package structure comprising:
a first cooling substrate;
a second cooling substrate disposed opposite to the first cooling substrate;
at least one semiconductor wafer bonded to one of the first cooling substrate and the second cooling substrate; and
a plurality of first conductive strips disposed between the first cooling substrate and the second cooling substrate, wherein each of the first conductive strips includes a first portion, a second portion, and a bendable portion connecting the first portion and the second portion, the bendable portion forming a closed loop at an edge of the first portion, one of the first portion and the second portion being in direct contact with the semiconductor wafer, and the other of the first portion and the second portion extending away from the semiconductor wafer.
2. The dual sided cooling power package structure of claim 1, wherein the first conductive strip is a discontinuous structure.
3. The dual sided cooling power package structure of claim 1, wherein the first conductive strap is a continuous structure.
4. The dual sided cooled power package structure of claim 1, wherein the first portion is in direct contact with the semiconductor die.
5. The dual sided cooling power package structure of claim 1, wherein the first portion is bonded to the semiconductor die via a first solder.
6. The dual sided cooling power package structure of claim 1, wherein the semiconductor die is bonded on the first cooling substrate and the second portion of each of the first conductive strips is in direct contact with the second cooling substrate.
7. The dual sided cooling power package structure of claim 1, wherein the semiconductor die is bonded on the first cooling substrate and the second portion of each of the first conductive strips is bonded to the second cooling substrate via a second solder.
8. The dual sided cooled power package structure of claim 1, wherein the second portion is in direct contact with the semiconductor die.
9. The dual sided cooling power package structure of claim 1, wherein the second portion is bonded to the semiconductor die via a first solder.
10. The dual sided cooled power package structure of claim 1, wherein the semiconductor die is bonded on the first cooling substrate and the first portion of each of the first conductive strips is in direct contact with the second cooling substrate.
11. The dual sided cooling power package structure of claim 1, wherein the semiconductor die is bonded on the first cooling substrate and the second portion of each of the first conductive strips is bonded to the second cooling substrate via a second solder.
12. The dual sided cooling power package structure of claim 1, further comprising a plurality of metal pre-forms disposed between the second cooling substrate and the semiconductor die, wherein the metal pre-forms are in direct contact with the second cooling substrate and the one of the first portion and the second portion is disposed between the metal pre-forms and the semiconductor die.
13. The dual sided cooling power package structure of claim 1, further comprising at least a second conductive strip disposed between the first cooling substrate and the second cooling substrate, wherein the second conductive strip has the same shape as each of the first conductive strips and does not contact the semiconductor die.
14. The dual sided cooling power package structure of claim 13, wherein the second conductive strip is a discontinuous structure with the first conductive strip.
15. The dual sided cooling power package structure of claim 13, wherein the second conductive strip is a continuous structure with the first conductive strip.
16. The dual sided cooled power package structure of claim 13, wherein the first and second cooling substrates comprise direct copper clad ceramic substrates.
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US10770369B2 (en) * 2018-08-24 2020-09-08 Advanced Semiconductor Engineering, Inc. Semiconductor device package
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