CN114553225A - Testing device for digital-to-analog conversion chip - Google Patents
Testing device for digital-to-analog conversion chip Download PDFInfo
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Abstract
本发明涉及电路技术领域，提供了一种用于数模转换芯片的测试装置，利用处理单元提供的标准测试码，通过具有待测D/A芯片的采样放大单元进行数模转换得到可表征任意两个相邻标准测试码转换后测试电压间差值的检测值；以及利用具有基准D/A芯片的基准放大单元对标准测试码进行数模转换得到可表征前述两个相邻标准测试码转换后基准电压间差值的参考值；再通过比较单元根据该检测值与该参考值比较生成检测信号，利用处理单元根据一组前述检测信号计算或者获得待测D/A芯片的一组静态参数向量，并根据该一组静态参数向量的变化量与预设误差范围的比较结果判断该待测D/A芯片的数模转换功能是否正常。由此可有效缩短数模转换芯片的测试时间。
The invention relates to the technical field of circuits, and provides a test device for a digital-to-analog conversion chip. The standard test code provided by a processing unit is used to perform digital-to-analog conversion by a sampling amplifying unit with a D/A chip to be tested to obtain a test code that can represent any arbitrary value. The detection value of the difference between the test voltages after the conversion of two adjacent standard test codes; The reference value of the difference between the reference voltages; the comparison unit generates a detection signal according to the detection value and the reference value, and the processing unit calculates or obtains a set of static parameters of the D/A chip to be tested according to a set of the foregoing detection signals. vector, and judge whether the digital-to-analog conversion function of the D/A chip to be tested is normal according to the comparison result between the variation of the set of static parameter vectors and the preset error range. Therefore, the test time of the digital-to-analog conversion chip can be effectively shortened.
Description
Technical Field
The present disclosure relates to the field of circuit technologies, and in particular, to a test apparatus for a digital-to-analog conversion chip.
Background
A digital-to-analog conversion chip (hereinafter referred to as a D/a chip) is an integrated chip that converts a digital signal into an analog voltage signal. The method is widely applied to the field of industrial control and also widely applied to the field of communication electronics, such as voltage input of a voltage control crystal oscillator control voltage end, analog intermediate frequency signal conversion of digital baseband intermediate frequency signals in a wireless communication base station and the like. For example, the D/a chip SGM5204/5207 integrates 32/48 12-bit Digital-to-Analog converters (DACs), an ideal DAC should exhibit a linear relationship between its Digital input and its Analog output, but in an actual DAC, this relationship is often non-linear due to component mismatch, non-ideal layout, modeling limitations, and other sources of deviation from ideal or desired behavior.
Therefore, in industrial applications, the static parameters of the DAC need to be calculated. The test of the existing D/a chip can be divided into two aspects, one is the test of the digital input interface, and the other is the test of the function of the analog output interface (i.e. the test of the digital-to-analog conversion function). The testing method of the digital input interface is simple and easy to realize, and the configuration and the write-read test of the register can be directly carried out by utilizing the CPU bus interface. For the analog output port, because the output voltage of the analog output port directly drives electrical equipment (such as voltage control equipment such as a motor) and the equipment is not directly connected with a D/A system through a feedback channel, the test of the digital-to-analog conversion function of the analog output port cannot be directly realized by the system.
The existing testing means of D/a chip to analog output mostly adopts methods such as multi-point sampling linear staircase histogram method or histogram method to test the static parameters of DAC, such as offset Error, Integral nonlinear value (INL), Differential nonlinear value (DNL), Gain Error (Gain Error), absolute accuracy Error and aperture Error. Since the analog voltage is a continuous signal and the digital code is a discrete value, for a DAC, the analog output voltage is determined based on the digital input code, resulting in a step increase in voltage from one digital code to the next. The width of each step is a function of the resolution of the DAC and the component mismatches within the DAC. DNL error refers to the difference between the actual step width between successive digital codes and the ideal step width of the DAC. The step width of an ideal DAC may be referred to as "1 LSB", and the DNL error may be expressed in units of LSB. For example, +1/2LSB DNL error means that the step width is 50% greater than the ideal DAC step width, and one of the DAC primary parameter metrics is conversion accuracy, which is the error between the output analogue voltage value and the value based on the ideal output voltage, which should typically be less than ± 1/2 LSB.
The use of a linear staircase histogram or histogram method is a statistical method, which has randomness and coarseness, and the value of the output voltage output from the DAC cannot determine the input code input to the DAC. In the process of testing the DAC, a more accurate test result can be obtained only by traversing all input codes of the DAC under the condition of enough sampling points. As mentioned above, in the stage of mass production test, the D/a chip SGM5204/5207 integrated with multiple DACs needs to traverse each input code of the DAC to obtain the voltage difference DNL between two adjacent output codes, for example, using a histogram test method, the total number of voltage values of all test points is 131072/196608, and the original scheme needs to scan and test the voltage values of all input codes, which consumes a long time for testing, resulting in higher test cost and long delivery cycle.
Therefore, how to design a test circuit capable of shortening the test time of the DAC is a technical problem to be solved at present.
Disclosure of Invention
In order to solve the above technical problem, the testing apparatus for a digital-to-analog conversion chip provided by the present disclosure can effectively shorten the testing time of the analog output of the D/a chip.
The present disclosure provides a testing apparatus for a digital-to-analog conversion chip, including:
the processing unit is used for providing standard test codes in the standard test code set;
the sampling amplification unit is used for receiving the standard test codes, performing digital-to-analog conversion processing according to the standard test codes and outputting a detection value obtained after conversion, wherein the detection value represents a difference value between two test voltages converted by any two adjacent standard test codes;
the standard amplifying unit is used for receiving the standard test code, performing digital-to-analog conversion processing according to the standard test code, and outputting a reference value obtained after conversion, wherein the reference value represents a difference value between two reference voltages obtained after the conversion of the two adjacent standard test codes;
a comparison unit, the input end of which is connected with the sampling amplification unit and the reference amplification unit respectively, and compares the detection value with the reference value to generate a detection signal,
the processing unit is connected with the output end of the comparing unit, and is further configured to calculate or obtain a set of static parameter vectors of the digital-to-analog conversion chip to be tested according to a set of the detection signals, and determine whether the digital-to-analog conversion function of the digital-to-analog conversion chip to be tested is normal according to a comparison result between the variation of the set of static parameter vectors and a preset error range.
Preferably, the sampling amplification unit includes:
the digital-to-analog conversion chip to be tested is used for performing digital-to-analog conversion processing according to the standard test codes and outputting converted test voltages, wherein each output test voltage corresponds to one input standard test code;
the sampling and holding module is used for holding and outputting the test voltage corresponding to the current standard test code;
and the differential amplifier is respectively connected with the digital-to-analog conversion chip to be tested and the sampling and holding module, and is used for acquiring a difference value between two test voltages converted by two adjacent standard test codes, amplifying the difference value and outputting the detection value.
Preferably, the sampling amplification unit further includes:
the first switch module is provided with a control end, a first selection end and a second selection end, the control end is connected with the output end of the digital-to-analog conversion chip to be tested, and the first switch module is controlled by a first control signal to select one of the first selection end and the second selection end to be communicated.
Preferably, the aforementioned sample-and-hold module comprises:
a non-inverting input terminal of the first comparator is connected with the first selection terminal;
a second comparator, wherein the non-inverting input terminal of the second comparator is connected to the ground through a second resistor and a first capacitor in series, and the inverting input terminal of the second comparator is connected to the inverting input terminal of the first comparator through a first resistor;
the second switch module is connected between the output end of the first comparator and the non-inverting input end of the second comparator, and is controlled by a second control signal to control the on-off between the output end of the first comparator and the non-inverting input end of the second comparator;
the positive end of the first diode and the negative end of the second diode are connected to the output end of the first comparator together, and the negative end of the first diode and the positive end of the second diode are connected to the inverting input end of the first comparator together.
Preferably, the differential amplifier comprises:
a third comparator, the non-inverting input end of which is connected with the output end of the second comparator, and the output end of which is connected with the output end of the differential amplifier in series through a third resistor and a fourth resistor;
a fourth comparator, a non-inverting input terminal of which is connected to the second selection terminal, an inverting input terminal of which is connected to an inverting input terminal of the third comparator through a third resistor, and an output terminal of which is connected to ground through a fifth resistor and a sixth resistor in series;
and a fifth comparator having a non-inverting input terminal connected to a connection node of the fifth resistor and the sixth resistor, an inverting input terminal connected to a connection node of the third resistor and the fourth resistor, and an output terminal serving as an output terminal of the differential amplifier for providing the detection value.
Preferably, the reference amplification unit includes:
the reference digital-to-analog conversion chip is used for performing digital-to-analog conversion processing according to the standard test codes and outputting converted reference voltages, and each output reference voltage corresponds to one input standard test code;
and the operational amplifier module is connected between the reference digital-to-analog conversion chip and the comparison unit and is used for acquiring a difference value between two reference voltages obtained after the two adjacent standard test codes are converted, amplifying the difference value and outputting the reference value.
Preferably, the operational amplifier module comprises an operational amplifier and a circuit located at the periphery of the operational amplifier chip, a non-inverting input terminal of the operational amplifier is connected to the output terminal of the reference digital-to-analog conversion chip, an inverting input terminal of the operational amplifier is connected to the ground through a seventh resistor, an output terminal of the operational amplifier is connected to a connection node of the inverting input terminal of the operational amplifier and the seventh resistor through an eighth resistor and a second capacitor which are connected in parallel, and
the operational amplifier is also provided with a positive power supply end connected with a positive power supply signal and a negative power supply end receiving a negative power supply signal, the positive power supply end is connected to the ground through a third capacitor and a fourth capacitor which are connected in parallel, and the negative power supply end is connected to the ground through a fifth capacitor and a sixth capacitor which are connected in parallel.
Preferably, the aforementioned comparison unit includes:
and a sixth comparator having a non-inverting input terminal connected to the output terminal of the fifth comparator, an inverting input terminal connected to the output terminal of the operational amplifier, and an output terminal supplying the detection signal.
Preferably, the aforementioned processing unit comprises:
the calculation module is connected with the output end of the sixth comparator and used for calculating or obtaining the static parameter vector of the analog-to-digital conversion chip to be detected according to a group of detection signals;
and the judging module is connected with the calculating module and used for reading and judging whether the digital-to-analog conversion function of the digital-to-analog conversion chip to be detected is normal or not according to the comparison result of the variable quantity of the static parameter vector and the preset error range.
Preferably, the processing unit further comprises:
the correction module is connected with the judgment module and used for acquiring a compensation code set according to the detection signal when the variation of the static parameter vector exceeds a preset error range so as to enable the processing unit to update the standard test code set according to the compensation code set;
and the storage module is connected with the correction module and is used for storing the standard test code set and the compensation code set, and the arrangement sequence of the difference value between any two adjacent test voltages in the compensation code set is consistent with the arrangement sequence of two corresponding adjacent standard test codes in the standard test code set.
The beneficial effects of this disclosure are: the test device for the digital-to-analog conversion chip provided by the disclosure utilizes the processing unit to provide the standard test codes in the standard test code set; performing digital-to-analog conversion processing according to the standard test codes through a sampling amplification unit, and outputting a detection value obtained after conversion, wherein the detection value represents a difference value between two test voltages obtained after conversion of any two adjacent standard test codes; performing digital-to-analog conversion processing by using a reference amplifying unit according to the standard test code, and outputting a reference value obtained after conversion, wherein the reference value represents a difference value between two reference voltages obtained after the conversion of the two adjacent standard test codes; and then, the detection value is compared with the reference value through a comparison unit to generate a detection signal, a processing unit is used for calculating or obtaining a group of static parameter vectors of the digital-to-analog conversion chip to be detected according to a group of detection signals, and whether the digital-to-analog conversion function of the digital-to-analog conversion chip to be detected is normal is judged according to the comparison result of the variable quantity of the group of static parameter vectors and a preset error range. Therefore, the voltage value of each test code is prevented from being acquired in the prior art, and whether the analog-to-digital conversion function of the analog-to-digital conversion chip to be tested is normal is directly judged only according to the variable quantity of the group of static parameter vectors output by the sixth comparator, so that the test time of analog output of the D/A chip is effectively shortened.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of the embodiments of the present disclosure with reference to the accompanying drawings.
Fig. 1 shows a block diagram of a testing apparatus for a digital-to-analog conversion chip according to an embodiment of the present disclosure;
FIG. 2 is a block diagram illustrating the structure of a further embodiment of the test apparatus shown in FIG. 1;
FIG. 3 illustrates a circuit schematic of the test apparatus of FIG. 2 in one embodiment;
FIG. 4 is a block diagram of a further embodiment of a processing unit in the test apparatus of FIG. 1.
Detailed Description
To facilitate an understanding of the present disclosure, the present disclosure will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present disclosure are set forth in the accompanying drawings. However, the present disclosure may be embodied in different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein in the description of the disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.
The test of the D/A chip digital-to-analog conversion function can be divided into static parameter test and dynamic parameter test, the static parameter test function adopts a single analog signal as an initial signal, converts the analog signal into a digital quantity, then outputs the digital quantity to enter a data acquisition card, converts the digital signal of the output data acquisition card into an analog signal, and compares the analog signal with the analog signal as the initial signal, thereby achieving the purpose of detecting a single point of the D/A chip; the dynamic parameter testing function can adopt a sine analog signal as an initial signal, divide sine into equal-time interval points, convert the voltage amplitude corresponding to each point into a digital quantity, then output the digital quantity, enter a data acquisition card, convert the acquisition point of the digital signal of the output digital acquisition card into an analog signal and compare the analog signal with the points of the analog signal as the initial signal one by one, thereby achieving the purpose of detecting the dynamic point of the D/A chip.
Many DACs include an array of capacitors that can be dynamically configured by switches coupled to the capacitors to form a capacitor divider network. Each switch may couple its respective capacitor to one of several voltages, for example, an analog input voltage, a positive reference voltage, or a negative reference voltage. Each bit of the input digital code is typically determined sequentially from the most significant bit to the least significant bit by an iterative successive approximation technique.
Some DACs include a MSB capacitor bank (also referred to as a "MSB capacitor array") and a LSB capacitor bank (referred to as a "LSB capacitor array"). In some embodiments, the capacitors in the MSB capacitor array are nominally all the same (i.e., have the same capacitance value), while the LSB capacitor bank may be binary weighted (e.g., 4C, 2C, 1C). Some DACs operate according to a thermometer coding scheme, where a binary intermediate digital code from a Successive Approximation Register (SAR) is converted to a thermometer intermediate digital code that contains one bit for each capacitor in the MSB capacitor array. By controlling the switching of the individual MSB capacitors, a particular proportion of a reference voltage may be generated and provided to the comparator for comparison with the output voltage to thereby determine each bit of the digital input code.
The present disclosure is described in detail below with reference to the accompanying drawings.
Fig. 1 shows a block diagram of a testing apparatus for a digital-to-analog conversion chip according to an embodiment of the present disclosure, and fig. 2 shows a block diagram of a further embodiment of the testing apparatus shown in fig. 1.
Referring to fig. 1 and 2, an embodiment of the present disclosure provides a test apparatus 100 for a digital-to-analog conversion chip (D/a chip), which includes but is not limited to: the device comprises a processing unit 110, a sampling amplification unit 120 integrated with a D/A chip 121 to be tested, a reference amplification unit 130 integrated with a reference D/A chip 131 and a comparison unit 140, wherein the processing unit 110 is used for providing standard test codes in a standard test code set; the sampling amplifying unit 120 is connected to the processing unit 110, and is configured to receive the standard test code, perform digital-to-analog conversion according to the standard test code, and output a detection value obtained after conversion, where the detection value represents a difference between two test voltages converted by any two adjacent standard test codes; the reference amplifying unit 130 is connected to the processing unit 110, and configured to receive the standard test code, perform digital-to-analog conversion according to the standard test code, and output a reference value obtained after the conversion, where the reference value represents a difference between two reference voltages converted by two adjacent standard test codes; the input end of the comparing unit 140 is connected to the sampling amplifying unit 120 and the reference amplifying unit 130, respectively, for comparing the detected value with the reference value to generate a detected signal,
moreover, the processing unit 110 is connected to the output end of the comparing unit 140, and the processing unit 110 is further configured to calculate or obtain a set of static parameter vectors of the D/a chip 121 to be tested according to a set of the detection signals, and determine whether the digital-to-analog conversion function of the D/a chip 121 to be tested is normal according to a comparison result between the variation of the set of static parameter vectors and a preset error range.
In further embodiments of the present disclosure, the sample amplification unit 120 includes, but is not limited to: a D/A chip 121 to be tested, a sample-and-hold module 122 and a differential amplifier 123.
The D/a chip 121 to be tested is connected to the processing unit 110, and configured to perform digital-to-analog conversion processing according to the standard test code, and output converted test voltages, where each output test voltage corresponds to an input standard test code; the input end of the sample-hold module 122 is connected to the D/a chip 121 to be tested, and the sample-hold module 122 is configured to hold and output a test voltage corresponding to the current standard test code; the input end of the differential amplifier 123 is connected to the D/a chip 121 to be tested and the sample-and-hold module 122, respectively, and is configured to obtain a difference between two test voltages obtained by converting two adjacent standard test codes, perform amplification processing, and output the detection value.
FIG. 3 shows a circuit schematic of the test apparatus of FIG. 2 in one embodiment.
Referring to fig. 2 and 3, in a further embodiment of the present disclosure, the sampling amplifying unit 120 further includes a first switch module SW1, the first switch module SW1 has a control terminal, a first selection terminal and a second selection terminal (not shown), the control terminal is connected to the output terminal VOUT1 of the D/a chip 121 to be tested, and the first switch module SW1 is controlled by a first control signal S1 to select one of the first selection terminal and the second selection terminal to be connected.
Further, the sample-and-hold module 122 includes: the circuit comprises a first comparator 1221, a second comparator 1222, a second switching module SW2, a first diode D1, a second diode D2, a first resistor R1, a second resistor R2 and a first capacitor C3.
Wherein, the non-inverting input terminal of the first comparator 1221 is connected to the first selection terminal of the first switch module SW1, and the inverting input terminal is connected to the inverting input terminal of the second comparator 1222 through the first resistor R1; the non-inverting input terminal of the second comparator 1222 is connected to the analog ground AGND through the second resistor R2 and the first capacitor C3 in series, and the inverting input terminal is connected to the inverting input terminal of the first comparator 1221 through the first resistor R1; the second switch module SW2 is connected between the output terminal of the first comparator 1221 and the non-inverting input terminal of the second comparator 1222, and the second switch module SW2 is controlled by the second control signal S2 to control the on/off between the output terminal of the first comparator 1221 and the non-inverting input terminal of the second comparator 1222; the positive terminal of the first diode D1 and the negative terminal of the second diode D2 are commonly connected to the output terminal of the first comparator 1221, and the negative terminal of the first diode D1 and the positive terminal of the second diode D2 are commonly connected to the inverting input terminal of the first comparator 1221.
Further, the differential amplifier 123 includes at least: a third comparator 1231, a fourth comparator 1232, a fifth comparator 1233, a second resistor R5, a third resistor R3, a fourth resistor R8, a fifth resistor R6, and a sixth resistor R9.
The non-inverting input terminal of the third comparator 1231 is connected to the output terminal of the second comparator 1222, and the output terminal is connected to the output terminal of the differential amplifier 123 through the third resistor R3 and the fourth resistor R8 in series; a non-inverting input terminal of the fourth comparator 1232 is connected to the second selection terminal of the first switching module SW1, an inverting input terminal of the fourth comparator 1232 is connected to an inverting input terminal of the third comparator 1231 through a second resistor R5, and an output terminal of the fourth comparator is connected to the ground GND through a fifth resistor R6 and a sixth resistor R9 in series; the non-inverting input terminal of the fifth comparator 1233 is connected to the connection node between the fifth resistor R6 and the sixth resistor R9, the inverting input terminal thereof is connected to the connection node between the third resistor R3 and the fourth resistor R8, and the output terminal thereof is used as the output terminal of the differential amplifier 123 for providing the aforementioned detection value. Meanwhile, the negative power supply terminal of the third comparator 1231 connected to the negative power supply signal-VCC is connected to the output terminal of the third comparator 1231 through a resistor R4, and the negative power supply terminal of the fourth comparator 1232 connected to the negative power supply signal-VCC is connected to the output terminal of the fourth comparator 1232 through a resistor R7.
Further, the reference amplifying unit 130 includes: a reference D/a chip 131 and an operational amplifier module 132, wherein the operational amplifier module 132 includes an operational amplifier 1321 and a circuit located at the periphery of the operational amplifier 1321, and the peripheral circuit includes: a seventh resistor R11, an eighth resistor R10, a second capacitor C10, a third capacitor C8, a fourth capacitor C9, and a fifth capacitor C6 and a sixth capacitor C7.
The reference D/a chip 131 is configured to perform digital-to-analog conversion according to the standard test code, and output converted reference voltages, where each output reference voltage corresponds to an input standard test code; the operational amplifier 1321 is connected between the reference D/a chip 131 and the comparing unit 140, and is configured to obtain a difference between two reference voltages obtained by converting the two adjacent standard test codes, perform amplification processing, and output the reference value.
Specifically, the non-inverting input terminal of the operational amplifier 1321 is connected to the output terminal of the reference D/a chip 131, the inverting input terminal is connected to the analog ground AGND through a seventh resistor R12, the output terminal is connected to a connection node of the inverting input terminal of the operational amplifier 1321 and the seventh resistor R12 through an eighth resistor R10 and a second capacitor C10 which are connected in parallel, the operational amplifier 1321 further has a positive power terminal which is connected to the positive power signal VCC and a negative power terminal which receives the negative power signal-VCC, and the positive power terminal is connected to the analog ground AGND through a third capacitor C8 and a fourth capacitor C9 which are connected in parallel, and the negative power terminal is connected to the analog ground AGND through a fifth capacitor C6 and a sixth capacitor C7 which are connected in parallel.
Further, the comparing unit 140 at least comprises a sixth comparator 141, wherein the non-inverting input terminal of the sixth comparator 141 is connected to the output terminal VOUT3 of the fifth comparator 1233, the inverting input terminal thereof is connected to the output terminal VOUT4 of the operational amplifier 1321, and the output terminal VOUT5 provides the aforementioned detection signal.
Further, the operational amplifier 1321 and the differential amplifier 123 are amplifiers having the same amplification factor after the calibration test.
In the present embodiment, the D/a chip 121 to be tested is, for example, a 12-bit DAC, the reference D/a chip 131 is, for example, a reference 16-bit D/a chip subjected to testing, and is used for outputting a desired reference, and the reference voltage VREF for being provided to the reference D/a chip 131 and the D/a chip 121 to be tested may be provided by a separate power module, or may be extracted by a power supply part driving the overall testing apparatus 100 through a circuit processing manner such as a voltage dividing circuit. The setting of the reference voltage is determined according to the D/A conversion index range of the actual D/A chip to be measured. The principle of reference voltage selection is: the reference voltage is to be within the analog output voltage range of the D/a chip, and if the analog voltage output range of the D/a chip is 0-a volts, the reference voltage should be selected to be between 0< reference voltage < a volts, e.g., a/2 volts. In addition, a plurality of reference voltages can be set, the same D/A chip can be tested by using the plurality of reference voltages, and different D/A chips can also be tested by using different reference voltages.
In this embodiment, the comparing unit 140 may be implemented by using a voltage comparator chip, and the model of the voltage comparator chip is selected according to the range of the D/a conversion index of the actual D/a chip 121 to be tested. The principle of voltage comparator chip selection is as follows: the input voltage ranges of the two input ends are larger than the analog voltage output range of the D/A chip 121 to be tested; of course, the comparing unit 140 may also use a voltage comparator circuit combined by operational amplifiers instead of a voltage comparator chip, and the effect is the same.
The detection value output by the differential amplifier 123 is an amplified signal of the test voltage difference, the reference value output by the operational amplifier 1321 is an amplified signal of the reference voltage difference, and the comparison result between the two signals indicates that the detection signal is also a voltage signal.
The processing unit 110 is used to provide a test of the entire test environment, and also to control the inputs of the digital input terminals of the D/a chip 121 to be tested and the reference D/a chip 131, and read the voltage comparison result output by the comparing unit 140.
FIG. 4 is a block diagram of a further embodiment of a processing unit in the test apparatus of FIG. 1.
Referring to fig. 4, in a further embodiment of this example, the processing unit 110 may include: a calculation module 111, a judgment module 112, a correction module 113 and a storage module 114.
The calculating module 111 is connected to the output terminal VOUT5 of the sixth comparator 141, and is configured to calculate or obtain a static parameter vector of the to-be-detected D/a chip 121 according to a group of the detection signals; the determining module 112 is connected to the calculating module 111, and configured to read and determine whether the digital-to-analog conversion function of the D/a chip 121 to be tested is normal according to a comparison result between the variation of the static parameter vector and a preset error range; the correcting module 113 is connected to the determining module 112, and configured to obtain a compensation code set according to the detection signal when the variation of the static parameter vector exceeds a preset error range, so that the processing unit 110 updates the standard test code set according to the compensation code set; the storage module 114 is connected to the correction module 113, and is configured to store the standard test code set and the compensation code set, and an arrangement order of differences between any two adjacent test voltages in the compensation code set is consistent with an arrangement order of two corresponding adjacent standard test codes in the standard test code set.
In the test process of a single D/a chip 121 to be tested: suppose we need to ensure that the DNL of each D/a chip 121 is within ± 0.5 LSB in mass production testing.
Firstly, a digital interface of the processing unit 110 is utilized to control a reference D/A chip 131 to output a certain number of digits converted from standard test codes, which corresponds to an expected 0.5 time DNL; secondly, the processing unit 110 is used for controlling the D/A chip 121 to be tested to output a test voltage value corresponding to the converted current standard test code; then the processing unit 110 controls the sample-and-hold module 122 to latch the currently output test voltage value; then, the processing unit 110 is used for controlling the D/A chip 121 to be tested to output a test voltage value corresponding to the next standard test code of the current standard test code after conversion; and the difference value of two adjacent test voltages is amplified by a certain magnification by the differential amplifier 123 and is input to the sixth comparator 141 in the comparison unit 140, the differential amplifier 123 and the operational amplifier 1321 are amplifiers with the same magnification after calibration test, the detection value and the reference value (0.5 LSB) output correspondingly by the differential amplifier 123 and the operational amplifier are respectively used as the positive input signal and the negative input signal of the sixth comparator 141 for comparison, and the result (detection signal) output by comparison is received and processed by the processing unit 110; the above steps are repeated to traverse all gradients of the standard test code, so as to obtain a set of static parameter vectors output by the comparator 141, and then the processing unit 110 determines whether the D/a chip 121 to be tested satisfies the expected DNL value according to (the variation amount of) the set of output static parameter vectors. For example, if the variation of the set of static parameter vectors outputted by the D/a chip 121 under test should be smaller than the expected DNL value range, the output of the comparing unit 140 should be a low level (logic "0"); the processing unit 110 reads the detection signal output by the comparing unit 140, and determines whether the detection signal is logic "0", if so, it indicates that the digital-to-analog conversion function test of the D/a chip 121 to be tested is valid; if not, the digital-to-analog conversion function test of the D/A chip is invalid.
Further, the sampling amplification unit 120, the reference amplification unit 130, and the comparison unit 140 may be respectively calibrated before each test, and the calibration data is stored in the processing unit 110. Compensating in the program based on the calibration data to improve the accuracy of the test, an
When the variation of the static parameter vector exceeds the predetermined error range, the processing unit 110 obtains a compensation code set according to the detection signal, so that the processing unit 110 updates the standard test code set according to the compensation code set.
To sum up, the testing apparatus 100 for D/a chip provided by the embodiment of the present disclosure provides a standard test code in a standard test code set by using the processing unit 110; performing digital-to-analog conversion processing according to the standard test code through the sampling amplification unit 120, and outputting a detection value obtained after conversion, wherein the detection value represents a difference value between two test voltages obtained after conversion of any two adjacent standard test codes; performing digital-to-analog conversion processing by using the reference amplifying unit 130 according to the standard test code, and outputting a reference value obtained after the conversion, wherein the reference value represents a difference value between two reference voltages obtained after the conversion of the two adjacent standard test codes; then, the comparison unit 140 compares the detection value with the reference value to generate a detection signal, the processing unit 110 calculates or obtains a set of static parameter vectors of the D/a chip 121 to be tested according to a set of the detection signal, and determines whether the digital-to-analog conversion function of the D/a chip 121 to be tested is normal according to a comparison result between the variation of the set of static parameter vectors and a preset error range. Therefore, the voltage value of each test code is prevented from being acquired in the prior art, and whether the analog-to-digital conversion function of the D/a chip 121 to be tested is normal is directly judged only according to the variation of the group of static parameter vectors output by the sixth comparator 141, so that the test time of analog output of the D/a chip is effectively shortened.
It should be noted that in the description of the present disclosure, it is to be understood that the terms "upper", "lower", "inner", and the like, indicate orientation or positional relationship, are only for convenience in describing the present disclosure and simplifying the description, but do not indicate or imply that the referenced components or elements must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present disclosure.
Further, in this document, the contained terms "include", "contain" or any other variation thereof are intended to cover a non-exclusive inclusion, so that a process, a method, an article or an apparatus including a series of elements includes not only those elements but also other elements not explicitly listed or inherent to such process, method, article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present disclosure, and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious changes and modifications can be made without departing from the scope of the present disclosure.
Claims (10)
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