CN114551450A - Semiconductor structure and method of making the same - Google Patents

Abstract

The embodiment of the present disclosure provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure comprises: a substrate; the first electrode is positioned on the substrate and surrounds a through hole extending towards the direction far away from the substrate; the second electrode is at least positioned in the through hole; the capacitor dielectric layer is positioned between the first electrode and the second electrode, the capacitor dielectric layer and the first electrode form a capacitor structure; the transistor is positioned on the capacitor structure and comprises a first doping area and a second doping area which are arranged at intervals along the direction vertical to the surface of the substrate, the first doping area is electrically connected with the second electrode, the doping type of the first doping area and the doping type of the second doping area are one of N type or P type, and the doping types of the first doping area and the second doping area are the same; and the bit line is positioned on the transistor and is electrically connected with the second doped region. The embodiment of the disclosure is at least beneficial to improving the performance of the semiconductor device and reducing the difficulty of the manufacturing process.

Description

Semiconductor structure and method of making the same

technical field

Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for manufacturing the same.

Background technique

With the development of semiconductor technology, the manufacture of semiconductor devices with better performance and higher integration has become the main direction pursued in the semiconductor processing process.

However, the manufacturing process of the smaller-sized semiconductor device is complex, and the performance of the processing equipment is extremely required, and it is difficult to realize the method of improving the processing accuracy by improving the performance of the processing equipment.

Therefore, improving the layout and formation method of the semiconductor device structure is an effective way to make the semiconductor device meet the requirements of better performance and smaller size while reducing the processing difficulty of the semiconductor device.

SUMMARY OF THE INVENTION

Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, which are at least beneficial to improve the performance of the semiconductor device and reduce the difficulty of the manufacturing process.

In one aspect, an embodiment of the present disclosure provides a semiconductor structure, comprising: a substrate; a first electrode, the first electrode is located on the substrate, the first electrode encloses a through hole extending in a direction away from the substrate; a second electrode, the second electrode is at least located on the substrate In the through hole; the capacitor dielectric layer, the capacitor dielectric layer is located between the first electrode and the second electrode, the second electrode, the capacitor dielectric layer and the first electrode form a capacitor structure; the transistor, the transistor is located on the capacitor structure, and the transistor includes a vertical The first doping region and the second doping region are arranged at intervals in the direction of the surface of the substrate, the first doping region is electrically connected to the second electrode, and the doping type of the first doping region and the second doping region is N-type Or one of the P-type, and the doping types of the first doping region and the second doping region are the same; the bit line is located on the transistor and is electrically connected to the second doping region.

In some embodiments, the method further includes: an insulating layer, the capacitor structure is located in the insulating layer, and the insulating layer exposes the top surface of the second electrode; the outer sidewall of the through hole away from the second electrode is in contact with the insulating layer; the through hole is surrounded by the second electrode. The electrodes and the capacitive dielectric layer are filled together, and the top surface of the second electrode is flush with the top surface of the capacitive dielectric layer.

In some embodiments, the capacitive dielectric layer is further located on the top surface of the first electrode and the top surface of the insulating layer, and the top surface of the second electrode is flush with the top surface of the capacitive dielectric layer.

In some embodiments, the second electrode is further located on the outer sidewall of the through hole and the top surface of the first electrode, and the second electrode includes: a first main body part, the first main body part is located in the through hole; The main body part is located on the outer side wall of the through hole, the material of the second main body part is the same as the material of the first main body part, and in the direction parallel to the surface of the substrate, the thickness of the first main body part is greater than the thickness of the second main body part; the electrical connection part , the electrical connection part spans the first main body part and the second main body part, and is in contact with the top surface of the first main body part and the top surface of the second main body part.

In some embodiments, for the same capacitor structure, the second electrode is an integrally formed structure.

In some embodiments, the first electrode includes: a side portion, where the side portion is a side wall portion of the through hole; a bottom connection portion, where the bottom connection portion is a bottom surface portion of the through hole parallel to the substrate; the semiconductor structure further includes: an electrical connection layer, and the electrical connection layer is located on the substrate and electrically connects the adjacent bottom connection parts.

In some embodiments, the electrical connection layer and the bottom connection portion are integrally formed as a film layer, and the capacitive dielectric layer is also located on the surface of the electrical connection layer.

In some embodiments, the side portion and the bottom connecting portion are integrally formed into a film layer, and the electrical connecting layer is also located between the bottom connecting portion and the substrate.

In some embodiments, the transistor further includes: a channel region, the channel region is located between the first doping region and the second doping region, and the material of the channel region, the first doping region and the second doping region is At least one or more of IGZO, IWO or ITO is included; a gate dielectric layer, the gate dielectric layer is arranged around the channel region, and is located on the sidewall surface of the channel region; the gate conductive layer, the gate conductive layer is arranged around the channel region , and is located on the sidewall surface of the gate dielectric layer corresponding to the channel region.

Another aspect of the embodiments of the present disclosure further provides a method for fabricating a semiconductor structure, including: providing a substrate; forming a first electrode on the substrate, the first electrode enclosing a through hole extending in a direction away from the substrate; forming a second electrode, the first electrode Two electrodes are located at least in the through holes; a capacitor dielectric layer is formed, the capacitor dielectric layer is located between the first electrode and the second electrode, and the second electrode, the capacitor dielectric layer and the first electrode form a capacitor structure; a transistor is formed, and the transistor is located on the capacitor structure , and the transistor includes a first doping region and a second doping region spaced along a direction perpendicular to the surface of the substrate, the first doping region is electrically connected to the second electrode, and the first doping region and the second doping region are The doping type is one of N-type or P-type, and the doping types of the first doping region and the second doping region are the same; a bit line is formed, and the bit line is located on the transistor and electrically connected to the second doping region. connect.

In some embodiments, the step of forming the first electrode includes: forming an insulating film on the substrate, and the insulating film has a groove through the thickness of the insulating film; forming a first electrode, the first electrode is located on the bottom and sidewalls of the groove .

In some embodiments, the remaining insulating film is used as an insulating layer; the steps of forming a capacitor dielectric layer and the second electrode include: forming a capacitor dielectric layer, and the capacitor dielectric layer is located at the bottom and sidewalls of the through hole; forming a second electrode layer, the second electrode The layer is on the surface of the capacitive dielectric layer and fills the via.

In some embodiments, the steps of forming the capacitor dielectric layer and the second electrode include: removing the remaining insulating film to expose the outer sidewall of the through hole; forming a capacitor dielectric layer, the capacitor dielectric layer is located on the bottom, inner sidewall and outer sidewall of the through hole; A second electrode is formed, and the second electrode is located on the surface of the capacitor dielectric layer, and also located in the through hole and on the outer sidewall of the through hole.

In some embodiments, the method further includes: forming an insulating layer, and the insulating layer is located on the substrate; the process step of forming the insulating layer and the second electrode includes: forming a first main body part and a second main body part, and the first main body part is located in the through hole , the second body part is located on the outer sidewall of the through hole, and the material of the second body part is the same as that of the first body part; an insulating layer is formed on the substrate, and the insulating layer is located on the sidewall of the second body part; The connection part spans the first main body part and the second main body part and is in contact with the top surface of the first main body part and the top surface of the second main body part, and the electrical connection part, the first main body part and the second main body part together constitute the second electrode.

In some embodiments, before forming the first electrode, the method further includes: forming an electrical connection layer on the substrate, and the electrical connection layer is electrically connected to the first electrode.

The technical solutions provided by the embodiments of the present disclosure have at least the following advantages: the capacitor structure of the semiconductor structure is located below the transistor, and this arrangement has the following advantages: The bit line structure is formed on the two-doped region. Compared with the traditional buried bit line, the process of forming the bit line is simpler; The limitation of the back-end process, then the multi-layer stacking of the capacitor structure and the crystal structure can be realized, and the storage capacity can be increased. The size of the single-layer structure reduces the difficulty of the process. In addition, the capacitor structure is a columnar capacitor, and in a limited space, the opposing area of the first electrode and the second electrode is larger, thereby increasing the storage capacity.

Description of drawings

One or more embodiments are exemplified by the pictures in the corresponding accompanying drawings, and these exemplary descriptions do not constitute limitations on the embodiments, unless otherwise stated, the drawings in the accompanying drawings do not constitute a scale limitation; In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the traditional technology, the accompanying drawings required in the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure. , for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort.

FIG. 1 is a schematic cross-sectional structural diagram of a semiconductor structure in a vertical direction according to an embodiment of the present disclosure;

FIG. 2 is a horizontal cross-sectional structural view of the capacitor structure of the embodiment shown in FIG. 1;

3 is a schematic cross-sectional structural diagram of a semiconductor structure in a vertical direction according to another embodiment of the present disclosure;

4 is a schematic cross-sectional structural diagram of a semiconductor structure in a vertical direction according to another embodiment of the present disclosure;

5 is a schematic cross-sectional structural diagram of a semiconductor structure in a vertical direction according to another embodiment of the present disclosure;

6 is a schematic cross-sectional structural diagram of a semiconductor structure in a vertical direction according to another embodiment of the present disclosure;

7 is a schematic cross-sectional structural schematic diagram of a semiconductor structure in a vertical direction according to another embodiment of the present disclosure;

FIG. 8 is a horizontal cross-sectional structural view of the transistor of the embodiment shown in FIG. 7;

FIG. 9 is a top view of the embodiment shown in FIG. 7 without an isolation layer;

10 to FIG. 25 are schematic structural diagrams corresponding to each step of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

Detailed ways

It can be seen from the background art that it is more difficult to improve the processing accuracy by improving the performance of the processing equipment. Improving the layout and formation of the semiconductor device structure is an effective way to make the semiconductor device meet the requirements of better performance and reduce the size of the integration. .

In order to solve the above problems, the embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. By adjusting the positional relationship between the capacitor structure and the transistor, the processing technology of the bit line of the semiconductor structure is simpler, and it is beneficial to realize the memory The 3D (3Dimensions) stacking increases the integration density of semiconductor structures. In addition, by increasing the opposing area of the first electrode and the second electrode, the capacitance capacity is increased, thereby increasing the storage capacity.

The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can appreciate that, in the various embodiments of the present disclosure, many technical details are provided for the reader to better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

1 is a schematic diagram of a vertical cross-sectional structure of a semiconductor structure provided by an embodiment of the present disclosure; FIG. 2 is a horizontal cross-sectional structural diagram of a capacitor structure of the embodiment shown in FIG. 1 ; FIG. 3 is provided by another embodiment of the present disclosure. A schematic view of a vertical cross-sectional structure of a semiconductor structure; FIG. 4 is a schematic view of a vertical cross-sectional structure of a semiconductor structure provided by another embodiment of the present disclosure; FIG. 5 is a vertical cross-sectional structure of a semiconductor structure provided by another embodiment of the present disclosure 6 is a schematic view of a vertical cross-sectional structure of a semiconductor structure provided by another embodiment of the present disclosure; FIG. 7 is a schematic view of a vertical cross-sectional structure of a semiconductor structure provided by another embodiment of the present disclosure; FIG. 9 is a top view of the embodiment shown in FIG. 7 without an isolation layer.

1 to 9, the semiconductor structure includes: a substrate 100; a first electrode 102, the first electrode 102 is located on the substrate 100, the first electrode 102 encloses a through hole extending away from the substrate 100; The two electrodes 104 are at least located in the through holes; the capacitor dielectric layer 103 is located between the first electrode 102 and the second electrode 104, and the second electrode 104, the capacitor dielectric layer 103 and the first electrode 102 constitute the capacitor structure 110; Transistor 111, the transistor 111 is located on the capacitor structure 110, and the transistor 111 includes a first doped region I and a second doped region III spaced along a direction perpendicular to the surface of the substrate 100, the first doped region I and the second electrode 104 is electrically connected, the doping type of the first doping region I and the second doping region III is one of N-type or P-type, and the doping type of the first doping region I and the second doping region III The same; the bit line 112, the bit line 112 is located on the transistor 111, and is electrically connected to the second doped region III.

Since the semiconductor structure includes a vertical gate-all-around (GAA, Gate-All-Around) transistor 111, and the manufacturing process temperature of the transistor 111 is compatible with the conductive material in the capacitor structure 110 and the conductive material in the bit line 112, the transistor The 111 can be stacked on the capacitor structure 110 or on the bit line 112, so that a 3D stacked memory device can be formed, which is beneficial to improve the integration density of the semiconductor structure. In addition, on the basis of 3D stacking, appropriately increasing the size of the single-layer memory device is beneficial to reduce the manufacturing difficulty. The bit line 112 is located on the transistor 111 , then, compared with the buried bit line 112 , the formation of the bit line 112 superimposed on the transistor 111 in this embodiment is simpler. Moreover, since the second electrode 104 is located in the through hole surrounded by the first electrode 102 , compared with the planar capacitor, the surface of the outer side wall of the second electrode 104 facing the inner wall of the through hole is opposite to the inner side wall of the through hole of the first electrode 102 . Larger area and larger capacitance.

Referring to FIG. 1, in this embodiment, since the first electrode 102 on the substrate 100 is in contact with the substrate 100, in order to improve the potential stability of the first electrode 102, the substrate 100 may be an insulating material, such as silicon dioxide, oxynitride Silicon, etc., and the substrate 100 may have a conductive layer (not shown in the figure). The conductive layer is electrically connected to the first electrode 102 for drawing out the first electrode 102, and a plurality of first electrodes 102 can be electrically connected to the same wire layer, which is beneficial to save wiring space and reduce the size of the semiconductor structure.

In some embodiments, the substrate 100 may also be a stacked structure composed of the first substrate layer 114 and the second substrate layer 115 . Taking the substrate 100 in contact with the first electrode 102 as the second substrate layer 115 as an example, the second substrate The bottom layer 115 may be an insulating material such as silicon oxide. And the second base layer 115 may have a conductive layer (not shown in the figure) for drawing out the first electrode 102 . The first base layer 114 is a material that can directly enter the manufacturing process to produce semiconductor devices. For example, the first base layer 114 can be silicon (SOI), silicon, germanium, silicon germanium, silicon carbide, arsenide on an insulating substrate Gallium or sapphire, etc.

Referring to FIG. 1 and FIG. 2 , in some embodiments, the through hole surrounded by the first electrode 102 of the capacitor structure 110 on the substrate 100 is a cylindrical through hole, that is, the capacitor structure 110 is a cylindrical capacitor, and the capacitor structure 110 has Smooth sides help avoid tip discharge. The capacitor dielectric layer 103 is located on the inner surface and bottom of the through hole of the first electrode 102 , that is, the capacitor dielectric layer 103 also surrounds the through hole extending away from the substrate 100 . The second electrode 104 fills the through hole surrounded by the capacitor dielectric layer 103 , and the second electrode 104 is in contact with the capacitor dielectric layer 103 close to the lower surface of the substrate 100 . In some other embodiments, the through hole enclosed by the first electrode 102 may be a square through hole or a columnar hole of other shapes, which also has a larger relative area of the plates compared to a planar capacitor, which can increase the capacitance.

In some embodiments, the first electrode 102 and the second electrode 104 are conductive materials, such as titanium nitride. In other embodiments, the material of the first electrode 102 and the second electrode 104 may also be at least one of conductive materials such as platinum nickel oxide, titanium, tantalum, cobalt, copper, tungsten, and tantalum nitride. The capacitor dielectric layer 103 is an insulating dielectric material, for example, the capacitor dielectric layer 103 is made of silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, At least one of high dielectric constant materials such as praseodymium oxide or barium strontium titanate.

In addition, the semiconductor structure includes a plurality of capacitor structures 110 spaced along a direction parallel to the top surface of the substrate 100 , and different capacitor structures 110 are separated from each other.

Continuing to refer to FIG. 1 , in some embodiments, the semiconductor structure may further include: an insulating layer 101 , the capacitor structure 110 is located in the insulating layer 101 , and the insulating layer 101 exposes the top surface of the second electrode 104 ; the through hole is away from the second electrode 104 The outer sidewall of the electrode is in contact with the insulating layer 101 ; the through hole is filled with the second electrode 104 and the capacitive dielectric layer 103 , and the top surface of the second electrode 104 is flush with the top surface of the capacitive dielectric layer 103 .

The insulating layer 101 is located between the capacitor structures 110 for supporting the capacitor structures 110 and isolating the second electrodes 102 of the adjacent capacitor structures 110 . The material of the insulating layer 101 includes at least one of silicon nitride, silicon oxynitride or silicon oxide. In some embodiments, the insulating layer 101 may also be a stacked film structure, as long as the insulating layer 101 can serve the purpose of support and isolation, and the embodiments of the present disclosure do not specifically limit the structure of the insulating layer 101 .

In some embodiments, the capacitive dielectric layer 103 may also be located on the top surface of the first electrode 102 , so that only the second electrode 104 is exposed on the top surface of the insulating layer 101 , which is beneficial to avoid the occurrence of the first electrode 102 caused by subsequent processing errors. A case of electrical connection with the first doped region I of the transistor 111 . In addition, the top surface of the second electrode 104 is flush with the top surface of the capacitor dielectric layer 103, which ensures that the opposing area of the first electrode 102 and the second electrode 104 is larger, which is beneficial to increase the capacitance. It can be understood that, in other embodiments, the top surface of the first electrode 102 may also be higher than the top surface of the capacitive dielectric layer 103 .

Referring to FIG. 3 , in some embodiments, the capacitive dielectric layer 103 is also located on the top surface of the first electrode 102 and the top surface of the insulating layer 101 , and the top surface of the second electrode 104 is flush with the top surface of the capacitive dielectric layer 103 .

Specifically, the capacitive dielectric layer 103 located on the top surface of the first electrode 102 and the top surface of the insulating layer 101 can be used as a planarization stop layer for the second electrode 104, and the second electrode 104 is only located in the through hole of the capacitive dielectric layer 103, and is different from that of the capacitor dielectric layer 103. The top surface of the capacitor dielectric layer 103 is flush, which not only facilitates the simplification of the manufacturing process, but also ensures that the capacitor structure 110 has a larger capacitance capacity.

Referring to FIG. 4 , in some embodiments, the second electrode 104 is also located on the outer sidewall of the through hole and the top surface of the first electrode 102 , and the second electrode 104 includes: a first main body part 120 , and the first main body part 120 is located in the through hole inside; the second body portion 121, the second body portion 121 is located on the outer sidewall of the through hole, the material of the second body portion 121 is the same as the material of the first body portion 120, and in the direction parallel to the surface of the substrate 100, the first body portion The thickness of the part 120 is greater than the thickness of the second main body part 121; the electrical connection part 122, the electrical connection part 122 spans the first main body part 120 and the second main body part 121, and is connected with the top surface of the first main body part 120 and the second main body part 121 The top surfaces are in contact. The electrical connection portion 122 is used to electrically connect the first body portion 120 of the inner sidewall of the through hole and the second body portion 121 of the outer sidewall of the through hole, so that the second electrode 104 is shared among a single capacitor. In addition, the outer sidewall and inner sidewall of the through hole have opposite second electrodes 104. Compared with the planar capacitor, by arranging the first main body portion 120 and the second main body portion 121, the capacitance capacity can be greatly increased, effectively improving the performance of semiconductor structures.

Specifically, the outer sidewall of the second electrode 104 also has an insulating layer 101 to isolate the second electrode 104 from the supporting capacitor structure 110 , so that the capacitors are independent of each other, and each capacitor is connected to a transistor 111 correspondingly. The first main body portion 120 and the second main body portion 121 are structures formed at the same time, that is, the materials constituting the first main body portion 120 and the second main body portion 121 are the same conductive material. Also, the thickness of the first main body portion 120 refers to the maximum thickness of the first main body portion 120 in a direction parallel to the surface of the substrate 100 . In addition, the capacitor dielectric layer 103 is also located on the surface of the substrate 100, and the capacitor dielectric layer 103 can be selectively removed or retained. Taking the capacitor dielectric layer 103 as an example, retaining the capacitor dielectric layer 103 can reduce the process time of the entire semiconductor manufacturing process and improve the semiconductor performance. Fabrication efficiency of the structure. It can be understood that, in other embodiments, the capacitive dielectric layer 103 may also be located only on the surface of the first electrode 102 , and may also achieve the effect of isolating the first electrode 102 and the second electrode 104 .

Continuing to refer to FIG. 4 , in some embodiments, for the same capacitor structure 110 , the second electrode 104 is an integrally formed structure. That is to say, the electrical connection portion 122 , the first main body portion 120 and the second main body portion 121 are formed of the same material at the same time, and this integrally formed structure makes the processing process of the second electrode 104 simpler. It can be understood that, in other embodiments, the materials of the electrical connection part 122 and the first main body part 120 and the second main body part 121 may also be different.

Referring to FIGS. 5 and 6 , in some embodiments, the first electrode 102 may include: a side portion 123 , the side portion 123 is a side wall portion of the through hole; a bottom connecting portion 124 , the bottom connecting portion 124 is parallel to the through holes On the bottom surface portion of the substrate 100 ; the semiconductor structure may further include: an electrical connection layer 108 , the electrical connection layer 108 is located on the substrate 100 and is electrically connected to the adjacent bottom connection portions 124 .

It should be noted that, since the substrate 100 has the electrical connection layer 108, the substrate 100 may not include a conductive layer. The electrical connection layer 108 electrically connects the first electrodes 102 of each capacitive structure 110 to the electrical connection layer 108 . The semiconductor structure with the electrical connection layer 108 not only ensures the independence of each capacitor structure 110 from each other, but also enables the first electrode 102 to be electrically connected to an external circuit through the electrical connection layer 108, so that the capacitor structure 110 of the semiconductor structure has a common first electrode. 102 , simplifying the process, which is beneficial to improve the space waste caused by adding the conductive layer.

In some embodiments, the material of the electrical connection layer 108 is the same as the material of the first electrode 102 layer, which is beneficial to avoid interface state defects and improve the conduction effect. It can be understood that, in other embodiments, the material of the electrical connection layer 108 and the material of the first electrode 102 may also be different, as long as it is only necessary to ensure that the first electrode 102 is electrically connected.

Referring to FIGS. 5 and 6 , in some embodiments, the electrical connection layer 108 and the bottom connection portion 124 may be integrally formed as a film layer, and the capacitive dielectric layer 103 is also located on the surface of the electrical connection layer 108 .

Specifically, the electrical connection layer 108 located at the bottom of the through hole directly serves as the bottom connection portion 124 of the first electrode 102 , which is beneficial to simplify the processing technology of the first electrode 102 . In addition, the capacitive dielectric layer 103 located on the surface of the electrical connection layer 108 prevents the second electrode 104 from being in contact with the electrical connection layer 108 .

Referring to FIG. 7 , in some embodiments, the side portion 123 and the bottom connecting portion 124 may be integrally formed as a film layer, and the electrical connecting layer 108 is also located between the bottom connecting portion 124 and the substrate 100 .

Specifically, the electrical connection layer 108 and the bottom connection portion 124 have different structures. A part of the surface of the electrical connection layer 108 away from the substrate 100 is in contact with the bottom connection portion 124 of the first electrode 102 , and the first electrode is directly drawn out through the electrical connection layer 108 . 102, to avoid adding other electrical connection structures to lead out the first electrode 103, thereby avoiding the waste of space by adding other electrical connection structures.

Referring to FIGS. 7 and 8 , the top of the second electrode 104 of each capacitor structure 110 of the semiconductor structure is in contact with the first doped region I of one transistor 111 . The first doped region I constitutes one of the source or the drain of the transistor 111 , and the second doped region III constitutes the other of the source or the drain of the transistor 111 . The first doping region I and the second doping region III can be N-type doping regions or P-type doping regions, the ions of the N-type doping regions include arsenic ions, phosphorus ions, antimony ions, etc., and the P-type doping regions The ions include boron ions, aluminum ions, gallium ions, etc.

In some embodiments, the transistor 111 may further include: a channel region II, the channel region II is located between the first doping region I and the second doping region III, and the channel region II, the first doping region The materials of the region I and the second doped region III at least include IGZO (Indium Gallium Zinc Oxide), IWO (Indium Tungsten Oxide) or ITO (Indium Tin Oxide). One or more, the above-mentioned materials have higher carrier mobility, which is beneficial to reduce the leakage current of the semiconductor structure during operation and improve the performance of the semiconductor structure.

The channel region II, the first doping region I, and the second doping region III of the transistor 111 constitute the semiconductor channel 105 of the transistor 111. In some embodiments, the material of the semiconductor channel 105 is IGZO, and the carrier mobility of IGZO is It is 20 to 50 times of the carrier mobility of polysilicon, which is beneficial to improve the carrier mobility of the channel region II, so as to reduce the power consumption of the semiconductor structure and improve the working efficiency of the semiconductor structure. In addition, the formation temperature of the IGZO semiconductor channel 105 is relatively low, which is convenient for forming on the metal structure, which is favorable for forming a 3D stacked memory structure, thereby increasing the integration density of the semiconductor structure and integrating more semiconductor structures in a limited space.

In some embodiments, the first doping region I, the channel region II, and the second doping region III constituting the semiconductor channel 105 are of an integrated structure, which is beneficial to improve the contact between the first doping region I and the channel region II. interface state defects, and improving the interface state defects between the channel region II and the second doped region III to improve the performance of the semiconductor structure. It can be understood that, in other embodiments, the semiconductor channel 105 may also have a three-layer structure, and each layer structure corresponds to the first doping region I, the channel region II, and the second doping region III.

In addition, referring to FIG. 8 , in some embodiments, the semiconductor channel 105 is a cylindrical structure, so that the side surface of the semiconductor channel 105 is a smooth transition surface, which is beneficial to avoid the phenomenon of tip discharge or leakage of the semiconductor channel 105, and further improves the semiconductor structure. electrical properties. It should be noted that, in other embodiments, the semiconductor channel 105 may also be a square column structure or other irregular structure. It can be understood that when the structure of the semiconductor channel 105 is a square columnar structure, the corners formed by the adjacent surfaces of the sidewalls of the square columnar structure can be rounded corners, which can also avoid the problem of tip discharge, and the square columnar structure can be a square columnar structure or Cuboid columnar structure.

7 and 8, the structure of the transistor 111 may further include: a gate dielectric layer 106, the gate dielectric layer 106 is disposed around the channel region II, and is located on the sidewall surface of the channel region II; a gate conductive layer 107, a gate conductive layer 107 is disposed around the channel region II, and is located on the sidewall surface of the gate dielectric layer 106 corresponding to the channel region II.

In some embodiments, the gate dielectric layer 106 is located on the sidewall surface of the semiconductor channel 105 in the channel region II and the sidewall surface of the semiconductor channel 105 in the second doping region III, for connecting the gate conductive layer 107 with the semiconductor channel 105 isolated. In addition, the gate dielectric layer 106 located on the sidewall surface of the semiconductor channel 105 in the second doped region III can protect the surface of the second doped region III, so as to avoid the second doped region during the formation of the gate conductive layer 107. The process damage caused by the surface of the impurity region III is beneficial to further improve the performance of the semiconductor structure. It can be understood that, in other embodiments, the gate dielectric layer 106 may only be located on the sidewall surface of the semiconductor channel 105 in the channel region II.

The material of the gate dielectric layer 106 includes at least one of silicon oxide, silicon nitride, silicon oxynitride or other high dielectric constant dielectric materials. The material of the gate conductive layer 107 includes at least one of polysilicon, titanium nitride, tantalum nitride, copper, tungsten or aluminum.

Continuing to refer to FIG. 7 , in some embodiments, the transistor 111 may further include an interlayer dielectric layer 113 . The interlayer dielectric layer 113 is located between the transistors 111 and exposes the top surface of the second doped region III of the transistor 111 for isolation. Adjacent transistors 111 and the role of support. And the interlayer dielectric layer 113 includes a first interlayer dielectric 125 , a second interlayer dielectric 126 and a third interlayer dielectric 127 . The first interlayer dielectric 125 is located on the sidewall surface of the semiconductor channel 105 where the first doped region I is located, the bottom surface of the gate dielectric layer 106 facing the substrate 100 and the bottom surface of the gate conductive layer 107 facing the substrate 100 . The second interlayer dielectric 126 is located on the sidewall surface of the gate dielectric layer 106 of the sidewall of the second doped region III and the top surface of the gate conductive layer 107 in the direction away from the substrate 100 . The third interlayer dielectric 127 is located on the sidewall surface of the gate conductive layer 107 , between the sidewalls of the different first interlayer dielectrics 125 and between the sidewalls of the different second interlayer dielectrics 126 . The first interlayer medium 125 , the second interlayer medium 126 and the third interlayer medium 127 may be separately formed structures, and the first interlayer medium 125 , the second interlayer medium 126 and the third interlayer medium 127 may The same insulating material, such as at least one of silicon oxide, silicon nitride, silicon carbonitride or silicon oxycarbonitride, is beneficial to form a good contact interface and improve the reliability of the semiconductor structure. It can be understood that, in other embodiments, the first interlayer dielectric 125 , the second interlayer dielectric 126 and the third interlayer dielectric 127 may also be different insulating materials.

Referring to FIG. 7 , in some embodiments, the semiconductor structure may further include a bit line 112 and an isolation layer 109 . The bit line 112 is located on a part of the surface of the interlayer dielectric layer 113 and is connected to the second doped region III of the transistor 111 and the gate dielectric layer. A portion of the top surface 106 away from the substrate 100 is in contact, and an isolation layer 109 covers the surface of the bit lines 112 to isolate the different bit lines 112 and to support other semiconductor structures stacked on the bit lines 112 . The material of the isolation layer 109 may include at least one of silicon oxide, silicon nitride or silicon oxynitride. In addition, the material of the interlayer dielectric layer 113 and the isolation layer 109 is the same, which is beneficial to improve the interface state defects between the interlayer dielectric layer 113 and the isolation layer 109, improve the performance of the semiconductor structure, and is beneficial to reduce the processing steps of the semiconductor structure , reducing the manufacturing cost and complexity of semiconductor structures. It can be understood that, in other implementations, the material of the interlayer dielectric layer 113 and the material of the isolation layer 109 may be different.

Specifically, a part of the surface of the interlayer dielectric layer 113 may have a plurality of bit lines 112 arranged at intervals, and each bit line 112 may be in electrical contact with at least one second doped region III. For example, referring to FIG. 9 , each bit line 112 is in contact with two second doped regions III. The number of the second doped regions III that are in contact and electrically connected to each bit line 112 can be reasonably set according to actual electrical requirements.

In the semiconductor structure provided by the above embodiment, on the basis that the capacitor structure 110 is a columnar structure, the through hole enclosed by the first electrode 102 and the outer side of the through hole have opposite second electrodes 104, which greatly increases the capacitance structure. The relative plate area of 110 increases the capacitance. The electrical connection layer 108 enables the semiconductor structure to have independent capacitance structures 110, and also enables the first electrode 102 to be electrically connected to an external circuit through the electrical connection layer 108, so that the semiconductor structure has a common first electrode 102, which is beneficial to simplify the process and avoid Waste of space. By adjusting the positional relationship between the transistor 111 and the capacitor structure 110 , the semiconductor structure satisfies the multi-layer stacking condition, and under the same volume, the integration density of the semiconductor structure is increased. In addition, the arrangement of the transistors 111 on the capacitor structure 110 not only makes the formation process of the bit line 112 simpler, but also appropriately increases the size of the single-layer semiconductor structure, which is beneficial to reduce the complexity of manufacturing.

Correspondingly, another aspect of the embodiments of the present disclosure further provides a method for fabricating a semiconductor structure for forming the above-mentioned semiconductor structure. It should be noted that, for the parts that are the same as or corresponding to the foregoing embodiments, reference may be made to the detailed descriptions of the foregoing embodiments, which will not be repeated below.

10 to FIG. 25 are schematic structural diagrams corresponding to each step of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

Referring to FIG. 10 , a method of fabricating a semiconductor structure includes: providing a substrate 100 .

The surface of the substrate 100 is formed with an insulating material or the substrate 100 itself is an insulating material, so that the semiconductor structure in contact with the substrate 100 can be prevented from being affected by unstable electrical signals and affect the electrical performance of the semiconductor structure.

Referring to FIG. 11 , in some embodiments, an electrical connection layer 108 may be formed on the substrate 100 . The electrical connection layer 108 is a conductive film layer located on the top surface of the substrate 100 and is electrically connected to the first electrode 102 formed subsequently. In addition, the electrical connection layer 108 may be formed by physical vapor deposition, evaporation, sputtering, or the like. For the materials of the substrate 100 and the electrical connection layer 108 , reference may be made to the corresponding descriptions of the foregoing embodiments, which will not be repeated here.

12 to 14 , a first electrode 102 is formed on the substrate 100 , and the first electrode 102 surrounds a through hole extending in a direction away from the substrate 100 .

Specifically, referring to FIG. 14 , mutually independent first electrodes 102 may be formed on the electrical connection layer 108 of the substrate 100 , and the first electrodes 102 are in contact with the electrical connection layer 108 toward the bottom surface of the substrate 100 . In this way, there is no need to add other lead layers, and the first electrode 102 can be directly led out through the electrical connection layer 108 , which can save space and help reduce the size of the semiconductor structure. In addition, for the shape of the through hole, reference may be made to the corresponding descriptions of the foregoing embodiments, which will not be repeated here.

12 to 14, in some embodiments, the step of forming the first electrode 102 may further include: forming an insulating film on the substrate 100, and the insulating film has a groove through the thickness of the insulating film; forming the first electrode 102, the first electrode 102 is located at the bottom and sidewalls of the groove. The groove in the insulating film defines the position of the first electrode 102. With the assistance and support of the insulating film, conductive materials are formed on the sidewall and bottom of the groove to obtain the first electrode of the columnar capacitor with larger capacitance. 102. Also, the material of the insulating film may be silicon oxide.

Specifically, firstly, an insulating film may be formed on the electrical connection layer 108 of the substrate 100 by means of deposition, and the thickness of the insulating film may be determined according to the required height of the columnar capacitance. Then, a groove is formed on the insulating film by means of photolithography, etching and other processes, and a part of the top surface of the electrical connection layer 108 is exposed at the bottom of the groove. Moreover, the groove formed here may be a circular hole-shaped groove extending toward the direction of the substrate 100 . It can be understood that, in other embodiments, the grooves can also be square-hole grooves or grooves of other shapes. Then, a layer of conductive material is formed as the first electrode 102 on the surface of the electrical connection layer 108 exposed at the bottom of the groove, the sidewall of the groove, and the top surface of the insulating film, and the top of the insulating film is removed by maskless etching. The conductive material of the surface is formed, thereby forming the first electrodes 102 independent of each other. In addition, the manner of forming the first electrode 102 may be an atomic layer deposition process.

In some embodiments, photoresist can also be used to cover the through hole, and then the first electrode 102 on the top surface of the insulating film can be removed, and the first electrode 102 can also be obtained. It should be noted that, at this time, the first electrode 102 located at the bottom of the through hole will not be etched and consumed under the coverage of the photoresist, and thus remains on the electrical connection layer 108 in the through hole.

Referring to FIG. 15 to FIG. 20 , after forming the first electrode 102 , it also includes forming the second electrode 104 and the capacitor dielectric layer 103 . The second electrode 104 is located at least in the through hole, the capacitor dielectric layer 103 is located between the first electrode 102 and the second electrode 104 , and the second electrode 104 , the capacitor dielectric layer 103 and the first electrode 102 constitute the capacitor structure 110 . Also, the method of forming the second electrode 104 may be an atomic layer deposition process.

The method of forming the capacitive dielectric layer 103 and the second electrode 104 is specifically described by the following embodiments.

Referring to FIGS. 15 to 16 , in some embodiments, the remaining insulating film can be used as the insulating layer 101 , and then, the capacitive dielectric layer 103 is formed, and the capacitive dielectric layer 103 is located at the bottom and sidewalls of the through hole; the second electrode 104 layer is formed, and the first The second electrode 104 layer is located on the surface of the capacitor dielectric layer 103 and fills the through hole. Remaining the remaining insulating film as the insulating layer 101 can play a supporting role when forming the second electrode 104 opposite to the inner sidewall of the through hole.

Specifically, the capacitor dielectric layer 103 is formed on the top surface of the insulating layer 101 away from the substrate 100 , the sidewalls, the top surface and the bottom of the through hole formed by the first electrode 102 . Then, a second electrode 104 is formed on the capacitor dielectric layer 103 , and the second electrode 104 fills the through hole formed in the capacitor dielectric layer 103 . Using the planarization process, the capacitor dielectric layer 103 is used as a planarization stop layer, and the second electrode 104 on the capacitor dielectric layer 103 located on the top surface of the insulating layer 101 and the top surface of the first electrode 102 is removed to obtain the top surface of the capacitor dielectric layer 103 The second electrode 104 with a flush surface. In this way, the process flow can be simplified and the manufacturing complexity can be reduced. In other embodiments, the method of removing the second electrode 104 located on the top surface of the insulating layer 101 and the capacitor dielectric layer 103 on the top surface of the first electrode 102 may also be a mask etching method, that is, covering the pass-through with photoresist The top surface of the second electrode 104 in the hole is removed, and the remaining second electrode 104 is removed.

17 and 18 , in some embodiments, the steps of forming the capacitor dielectric layer 103 and the second electrode 104 may further include: removing the remaining insulating film to expose the outer sidewalls of the through holes; forming the capacitor dielectric layer 103 , the capacitor dielectric layer 103 is located at the bottom, inner sidewall and outer sidewall of the through hole; a second electrode 104 is formed, and the second electrode 104 is located on the surface of the capacitor dielectric layer 103 and also located in the through hole and on the outer sidewall of the through hole. In this way, the second electrode 104 can be formed on both the inner sidewall and the outer sidewall of the through hole of the first electrode 102 to further increase the relative area of the electrode plates, thereby increasing the capacitance.

Specifically, the insulating films on the electrical connection layer 108 of the substrate 100 and the outer sidewalls of the through holes are removed, and the capacitor dielectric layer 103 is formed on the electrical connection layer 108 and the first electrode 102 by a functional deposition process, and then the capacitor dielectric layer 103 is formed on the electrical connection layer 108 and the first electrode 102 by a functional deposition process A second electrode 104 is formed on the layer 103 . The method for forming the second electrode 104 is an atomic layer deposition process.

19 to 20 , in some embodiments, the step of forming the second electrode 104 may further include: forming an insulating layer 101 on the substrate 100 ; and forming the insulating layer 101 and the second electrode 104 The steps include: forming a first main body part 120 and a second main body part 121, the first main body part 120 is located in the through hole, the second main body part 121 is located in the outer side wall of the through hole, the material of the second main body part 121 is the same as that of the first main body part The material of 120 is the same; an insulating layer 101 is formed on the substrate 100, and the insulating layer 101 is located on the sidewall of the second main body part 121; And in contact with the top surface of the first main body part 120 and the top surface of the second main body part 121 , the electrical connection part 122 , the first main body part 120 and the second main body part 121 together constitute the second electrode 104 .

Specifically, after the second electrode 104 on the capacitor dielectric layer 103 is formed, maskless etching is used to remove the top of the through hole in the capacitor dielectric layer 103 and the second electrode on the surface of the capacitor dielectric layer 103 on the electrical connection layer 108 Step 104 , the first main body part 120 and the second main body part 121 of the second electrode 104 are obtained. An insulating layer 101 is formed on the outer sidewall of the second body portion 121 to insulate and isolate the second electrodes 104 independent of each other, and play a supporting role for subsequent semiconductor structures. The insulating layer 101 exposes the top surface of the first body portion 120 , the top surface of the second body portion 121 , and the top surface of the capacitor dielectric layer 103 away from the substrate 100 . The material of the electrical connection portion 122 is formed on the top surface of the insulating layer 101 away from the substrate 100 , the top surface of the first body portion 120 , the top surface of the second body portion 121 , and the top surface of the capacitive dielectric layer 103 away from the substrate 100 , and the insulation is removed. The layer 101 is away from the electrical connection portion 122 on the top surface of the substrate 100 , electrically connecting the first body portion 120 and the second body portion 121 of the second electrode 104 and forming the second electrode 104 independent of each other.

In some embodiments, the electrical connection portion 122 is formed as follows: the top surface of the insulating layer 101 away from the substrate 100 , the top surface of the first body portion 120 , the top surface of the second body portion 121 , and the capacitor dielectric layer 103 away from the substrate A layer is formed on the top surface of 100, such as a conductive material and a mask layer, and a SADP (Self-aligned Double Patterning) process is used to form a plurality of raised first mask patterns in one direction, In the other direction, a plurality of raised second mask patterns are formed by the SADP process. Selectively etch the area where the first mask pattern and the second mask pattern intersect, remove the mask layer and the conductive material under the mask layer until the insulating layer 101 is exposed, and then remove the remaining mask layer, Remaining material of the electrical connection portion 122 is retained to form the electrical connection portion 122 . The embodiment of the present disclosure can precisely control the position and shape of the electrical connection portion 122 to form mutually independent electrical connection portions 122 , thereby realizing that the first main body portion 120 and the second main body portion 121 are connected through the electrical connection portion 122 to form a mutually independent electrical connection portion 122 . The second electrode 104 is an independent and one-piece structure. In other embodiments, the electrical connection portion 122 may also be formed by using a SAQP (Self-aligned Quadruple Patterning) process to form the electrical connection portion 122 .

In some embodiments, photoresist is used to cover the outer sidewall, inner sidewall, bottom and second electrode 104 on the top of the through hole surrounded by the capacitor dielectric layer 103 , and the capacitor dielectric layer on the outer electrical connection layer 108 of the through hole is removed by etching. The second electrode 104 on the surface of 103 is directly obtained, and the second electrode 104 including the first main body part 120 , the second main body part 121 and the electrical connection part 122 is directly obtained. In addition, after removing the photoresist, an insulating layer 101 is formed, and a planarization process is used to expose the insulating layer 101 to the top surface of the second electrode 104, so that the first doped region I of the transistor 111 and the second electrode 104 to be formed subsequently touch.

Referring to FIGS. 21 to 23 , a transistor 111 is formed, the transistor 111 is located on the capacitor structure 110 , and the transistor 111 includes a first doped region I and a second doped region III spaced along a direction perpendicular to the surface of the substrate 100 . The doping region I is electrically connected to the second electrode 104, the doping type of the first doping region I and the second doping region III is one of N-type or P-type, and the first doping region I and the second doping region The doping type of the doped region III is the same. It should be noted that, forming the transistor 111 may further include: forming a channel region II, the channel region II is located between the first doping region I and the second doping region III, and the channel region II and the first doping region II The region I and the second doped region III constitute the semiconductor channel 105 of the transistor 111; the gate dielectric layer 106 is formed, and the gate dielectric layer 106 is arranged around the channel region II and is located on the sidewall surface of the channel region II; the gate conductive layer 107 is formed , the gate conductive layer 107 is disposed around the channel region II, and is located on the sidewall surface of the gate dielectric layer 106 corresponding to the channel region II.

In addition, before forming the transistor 111 , it may further include forming a first interlayer dielectric 125 . Referring to FIG. 21 , the first interlayer dielectric 125 is on a part of the surface of the second electrode 104 and the surface of the insulating layer 101 , and inside the first interlayer dielectric 125 A groove extending toward the top surface of the second electrode 104 is formed, and a part of the top surface of the second electrode 104 is exposed at the bottom of the groove. Wherein, the groove may be a circular hole-shaped groove. Referring to FIG. 22 , a semiconductor channel 105 is formed in the groove, and then a partial thickness of the first interlayer dielectric 125 is removed to form a gate dielectric layer 106 , a gate conductive layer 107 and a second interlayer dielectric 126 . Since the gate conductive layers 107 of different transistors 111 are all connected to each other at this time, referring to FIG. 23 , the gate conductive layers 107 are interrupted by selective etching, thereby forming the gate conductive layers 107 that are independent of each other or have a specified connection mode. . And a third interlayer dielectric 127 is formed between the mutually independent gate conductive layers 107 . The first interlayer dielectric 125 , the second interlayer dielectric 126 and the third interlayer dielectric 127 constitute the interlayer dielectric layer 113 , and the interlayer dielectric layer 113 is conducive to achieving better insulation and isolation effect of the transistor, and is a subsequent semiconductor structure Provide support.

Referring to FIG. 24, a bit line 112 is formed, and the bit line 112 is located on the transistor 111 and is electrically connected to the second doped region III.

Specifically, the bit line 112 is formed on the surface of the interlayer dielectric layer 113, the second doped region III of the transistor 111, and the top surface of the gate dielectric layer 106 away from the substrate 100, and patterned to form independent or specified connection modes. bit line 112 . In addition, an isolation layer 109 is formed on the surface of the bit lines 112 , so that the independent bit lines 112 have better insulation and isolation effect, and provide support for the stacked semiconductor structure formed on the subsequent bit lines 112 .

Referring to FIG. 25 , the capacitor structure 110 , the transistor 111 and the bit line 112 adjacent to the substrate 100 constitute a memory cell array 130 , at least one memory cell array 130 is formed on the isolation layer 109 , and a plurality of memory cell arrays 130 are far from the top of the substrate 100 direction of the face.

The manufacturing method of the semiconductor structure provided by the above embodiments can form the columnar capacitor structure 110 sharing the first electrode 102 , the transistor 111 structure arranged on the capacitor structure 110 and the non-buried bit line 112 . Sharing the first electrode 102 can save space, and the transistor 111 structure arranged on the capacitor structure 110 can realize the multi-layer stacking of the memory cell array, which is beneficial to further realize the size reduction on the premise of ensuring the semiconductor structure has better performance . In addition, the manufacturing complexity of the non-buried bit line 112 is reduced, and the columnar capacitor structure 110 has a larger opposing electrode area, which improves the performance of the semiconductor structure.

Those of ordinary skill in the art can understand that the above embodiments are specific examples for realizing the present disclosure, and in practical applications, various changes in form and details can be made without departing from the spirit and the spirit of the present disclosure. scope. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the scope defined by the claims.

Claims (15)

1. a semiconductor structure, is characterized in that, comprises: base; a first electrode, the first electrode is located on the substrate, and the first electrode surrounds a through hole extending in a direction away from the substrate; a second electrode, the second electrode is at least located in the through hole; a capacitor dielectric layer, the capacitor dielectric layer is located between the first electrode and the second electrode, and the second electrode, the capacitor dielectric layer and the first electrode constitute a capacitor structure; a transistor, the transistor is located on the capacitor structure, and the transistor includes a first doped region and a second doped region spaced along a direction perpendicular to the surface of the substrate, the first doped region and the The second electrode is electrically connected, the doping type of the first doping region and the second doping region is one of N-type or P-type, and the first doping region and the second doping region are The doping types of the doped regions are the same; a bit line, which is located on the transistor and is electrically connected to the second doped region. 2 . The semiconductor structure of claim 1 , further comprising: an insulating layer, the capacitor structure is located in the insulating layer, and the insulating layer exposes the top surface of the second electrode; the The outer sidewall of the through hole away from the second electrode is in contact with the insulating layer; the through hole is jointly filled by the second electrode and the capacitor dielectric layer, and the top surface of the second electrode is in contact with the insulating layer. The top surface of the capacitor dielectric layer is flush. 3 . The semiconductor structure of claim 2 , wherein the capacitor dielectric layer is further located on the top surface of the first electrode and the top surface of the insulating layer, and the second electrode top surface is connected to the capacitor 3 . The top surface of the dielectric layer is flush. 4. The semiconductor structure of claim 1, wherein the second electrode is further located on the outer sidewall of the through hole and the top surface of the first electrode, and the second electrode comprises: a first main body part, the first main body part is located in the through hole; a second main body part, the second main body part is located on the outer side wall of the through hole, the material of the second main body part is the same as the material of the first main body part, and in a direction parallel to the surface of the base, The thickness of the first body portion is greater than the thickness of the second body portion; an electrical connection part, the electrical connection part spans the first main body part and the second main body part, and is in contact with the top surface of the first main body part and the top surface of the second main body part. 5 . The semiconductor structure of claim 4 , wherein for the same capacitor structure, the second electrode is an integrally formed structure. 6 . 6. The semiconductor structure of claim 1, wherein the first electrode comprises: a side part, the side part is the side wall part of the through hole; a bottom connecting part, the bottom connecting part is a bottom surface part of the through hole parallel to the base; The semiconductor structure further includes: an electrical connection layer located on the substrate and electrically connected to the adjacent bottom connection parts. 7 . The semiconductor structure of claim 6 , wherein the electrical connection layer and the bottom connection portion are integrally formed as a film layer, and the capacitive dielectric layer is also located on the surface of the electrical connection layer. 8 . 8 . The semiconductor structure of claim 6 , wherein the side portion and the bottom connecting portion are integrally formed into a film layer, and the electrical connecting layer is also located between the bottom connecting portion and the substrate. 9 . between. 9. The semiconductor structure of claim 1, wherein the transistor further comprises: a channel region, the channel region is located between the first doping region and the second doping region, and the channel region, the first doping region and the second doping region The material includes at least one or more of IGZO, IWO or ITO; a gate dielectric layer, the gate dielectric layer is disposed around the channel region and is located on the sidewall surface of the channel region; A gate conductive layer, the gate conductive layer is disposed around the channel region and is located on the sidewall surface of the gate dielectric layer corresponding to the channel region. 10. A method for manufacturing a semiconductor structure, comprising: provide a base; forming a first electrode on the substrate, the first electrode enclosing a through hole extending away from the substrate; forming a second electrode, the second electrode is located at least in the through hole; forming a capacitor dielectric layer, the capacitor dielectric layer is located between the first electrode and the second electrode, and the second electrode, the capacitor dielectric layer and the first electrode constitute a capacitor structure; A transistor is formed, the transistor is located on the capacitor structure, and the transistor includes a first doped region and a second doped region spaced along a direction perpendicular to the surface of the substrate, the first doped region and the The second electrode is electrically connected, the doping type of the first doping region and the second doping region is one of N-type or P-type, and the first doping region and the first doping region are The doping types of the two doped regions are the same; A bit line is formed, the bit line is located on the transistor and is electrically connected to the second doped region. 11. The method of manufacturing a semiconductor structure according to claim 10, wherein the step of forming the first electrode comprises: forming an insulating film on the substrate, and the insulating film has a groove through the thickness of the insulating film; The first electrode is formed, and the first electrode is located at the bottom and sidewalls of the groove. 12. The method for manufacturing a semiconductor structure according to claim 11, wherein the insulating film is left as an insulating layer; the step of forming the capacitor dielectric layer and the second electrode comprises: forming the capacitive dielectric layer, where the capacitive dielectric layer is located at the bottom and sidewalls of the through hole; A second electrode layer is formed, the second electrode layer is located on the surface of the capacitor dielectric layer and fills the through hole. 13. The method for manufacturing a semiconductor structure according to claim 11, wherein the step of forming the capacitor dielectric layer and the second electrode comprises: removing the remaining insulating film to expose the outer sidewall of the through hole; forming the capacitive dielectric layer, the capacitive dielectric layer is located at the bottom, inner sidewall and outer sidewall of the through hole; The second electrode is formed, and the second electrode is located on the surface of the capacitor dielectric layer, and is also located in the through hole and on the outer sidewall of the through hole. 14. The method for fabricating a semiconductor structure according to claim 13, further comprising: forming an insulating layer, the insulating layer being located on the substrate; the process steps of forming the insulating layer and the second electrode include: A first main body part and a second main body part are formed, the first main body part is located in the through hole, the second main body part is located in the outer side wall of the through hole, and the material of the second main body part is the same as the material of the through hole. The material of the first body part is the same; forming the insulating layer on the substrate, the insulating layer being located on the sidewall of the second body portion; An electrical connection portion is formed, the electrical connection portion spans the first body portion and the second body portion, and is in contact with the top surface of the first body portion and the top surface of the second body portion, the electrical connection portion The connection part, the first main body part and the second main body part together constitute the second electrode. 15 . The method for manufacturing a semiconductor structure according to claim 10 , wherein before forming the first electrode, further comprising: forming an electrical connection layer on the substrate, the electrical connection layer and the first electrode 15 . An electrode is electrically connected.

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