CN114551376A - Semiconductor packaging structure and manufacturing method thereof - Google Patents
Semiconductor packaging structure and manufacturing method thereof Download PDFInfo
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Abstract
本申请实施例公开了一种半导体封装结构及其制作方法，该封装结构包括：基板、多个支撑体、主芯片以及塑封体；其中，多个支撑体与主芯片上的多个预设支撑位一一对应粘接，使得多个支撑体能够对主芯片起到良好的支撑作用，并避免所述主芯片存在大部分的悬空区域，有助于提高所述半导体封装结构的可靠性，并且多个支撑体还能够在塑封过程中对主芯片进行支撑，提高所述半导体封装结构的可靠性。另外，金属微凸点的高度和宽度可以控制，使得支撑体的高度和宽度可以根据主芯片的结构以及实际需求进行控制，有助于保证支撑体对主芯片的支撑，且金属微凸点的宽度相对于支撑芯片宽度较小，有助于提高所述半导体封装结构的封装密度。
Embodiments of the present application disclose a semiconductor packaging structure and a manufacturing method thereof. The packaging structure includes: a substrate, a plurality of supports, a main chip and a plastic sealing body; wherein the plurality of supports and a plurality of preset supports on the main chip One-to-one bonding, so that a plurality of supports can play a good supporting role on the main chip, and avoid most of the floating area of the main chip, which helps to improve the reliability of the semiconductor package structure, and The plurality of support bodies can also support the main chip during the plastic packaging process, thereby improving the reliability of the semiconductor packaging structure. In addition, the height and width of the metal micro-bumps can be controlled, so that the height and width of the support body can be controlled according to the structure of the main chip and actual needs, which helps to ensure that the support body supports the main chip, and the metal micro-bumps The width is smaller than that of the supporting chip, which helps to improve the packing density of the semiconductor package structure.
Description
Technical Field
The present disclosure relates to the field of semiconductor packaging technologies, and in particular, to a semiconductor package structure and a method for manufacturing the same.
Background
With the increasing demands for large capacity, miniaturization, thinning and high integration of electronic devices, higher requirements are also put forward on the packaging density of electronic devices to reduce the size of the electronic device packaging structure, and further reduce the volume occupied by the electronic device package during assembly.
At present, a commonly used semiconductor package structure includes a substrate, a supporting chip and a plurality of components on the surface of the substrate, and further includes a main chip stacked on the supporting chip, wherein the main chip is fixed on the supporting chip to improve the packaging density of the package structure, thereby reducing the size of the package structure. However, in general, when the main chip is fixed on the supporting chip, the main chip has a large suspended area, that is, a supporting surface of the main chip has a large area which is not supported by the supporting chip, so that the main chip is deformed or bent in a process of wire bonding between the main chip and the substrate, and in a serious case, the main chip is cracked to damage the main chip, which affects normal operation of the main chip, and further affects normal operation of the semiconductor package structure. Therefore, it is important for those skilled in the art to provide a semiconductor package structure that can contribute to the suppression of the deformation, bending, and cracking of the main chip.
Disclosure of Invention
In order to solve the above technical problem, embodiments of the present application provide a semiconductor package structure, which can help to suppress deformation, bending, and cracking of a main chip, and further help to improve reliability of the semiconductor package structure.
In order to solve the above problem, the embodiment of the present application provides the following technical solutions:
a semiconductor package structure, comprising:
a substrate;
the plurality of supporting bodies are positioned on the surface of the substrate and comprise a plurality of metal micro-bumps which are sequentially arranged along one side departing from the surface of the substrate;
the main chip is connected with the substrate, one side of the main chip, facing the surface of the substrate, is provided with a plurality of preset supporting positions, and the plurality of supporting bodies are respectively bonded with the plurality of preset supporting positions in a one-to-one correspondence manner, so that the supporting bodies support the main chip;
and the plastic package body is positioned on the surface of the substrate, extends to one side back to the surface of the substrate and covers the surface of the substrate, the support body and the main chip.
Optionally, the height of the metal micro-bump ranges from 20um to 50um, and the width of the metal micro-bump ranges from 30um to 100 um;
the width of the metal micro-bump is the radial length of the metal micro-bump along a first direction, the height of the metal micro-bump is the radial length of the metal micro-bump along a second direction, the first direction is parallel to the surface of the substrate, and the second direction is perpendicular to the first direction.
Optionally, the main chip includes a plurality of sub-chips sequentially arranged along a side away from the substrate surface, at least one of the plurality of sub-chips except the first sub-chip has a suspension region, and a part of the plurality of preset support positions is located in the first sub-chip, and another part of the plurality of preset support positions is located in the suspension region;
one part of the plurality of supporting bodies is adhered to a preset supporting phase positioned on the first sub-chip, and the other part of the plurality of supporting bodies is adhered to a preset supporting phase positioned in the suspension area;
the first sub-chip is the sub-chip closest to the substrate surface among the plurality of sub-chips, and the suspension area is an area where the other sub-chips except the first sub-chip are not shielded from one side of the substrate surface.
Optionally, the method further includes: the first bonding pad and the second bonding pad are positioned on the surface of the substrate, the first bonding pad is not connected with the internal circuit of the substrate, the second bonding pad is connected with the internal circuit of the substrate, and the support body is fixed on one side of the first bonding pad, which is far away from the surface of the substrate;
and the third bonding pad is positioned on one side of the main chip, which deviates from the surface of the substrate, is connected with the internal circuit of the main chip, and is connected with the second bonding pad.
Optionally, the method further includes: the control chip and the fourth bonding pad are positioned on the surface of the substrate, a fifth bonding pad is arranged on one side, away from the surface of the substrate, of the control chip, and the fourth bonding pad is connected with the fifth bonding pad;
the fourth bonding pad is connected with the internal circuit of the substrate, and the fifth bonding pad is connected with the internal circuit of the control chip.
Optionally, the first bonding pad, the second bonding pad, the third bonding pad, the fourth bonding pad and the fifth bonding pad are made of the same material and are all one of gold, silver, copper and aluminum.
A manufacturing method of a semiconductor packaging structure comprises the following steps:
providing a substrate;
forming a plurality of supporting bodies, fixing the supporting bodies on the surface of the substrate, wherein the supporting bodies comprise a plurality of metal micro-bumps which are sequentially arranged along one side departing from the surface of the substrate;
providing a main chip, connecting the main chip with the substrate, wherein one side of the main chip, which faces the surface of the substrate, is provided with a plurality of preset supporting positions, and bonding the plurality of supporting bodies and the plurality of preset supporting positions in a one-to-one correspondence manner so that the supporting bodies support the main chip;
and forming a plastic package body, wherein the plastic package body is positioned on the surface of the substrate, extends to one side away from the surface of the substrate and covers the surface of the substrate, the support body and the main chip.
Optionally, the main chip includes a plurality of sub-chips sequentially arranged along a side away from the substrate surface, at least one of the plurality of sub-chips except the first sub-chip has a suspension region, and a part of the plurality of preset support positions is located in the first sub-chip, and another part of the plurality of preset support positions is located in the suspension region; bonding the plurality of support bodies and the plurality of preset support positions in a one-to-one correspondence manner comprises:
bonding a part of the plurality of support bodies with a preset support position on the first sub-chip;
bonding the other part of the support body with a preset support phase positioned in the suspension area;
the first sub-chip is the sub-chip closest to the substrate surface among the plurality of sub-chips, and the suspension area is an area where the other sub-chips except the first sub-chip are not shielded from one side of the substrate surface.
Optionally, the surface of the substrate has a first pad and a second pad, where the first pad is not connected to the internal circuit of the substrate, and the second pad is connected to the internal circuit of the substrate; a third bonding pad is arranged on one side of the main chip, which is far away from the surface of the substrate, and the third bonding pad is connected with an internal circuit of the main chip; fixing the support body on the surface of the substrate, and connecting the main chip with the substrate comprises:
fixing the support body on one side, away from the substrate surface, of the first bonding pad so as to fix the support body on the substrate surface;
and connecting the second bonding pad with the third bonding pad so as to connect the main chip with the substrate.
Optionally, the surface of the substrate is provided with a fourth pad, and the fourth pad is connected with the internal circuit of the substrate; the manufacturing method also comprises the following steps:
providing a control chip, wherein a fifth bonding pad is arranged on one side of the control chip, which is far away from the surface of the substrate, and the fifth bonding pad is connected with an internal circuit of the control chip;
arranging the control chip on the surface of the substrate;
and connecting the fourth bonding pad with the fifth bonding pad so as to connect the control chip with the substrate.
Compared with the prior art, the technical scheme has the following advantages:
the technical scheme provided by the application comprises the following steps: the chip comprises a substrate, a plurality of supporting bodies, a main chip and a plastic package body; the plurality of supporting bodies are positioned on the surface of the substrate, and the supporting bodies comprise a plurality of metal micro-bumps which are sequentially arranged along one side departing from the surface of the substrate; the main chip is connected with the internal circuit of the substrate to ensure the normal work of the semiconductor packaging structure, one side of the main chip, which faces the surface of the substrate, is provided with a plurality of preset supporting positions, and the plurality of supporting bodies are bonded with the plurality of preset supporting positions in a one-to-one correspondence manner, so that the supporting bodies support the main chip. It should be noted that the preset support positions on the side of the main chip facing the substrate surface are obtained through mechanical analysis according to the structure of the main chip, and the support bodies are bonded to the preset support positions in a one-to-one correspondence manner, so that the support bodies can well support the main chip, most of the suspended areas of the main chip are avoided, the main chip can be prevented from being deformed, bent or even cracked, and the reliability of the semiconductor package structure can be improved. And the supporting body comprises a plurality of metal micro-bumps which are sequentially arranged along one side departing from the surface of the substrate, and the height and the width of each metal micro-bump can be controlled, so that the height and the width of the supporting body can be controlled according to the structure and the actual requirement of a main chip, and the supporting of the main chip by the supporting body is favorably ensured. Meanwhile, the width of the metal micro-bump is smaller than that of a supporting chip in the conventional semiconductor packaging structure, so that the supporting body can have a larger height-width ratio relative to the supporting chip, and the packaging density of the semiconductor packaging structure is improved.
The semiconductor packaging structure comprises a plastic packaging body, wherein the plastic packaging body covers the surface of the substrate, the supporting body and the main chip so as to improve the mechanical strength of the semiconductor packaging structure and prevent water vapor in the external environment from entering the inside of the semiconductor packaging structure, and meanwhile, the supporting body can also support the main chip in the plastic packaging process so as to prevent the main chip from being bent, deformed or even cracked in the plastic packaging process, so that the reliability of the semiconductor packaging structure is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a conventional semiconductor package structure;
FIG. 2 is a schematic structural diagram of a semiconductor package structure proposed in patent CN100424871C
Fig. 3 is a schematic structural diagram of a semiconductor package structure according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of another semiconductor package structure according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of the dimensions of a metal micro-bump;
fig. 6 is a schematic structural diagram of another semiconductor package structure according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of another semiconductor package structure according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of a semiconductor package structure according to an embodiment of the present disclosure;
fig. 9 is a flowchart illustrating a method for fabricating a semiconductor package structure according to an embodiment of the present disclosure;
FIG. 10 is a schematic view of a microprotrusion manufacturing process;
FIG. 11 is a top view of a wafer after dicing to form chips;
fig. 12 to fig. 13 are structural diagrams of different process steps of a method for manufacturing a semiconductor package structure according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein, and it will be apparent to those of ordinary skill in the art that the present application is not limited to the specific embodiments disclosed below.
Next, the present application will be described in detail with reference to the drawings, and in the detailed description of the embodiments of the present application, the cross-sectional views illustrating the structure of the device are not enlarged partially according to the general scale for convenience of illustration, and the drawings are only examples, which should not limit the scope of the protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
As described in the background section, it is important for those skilled in the art to provide a semiconductor package structure that can help suppress deformation, warpage, and cracking of a main chip.
At present, in order to reduce the size of the semiconductor package structure and further reduce the space occupied by the semiconductor package structure during assembly, a common technical solution is to suspend the stacked main chips in the same semiconductor package structure. As shown in fig. 1, the conventional semiconductor package structure includes a substrate 60, and a plurality of components and supporting chips 61 located on a surface of the substrate, and further includes a main chip 62 stacked on the substrate, where the main chip 62 is connected to the substrate 60, and the main chip 62 is fixed to a side of the supporting chip 61 facing away from the surface of the substrate 60, that is, the main chip 62 is fixed at a position away from the surface of the substrate 10, so that the semiconductor package structure can extend longitudinally, thereby improving the packaging density of the semiconductor package structure.
Generally, in order to make the supporting chips not occupy the space on the substrate surface for disposing components and devices, so as to ensure the packaging density of the semiconductor package structure, the size of the supporting chips is smaller than that of the main chips, and one main chip corresponds to one supporting chip, so that when the main chips are fixed on the supporting chips, a large suspending area exists on the side surface of the main chip supported by the supporting chips, that is, a large part of the area of the side surface of the main chip supported by the supporting chips is not supported by the supporting chips.
It should be noted that the main chip has a chip pad connected to the internal circuit of the main chip, the substrate has a substrate pad connected to the internal circuit of the substrate, and the chip pad and the substrate pad are connected by a Wire Bonding (WB) process, so that the main chip is connected to the substrate. The process that the chip bonding pad is connected with the substrate bonding pad through the wire bonding comprises the following steps: welding points are respectively formed on the surface of the chip welding pad and the surface of the substrate welding pad, and then the welding points on the surface of the chip welding pad and the surface of the substrate welding pad are connected through welding wires. However, in the process of connecting the die pad and the substrate pad through a wire bonding process, the main chip is subjected to a large stress, so that when a large suspension area exists on the surface of one side of the main chip supported by the supporting chip, the main chip is deformed or bent, and the pad on the surface of the main chip is not connected well with the corresponding welding point. Because the surface of the main chip bonding pad connected with the welding spot is a plane, when the main chip deforms or bends, the condition that the bonding pad on the surface of the main chip is connected with the corresponding welding spot badly can occur, and the work of the semiconductor packaging structure is influenced.
In addition, in the process of connecting the main chip and the substrate, the main chip is sometimes connected with the substrate through a plurality of lead bonding processes, which may cause the main chip to be repeatedly bent and deformed, thereby causing connection fatigue between the main chip bonding pad and a bonding wire connected thereto, which is easily damaged, and affecting the service life and reliability of the semiconductor packaging structure. Meanwhile, as the semiconductor technology is developed, the thickness of the chip is gradually reduced, and the thinnest chip thickness has reached 25 um. Because the pressure that the chip can bear is in direct proportion to the thickness of the chip, when the thickness of the main chip is smaller, the pressure that the chip can bear is also gradually reduced, so that the possibility that the main chip is bent and deformed is also gradually increased in the process that the main chip is connected with the substrate through a wire bonding process, and the reliability of the semiconductor packaging structure is seriously influenced.
In order to solve the above problems, as shown in fig. 2, patent CN100424871C proposes that after a main chip and a supporting chip are disposed on a surface of a substrate and before wire bonding is performed, an adhesive layer made of non-conductor microspheres is added in an overhang region of the main chip to solve the problem of stress bending deformation of the overhang region of the main chip, but in the process of solving the problem, new materials and new processes are added, so as to increase the cost and process complexity of a semiconductor package structure, and there is also a problem that the sizes of the microspheres are difficult to unify, which affects the supporting effect on the overhang region of the main chip.
In addition, the process of forming the known semiconductor packaging structure also includes a plastic packaging process, and the plastic packaging process can generate large stress on the main chip, so that the main chip is bent or deformed, and the reliability of the semiconductor packaging structure is influenced. And before plastic packaging, the main chip is deformed or bent due to stress generated in the lead bonding process, so that the main chip is further deformed or bent in the plastic packaging process, even cracks are generated in the main chip, the main chip is damaged, the normal work of the main chip is influenced, and the normal work of the semiconductor packaging structure is further influenced.
Based on the above research, an embodiment of the present application provides a semiconductor package structure, as shown in fig. 3, the semiconductor package structure includes:
a substrate 10; the substrate is a thin circuit board for carrying a chip in the field of semiconductor packaging, but the substrate is not limited in the application and is determined according to the situation;
the plurality of supporting bodies 20 are positioned on the surface of the substrate 10, and the plurality of supporting bodies 20 comprise a plurality of metal micro-bumps 21 which are sequentially arranged along the side departing from the surface of the substrate 10;
the main chip 30 is connected with the substrate 10, one side of the main chip 30, which faces the surface of the substrate 10, is provided with a plurality of preset supporting positions, and the plurality of supporting bodies 20 are respectively bonded with the plurality of preset supporting positions in a one-to-one correspondence manner, so that the supporting bodies support the main chip 30; the side of the main chip bonded to the support body is provided with an adhesive layer formed by an adhesive, so that the support body is bonded to the main chip; the preset support positions are used for performing mechanical approval on the main chip, and the obtained positions of the main chip needing to be supported are not embodied by the entity part on the main chip;
and the plastic package body 40 is positioned on the surface of the substrate 10, extends towards one side away from the surface of the substrate 10, and covers the surface of the substrate 10, the support body 20 and the main chip 30.
Specifically, in the embodiment of the present application, the semiconductor package structure has a plurality of supporting bodies, the main chip has a plurality of predetermined supporting positions on a side facing the substrate surface, the positions of the plurality of preset supporting positions on the main chip are according to the shape of the main chip, the plurality of support positions are respectively bonded with the plurality of preset support positions in a one-to-one correspondence manner through mechanical analysis, so that the support body can support each position of the main chip to be supported, thereby the support body can realize good support to the main chip, and the plurality of support positions are respectively bonded with the plurality of preset support positions in a one-to-one correspondence manner, thereby avoiding most of the suspended area of the main chip, therefore, the main chip is prevented from bending, deforming and even cracking, and the semiconductor packaging structure has high reliability. Meanwhile, the support body can support each position of the main chip, which needs to be supported, so that the support body can also well support the main chip even under the condition that the thickness of the main chip is thinner, and the influence of the gradual thinning of the chip thickness on the reliability of the semiconductor packaging structure is favorably improved. It should be noted that, depending on the form of the object, it is a common technical means to perform mechanical analysis on each part of the object, and the description thereof is not repeated here.
And the supporting body in the semiconductor packaging structure comprises a plurality of micro-convex bodies which are sequentially arranged along one side departing from the surface of the substrate, the forming process of the micro-convex bodies comprises ball burning, ball pressing and tangent line, the difference with the process of lead bonding is only that after the ball pressing process, the tangent line is carried out, the metal bonding wire is cut off to form the micro-convex bodies, and the metal micro-convex points can be formed by a lead bonding process method. The process parameters of the known wire bonding process can be controlled to control the height and width of a product, so that the height and width of the micro-convex body can be controlled through the process parameters, the height and width of the supporting body can be controlled according to the shape and size of the main chip and the practical application environment, and the supporting body can be guaranteed to support the main chip well. It should be noted that, in order to reduce the influence of the wire tail left after the wire cutting on the stacking of the plurality of metal micro bumps, in the embodiment of the present application, a smooth micro bump (smooth bump) technology is used, which is helpful for reducing the wire tail left after the wire cutting, making the wire tail left smooth and uniform, and is helpful for stacking the plurality of metal micro bumps to form a supporting body.
In addition, it is known that the conventional semiconductor package structure includes supporting chips, and the main chips are located on the supporting chips and supported by the supporting chips, and since the width of the supporting chips is difficult to be small and difficult to achieve a large aspect ratio, in order to ensure the packaging density of the conventional semiconductor package structure, one main chip corresponds to one supporting chip. And the main chip among the semiconductor package structure that this application embodiment provided is supported by the supporter, the supporter includes a plurality of little bumps, little bump is the little bump of metal, the width of little convex body can be done for a short time, makes great aspect ratio can be accomplished to the supporter, and then makes the supporter can be right when the main chip supports, can also reduce the supporter as far as and be in the space that substrate surface occupied guarantees semiconductor package structure's packaging density.
Meanwhile, the semiconductor packaging structure comprises a plastic packaging body, and the plastic packaging body covers the substrate surface, the supporting body and the main chip so as to improve the mechanical strength of the semiconductor packaging structure and prevent water vapor in the external environment from entering the inside of the semiconductor packaging structure. The semiconductor packaging structure is known to generate large stress to the main chip in the plastic packaging process, so that the main chip is bent or deformed or even cracked, and the support body in the semiconductor packaging structure can well support the main chip, so that the main chip is prevented from being bent, deformed or even cracked in the plastic packaging process, and the semiconductor packaging structure has high reliability.
It should be noted that, in an embodiment of the present application, the main chip may be completely supported by the plurality of supporting bodies, so as to reduce the space of the semiconductor package structure occupied by supporting the main chip as much as possible, increase the available space of the semiconductor package structure, and improve the packaging density of the semiconductor package structure as much as possible; in another embodiment of the present application, as shown in fig. 4, the semiconductor package structure may also include a supporting chip 18, and the supporting chip 18 and the supporting body 20 jointly support the main chip 30, as the case may be. It should be noted that, in the embodiments of the present application, specific numbers of the plurality of supporting bodies are not limited, and are determined as the case may be.
Optionally, in an embodiment of this application, as shown in fig. 5, the value range of the height h of the metal micro-bump is 20 um-50 um, the value range of the width d of the metal micro-bump is 30 um-100 um, wherein, the width of the metal micro-bump is the radial length of the metal micro-bump along the first direction, the height of the metal micro-bump is the radial length of the metal micro-bump along the second direction, the first direction is parallel to the substrate surface, the second direction with the first direction is perpendicular. However, this is not limited in this embodiment, and in other embodiments of the present application, the value range of the height of the metal micro bump and the value range of the width of the metal micro bump may also be other values, as the case may be. It should be noted that, in an embodiment of the present application, the height and the width of the metal micro bump may be adjusted according to a distance between a chip to be supported and a surface of a substrate, where the widths and the heights of the plurality of metal micro bumps in different supporting bodies may be consistent or inconsistent, and the widths and the heights of the metal micro bumps in the same supporting body may be consistent or inconsistent, which is not limited in this application embodiment, and in other embodiments of the present application, the widths and the heights of the plurality of metal micro bumps may also be inconsistent, depending on a situation.
It should be noted that, in order to increase the packing density of the semiconductor package structure, the stacked main chips are usually disposed in the package structure. Therefore, on the basis of the above embodiments, in an embodiment of the present application, as shown in fig. 6, the main chip 30 includes a plurality of sub-chips 32 sequentially arranged along a side away from the surface of the substrate 10, at least one sub-chip 32 of the plurality of sub-chips 32 except a first sub-chip 33 has an overhang region 34, a part of the plurality of preset supporting bits is located on the first sub-chip 33, and another part of the plurality of preset supporting bits is located in the overhang region 34; one part of the plurality of supporting bodies 20 is adhered to a preset supporting position on the first sub-chip 33, and the other part is adhered to a preset supporting position in the suspending area 34, so that when the main chip comprises a plurality of sub-chips, the main chip is supported, and the main chip is prevented from being bent, deformed or even deformed. The first sub-chip is a sub-chip closest to the substrate surface among the plurality of sub-chips, and the suspension area is an area where the other sub-chips except the first sub-chip are not shielded from one side of the substrate surface, that is, the suspension area is an area where the sub-chips except the first sub-chip are directly opposite to the substrate surface. It should be further noted that the number of the plurality of preset supporting positions on the first sub-chip and the position distribution on the first sub-chip are obtained through mechanical analysis, and the number of the plurality of preset supporting positions on the suspension area and the position distribution on the suspension area are also obtained through mechanical analysis. Meanwhile, when the main chip comprises a plurality of sub-chips, one side of each sub-chip, which faces the surface of the substrate, is provided with an adhesive layer, so that the sub-chips are fixedly adhered to each other through the adhesive layers, and internal circuits of the sub-chips are sequentially connected through a wire bonding process, so that the sub-chips are sequentially connected.
On the basis of the above embodiments, in an embodiment of the present application, in order to fix the supporting body on the surface of the substrate and connect the main chip and the substrate, as shown in fig. 6, the semiconductor package structure further includes: a first pad 11 and a second pad 12 on the surface of the substrate 10, wherein the first pad 11 is not connected to the internal circuit of the substrate 10, the second pad 12 is connected to the internal circuit of the substrate 10, and the support 20 is fixed to a side of the first pad 11 facing away from the surface of the substrate 10, so as to fix the support 20 to the surface of the substrate 10, so that the support 20 supports the main chip 30; the main chip 30 deviates from the substrate 10, a third bonding pad 13 is arranged on one side of the surface, the third bonding pad 13 is connected with an internal circuit of the main chip 30, the third bonding pad 13 is connected with the second bonding pad 12 through lead bonding, and the second bonding pad 12 is known to be connected with the internal circuit of the substrate 10, so that the main chip can be connected with the substrate, and the normal work of the semiconductor packaging structure is guaranteed.
And, discover when the number of the little bump of metal is not more than 5 according to the experiment, the little bump of metal can form stable supporter, just first pad also can be right the supporter carries out the outrigger, and is known the value scope of the little bump height of metal is 20um ~ 50um, the value scope of the little bump width of metal is 30um ~ 100um, thereby makes the height of supporter can reach 250um, and the thickness of general support chip is about 100um, promptly the height of supporter is greater than the thickness of supporting the chip, makes semiconductor package structure's vertical extension height is higher, makes semiconductor package structure's packaging space is bigger, helps improving semiconductor package structure's packaging density.
In addition, a third bonding pad is arranged on one side, away from the surface of the substrate, of the main chip, a second bonding pad is arranged on the surface of the substrate, and the third bonding pad is connected with the second bonding pad through wire bonding so that the main chip is connected with the substrate through wire bonding. Meanwhile, even if the manufacturing process of the semiconductor packaging structure does not include a wire bonding process, the wire bonding process is a process method frequently used in the semiconductor manufacturing process, and only the existing wire bonding process is used for manufacturing the metal micro-bumps, so that the difficulty of the manufacturing process is not increased. It should be noted that, the formation of the metal micro-bump and the connection between the main chip and the substrate may be completed in the same process step or different process steps, which is not limited in this application and is determined as the case may be.
On the basis of the above embodiments, in an embodiment of the present application, as shown in fig. 7, the semiconductor package structure further includes: the semiconductor package structure comprises a control chip 50 and a fourth bonding pad 14, wherein the control chip 50 is located on the surface of the substrate 10, the fifth bonding pad 15 is arranged on one side, away from the surface of the substrate 10, of the control chip 50, the fourth bonding pad 14 is connected with the fifth bonding pad 15, the fourth bonding pad 14 is connected with an internal circuit of the substrate 10, the fifth bonding pad 15 is connected with an internal circuit of the control chip 50, so that the control chip 50 is connected with the substrate, and the work of the semiconductor package structure is controlled through the control chip 50. The control chip is fixed to the surface of the substrate by an adhesive layer made of an adhesive.
Optionally, in an embodiment of the present application, the first pad, the second pad, the third pad, the fourth pad, and the fifth pad are made of the same material, and are made of one of gold, silver, copper, and aluminum. However, this is not limited in this embodiment of the present application, and in other embodiments of the present application, the material of the first pad, the second pad, the third pad, the fourth pad, and the fifth pad may also be other materials, as the case may be.
On the basis of the above embodiments, in an embodiment of the present application, as shown in fig. 8, a side of the substrate 10 away from the substrate main chip 30 is provided with a plurality of solder balls 16, and the solder balls 16 are I/O interfaces of the semiconductor package structure, so that the semiconductor package structure can be connected to an external circuit to perform corresponding operations.
On the basis of the above embodiments, in an embodiment of the present application, as shown in fig. 8, the surface of the substrate 10 further has a plurality of passive components 17, such as inductors, resistors, inductors, and the like, so that the semiconductor package structure can perform corresponding functions. The plurality of passive elements are fixed to the surface of the substrate by an adhesive layer made of an adhesive.
Correspondingly, the present application also provides a method for manufacturing a semiconductor package structure, as shown in fig. 9, the method includes:
s1: providing a substrate;
s2: forming a plurality of supporting bodies, fixing the supporting bodies on the surface of the substrate, wherein the supporting bodies comprise a plurality of metal micro-bumps which are sequentially arranged along one side departing from the surface of the substrate; as shown in fig. 10, the process of forming the metal micro-bump includes: 1. the method comprises the following steps of (1) burning a ball by a cleaver and moving downwards, 2, continuously moving the cleaver downwards to form a metal micro-bump main body on the surface of a substrate, 3, moving the cleaver upwards to reach a Separation height, 4, moving the cleaver downwards to finish a tangent line, 5, moving the cleaver upwards to finish the tangent line to form a metal micro-bump, and repeating the process to form a plurality of metal micro-bumps on the surface of the substrate. It should be noted that, the process method used for forming the metal micro-bump is a process method commonly used in the semiconductor field, and details of the process method are not described too much here;
s3: providing a main chip, connecting the main chip with the substrate, wherein one side of the main chip, which faces the surface of the substrate, is provided with a plurality of preset supporting positions, and bonding the plurality of supporting bodies and the plurality of preset supporting positions in a one-to-one correspondence manner so that the supporting bodies support the main chip; as shown in fig. 11, the process of forming the main chip includes: providing a wafer 100, grinding the wafer 100 to a specified thickness, and then dividing the wafer 100 into a plurality of crystal grains to form main chips 30;
s4: and forming a plastic package body, wherein the plastic package body is positioned on the surface of the substrate, extends to one side away from the surface of the substrate and covers the surface of the substrate, the support body and the main chip.
Specifically, in the embodiment of the present application, the manufacturing method includes forming a plurality of supporting bodies fixed on the substrate surface, where one side of the main chip facing the substrate surface has a plurality of preset supporting positions, where the positions of the preset supporting positions on the main chip are obtained through mechanical analysis according to the shape of the main chip, and bonding the plurality of supporting positions with the plurality of preset supporting positions in a one-to-one correspondence manner, respectively, so that the supporting bodies can support the positions of the main chip, which need to be supported, and further the supporting bodies can realize good support of the main chip, and the plurality of supporting positions are bonded with the plurality of preset supporting positions in a one-to-one correspondence manner, so that a majority of suspended areas of the main chip can be avoided, and the main chip is prevented from being bent, deformed, and even cracked, the semiconductor packaging structure manufactured by the manufacturing method has higher reliability. Meanwhile, the support body can support each position of the main chip, which needs to be supported, so that the support body can also well support the main chip even under the condition that the thickness of the main chip is thinner, and the influence of the gradual thinning of the chip thickness on the reliability of the semiconductor packaging structure is favorably improved.
And the supporting body comprises a plurality of micro-convex bodies which are sequentially arranged along one side departing from the surface of the substrate, the forming process of the micro-convex bodies comprises ball burning, ball pressing and cutting, the difference of the process with the lead bonding is that the cutting is carried out after the ball pressing process, and the metal bonding wire is cut off to form the micro-convex bodies, so that the metal micro-convex points can be formed by a lead bonding process. The process parameters of the known wire bonding process can be controlled to control the height and width of a product, so that the height and width of the micro-convex body can be controlled through the process parameters, the height and width of the supporting body can be controlled according to the shape and size of the main chip and the practical application environment, and the supporting body can be guaranteed to support the main chip well.
In addition, it is known that the conventional semiconductor package structure includes supporting chips, and the main chips are located on the supporting chips and supported by the supporting chips, and since the width of the supporting chips is difficult to be small and difficult to achieve a large aspect ratio, in order to ensure the packaging density of the conventional semiconductor package structure, one main chip corresponds to one supporting chip. The main chip in the semiconductor packaging structure manufactured by the manufacturing method provided by the embodiment of the application is supported by the supporting body, the supporting body comprises a plurality of micro-convex bodies, the micro-convex bodies are metal micro-convex bodies, the width of each micro-convex body can be reduced, so that the supporting body can achieve a larger height-width ratio, and further the supporting body can support the main chip and simultaneously reduce the space occupied by the surface of the substrate as much as possible, and the packaging density of the semiconductor packaging structure is ensured.
Meanwhile, the manufacturing method comprises the step of forming a plastic package body, wherein the plastic package body covers the surface of the substrate, the supporting body and the main chip so as to improve the mechanical strength of the semiconductor packaging structure and prevent water vapor in the external environment from entering the inside of the semiconductor packaging structure. The semiconductor packaging structure is known to generate large stress to the main chip in the plastic packaging process, so that the main chip is bent or deformed or even cracked, and the support body in the semiconductor packaging structure can well support the main chip, so that the main chip is prevented from being bent, deformed or even cracked in the plastic packaging process, and the semiconductor packaging structure has high reliability.
It should be noted that, in an embodiment of the present application, the main chip may completely pass through the plurality of supporting bodies to support, so as to reduce as much as possible the space of the semiconductor package structure occupied by the main chip to support, so as to increase the available space of the semiconductor package structure, and improve as much as possible the packaging density of the semiconductor package structure. When the semiconductor packaging structure comprises a supporting chip, the manufacturing method further comprises the following steps: as shown in fig. 12, before the main chip is supported, a supporting chip 18 is provided, and the supporting chip 18 is disposed on the surface of the substrate 10, so that the supporting chip can support the main chip.
It should be noted that, in order to increase the packing density of the semiconductor package structure, the stacked main chips are usually disposed in the package structure. Therefore, on the basis of the above embodiments, in an embodiment of the present application, as shown in fig. 6, the main chip 30 includes a plurality of sub-chips 32 sequentially arranged along a side away from the surface of the substrate 10, at least one sub-chip 32 of the plurality of sub-chips 32 except a first sub-chip 33 has an overhang region 34, a part of the plurality of preset support locations is located on the first sub-chip 33, and another part of the plurality of preset support locations is located in the overhang region 34; bonding the plurality of support bodies and the plurality of preset support positions in a one-to-one correspondence manner comprises: and adhering one part of the plurality of supporting bodies 20 to a preset supporting phase on the first sub-chip 33, and adhering the other part of the plurality of supporting bodies to a preset supporting phase in the suspending area 34, so as to support the main chip when the main chip comprises a plurality of sub-chips, and inhibit the main chip from bending, deforming or even deforming. The first sub-chip is a sub-chip closest to the substrate surface among the plurality of sub-chips, and the suspension area is an area where the other sub-chips except the first sub-chip are not shielded towards one side of the substrate surface, that is, the suspension area is an area where the sub-chips except the first sub-chip are directly opposite to the substrate surface and is not shielded by the first sub-chip but other sub-chips. It should be further noted that the number of the plurality of preset supporting positions on the first sub-chip and the position distribution on the first sub-chip are obtained through mechanical analysis, and the number of the plurality of preset supporting positions on the suspension area and the position distribution on the suspension area are also obtained through mechanical analysis. Meanwhile, when the main chip comprises a plurality of sub-chips, one side of each sub-chip, which faces the surface of the substrate, is provided with an adhesive layer, so that the sub-chips are fixedly adhered to each other through the adhesive layers, and internal circuits of the sub-chips are sequentially connected through a wire bonding process, so that the sub-chips are sequentially connected.
On the basis of the foregoing embodiments, in an embodiment of the present application, as shown in fig. 6, the surface of the substrate 10 has a first pad 11 and a second pad 12, where the first pad 11 is not connected to the internal circuit of the substrate 10, the second pad 12 is connected to the internal circuit of the substrate 10, the side of the main chip 30 facing away from the surface of the substrate 10 has a third pad 13, and the third pad 13 is connected to the internal circuit of the main chip 30; fixing the support body on the surface of the substrate, and connecting the main chip with the substrate comprises: fixing the support body 20 to the side of the first pad 11 facing away from the surface of the substrate 10 to fix the support body 20 to the surface of the substrate 10, so that the support body 20 supports the main chip 30; and connecting the third bonding pad 13 with the second bonding pad 12 through a bonding wire, wherein the second bonding pad 12 is known to be connected with an internal circuit of the substrate 10, so that the main chip can be connected with the substrate, and the normal operation of the semiconductor packaging structure is ensured.
And, discover when the number of the little bump of metal is not more than 5 according to the experiment, the little bump of metal can form stable supporter, just first pad also can be right the supporter carries out the outrigger, and is known the value scope of the little bump height of metal is 20um ~ 50um, the value scope of the little bump width of metal is 30um ~ 100um, thereby makes the height of supporter can reach 250um, and the thickness of general support chip is about 100um, promptly the height of supporter is greater than the thickness of supporting the chip, makes semiconductor package structure's vertical extension height is higher, makes semiconductor package structure's packaging space is bigger, helps improving semiconductor package structure's packaging density.
In addition, the surface of the main chip is provided with a third bonding pad, the surface of the substrate is provided with a second bonding pad, the third bonding pad is connected with the second bonding pad through a bonding wire, so that the main chip is connected with the substrate through wire bonding. Meanwhile, even if the manufacturing process of the semiconductor packaging structure does not include a wire bonding process, the wire bonding process is a process method frequently used in the semiconductor manufacturing process, and only the existing wire bonding process is used for manufacturing the metal micro-bumps, so that the difficulty of the manufacturing process is not increased.
On the basis of the above embodiments, in an embodiment of the present application, as shown in fig. 7, the surface of the substrate 10 has fourth pads 14, and the fourth pads 14 are connected to the internal circuit of the substrate 10; the manufacturing method further comprises the following steps:
s5: as shown in fig. 13, providing a control chip 50, wherein a side of the control chip 50 facing away from the surface of the substrate 10 has a fifth pad 15, and the fifth pad 15 is connected to an internal circuit of the control chip 50;
s6: arranging the control chip 50 on the surface of the substrate 10;
s7: continuing with fig. 7, the fourth pads 14 are connected to the fifth pads 15 to connect the control chip 50 to the substrate 10.
Specifically, in this embodiment of the application, the fourth pad is connected to the substrate internal circuit, the fifth pad is connected to the control chip internal circuit, and the fourth pad is connected to the fifth pad, so that the control chip is connected to the substrate, and the semiconductor package structure is controlled by the control chip to operate.
On the basis of the above embodiment, in an embodiment of the present application, the manufacturing method further includes:
s8: as shown in fig. 8, a plurality of solder balls 16 are formed on a side of the substrate 10 away from the surface of the substrate 10, where the solder balls 16 are I/O interfaces of the semiconductor package structure, so that the semiconductor package structure can be connected to an external circuit to perform corresponding operations;
s9: as shown in fig. 8, a plurality of passive components 17, such as inductors, resistors, inductors, etc., are formed on the surface of the substrate 10, so that the semiconductor package structure can perform corresponding functions.
In summary, the present application provides a semiconductor package structure and a method for manufacturing the same, the semiconductor package structure includes: the chip comprises a substrate, a plurality of supporting bodies, a main chip and a plastic package body; the plurality of support bodies are bonded with the plurality of preset support positions on the main chip in a one-to-one correspondence manner, it needs to be noted that the plurality of preset support positions on one side, facing the substrate surface, of the main chip are obtained through mechanical analysis according to the structure of the main chip, so that the plurality of support bodies can well support the main chip, most of suspended areas of the main chip are avoided, the main chip can be prevented from deforming, bending and even cracking, and the reliability of the semiconductor packaging structure is improved. Moreover, the height and the width of the plurality of metal micro-bumps can be controlled, so that the height and the width of the support body can be controlled according to the structure of a main chip and actual requirements, and the support of the support body on the main chip is ensured. Meanwhile, the width of the metal micro-bump is smaller than that of a supporting chip in the conventional semiconductor packaging structure, so that the supporting body can have a larger height-width ratio relative to the supporting chip, and the packaging density of the semiconductor packaging structure is improved.
In addition, the support body can also support the main chip in the plastic package process, so that the main chip is prevented from being bent, deformed and even cracked in the plastic package process, and the reliability of the semiconductor packaging structure is improved.
All parts in the specification are described in a mode of combining parallel and progressive, each part is mainly described to be different from other parts, and the same and similar parts among all parts can be referred to each other.
In the above description of the disclosed embodiments, features described in various embodiments in this specification can be substituted for or combined with each other to enable those skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A semiconductor package structure, comprising:
a substrate;
the plurality of supporting bodies are positioned on the surface of the substrate and comprise a plurality of metal micro-bumps which are sequentially arranged along one side departing from the surface of the substrate;
the main chip is connected with the substrate, one side of the main chip, facing the surface of the substrate, is provided with a plurality of preset supporting positions, and the plurality of supporting bodies are respectively bonded with the plurality of preset supporting positions in a one-to-one correspondence manner, so that the supporting bodies support the main chip;
and the plastic package body is positioned on the surface of the substrate, extends to one side back to the surface of the substrate and covers the surface of the substrate, the support body and the main chip.
2. The semiconductor package structure of claim 1, wherein the height of the metal microbumps ranges from 20um to 50um, and the width of the metal microbumps ranges from 30um to 100 um;
the width of the metal micro-bump is the radial length of the metal micro-bump along a first direction, the height of the metal micro-bump is the radial length of the metal micro-bump along a second direction, the first direction is parallel to the surface of the substrate, and the second direction is perpendicular to the first direction.
3. The semiconductor package structure according to claim 1, wherein the main chip comprises a plurality of sub-chips sequentially arranged along a side away from the substrate surface, at least one of the sub-chips except a first sub-chip has a suspending area, and a part of the plurality of preset supporting bits is located in the first sub-chip and another part is located in the suspending area;
one part of the plurality of supporting bodies is adhered to a preset supporting phase positioned on the first sub-chip, and the other part of the plurality of supporting bodies is adhered to a preset supporting phase positioned in the suspension area;
the first sub-chip is the sub-chip closest to the substrate surface among the plurality of sub-chips, and the suspension area is an area where the other sub-chips except the first sub-chip are not shielded from one side of the substrate surface.
4. The semiconductor package structure of claim 1, further comprising: the first bonding pad and the second bonding pad are positioned on the surface of the substrate, the first bonding pad is not connected with the internal circuit of the substrate, the second bonding pad is connected with the internal circuit of the substrate, and the support body is fixed on one side of the first bonding pad, which is far away from the surface of the substrate;
and the third bonding pad is positioned on one side of the main chip, which deviates from the surface of the substrate, is connected with the internal circuit of the main chip, and is connected with the second bonding pad.
5. The semiconductor package structure of claim 4, further comprising: the control chip and the fourth bonding pad are positioned on the surface of the substrate, a fifth bonding pad is arranged on one side, away from the surface of the substrate, of the control chip, and the fourth bonding pad is connected with the fifth bonding pad;
the fourth bonding pad is connected with the internal circuit of the substrate, and the fifth bonding pad is connected with the internal circuit of the control chip.
6. The semiconductor package structure according to claim 5, wherein the first bonding pad, the second bonding pad, the third bonding pad, the fourth bonding pad and the fifth bonding pad are made of the same material and are made of one of gold, silver, copper and aluminum.
7. A method for manufacturing a semiconductor packaging structure is characterized by comprising the following steps:
providing a substrate;
forming a plurality of supporting bodies, fixing the supporting bodies on the surface of the substrate, wherein the supporting bodies comprise a plurality of metal micro-bumps which are sequentially arranged along one side departing from the surface of the substrate;
providing a main chip, connecting the main chip with the substrate, wherein one side of the main chip, which faces the surface of the substrate, is provided with a plurality of preset supporting positions, and bonding the plurality of supporting bodies and the plurality of preset supporting positions in a one-to-one correspondence manner so that the supporting bodies support the main chip;
and forming a plastic package body, wherein the plastic package body is positioned on the surface of the substrate, extends to one side away from the surface of the substrate and covers the surface of the substrate, the support body and the main chip.
8. The manufacturing method of claim 7, wherein the main chip comprises a plurality of sub-chips sequentially arranged along a side away from the substrate surface, at least one of the sub-chips except a first sub-chip has a suspending area, and a part of the plurality of preset supporting positions is located in the first sub-chip, and another part of the plurality of preset supporting positions is located in the suspending area; bonding the plurality of support bodies and the plurality of preset support positions in a one-to-one correspondence manner comprises:
bonding a part of the plurality of support bodies with a preset support position on the first sub-chip;
bonding the other part of the support body with a preset support position positioned in the suspension area;
the first sub-chip is the sub-chip closest to the substrate surface among the plurality of sub-chips, and the suspension area is an area where the other sub-chips except the first sub-chip are not shielded from one side of the substrate surface.
9. The method of manufacturing according to claim 7, wherein the substrate surface has a first pad and a second pad, wherein the first pad is not connected to the substrate internal wiring, and the second pad is connected to the substrate internal wiring; a third bonding pad is arranged on one side of the main chip, which is far away from the surface of the substrate, and the third bonding pad is connected with an internal circuit of the main chip; fixing the support body on the surface of the substrate, and connecting the main chip with the substrate comprises:
fixing the support body on one side, away from the substrate surface, of the first bonding pad so as to fix the support body on the substrate surface;
and connecting the second bonding pad with the third bonding pad so as to connect the main chip with the substrate.
10. The manufacturing method according to claim 8, wherein the substrate surface has a fourth bonding pad connected to the substrate internal circuit; the manufacturing method also comprises the following steps:
providing a control chip, wherein a fifth bonding pad is arranged on one side of the control chip, which is far away from the surface of the substrate, and the fifth bonding pad is connected with an internal circuit of the control chip;
arranging the control chip on the surface of the substrate;
and connecting the fourth bonding pad with the fifth bonding pad so as to connect the control chip with the substrate.
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