CN114550809B

CN114550809B - Multi-storage card testing method, device, computer equipment and storage medium

Info

Publication number: CN114550809B
Application number: CN202210068159.1A
Authority: CN
Inventors: 赖振楠; 王嗣钧
Original assignee: Hosin Global Electronics Co Ltd
Current assignee: Hosin Global Electronics Co Ltd
Priority date: 2022-01-20
Filing date: 2022-01-20
Publication date: 2025-01-14
Anticipated expiration: 2042-01-20
Also published as: CN114550809A

Abstract

The application belongs to the technical field of storage, and relates to a testing method, a testing device, computer equipment and a storage medium of a multi-storage card, wherein the method comprises the steps of obtaining a writing command for writing data and the serial numbers of the multi-storage card into the multi-storage card, wherein the writing command carries the data and the serial numbers; reading the data from each two different numbered multiple memory cards, putting the read data into a comparison circuit for exclusive OR operation, and judging whether the multiple memory cards are normal according to the exclusive OR operation result. By numbering the multiple memory cards, the application writes data into the multiple memory cards at the same time, does not need to rely on manpower, can automatically execute the test of the memory cards, saves the cost, can improve the test efficiency, has reliable test and easy realization, and can be widely applied to the test of the memory cards.

Description

Method and device for testing multiple memory cards, computer equipment and storage medium

Technical Field

The present application relates to the field of storage technologies, and in particular, to a method and apparatus for testing multiple memory cards, a computer device, and a storage medium.

Background

With the development of information processing technology, the demand for storage devices has increased significantly. Small memory devices, such as memory cards, are widely used for their convenience in carrying, high data storage capacity, and ease of access. Based on the increasing demand of memory cards, the importance of the memory card testing process is relatively improved before mass production of the memory cards, and the efficiency and compatibility of the memory cards are further ensured. Therefore, low cost and high performance memory card testing is an important issue for system manufacturers and designers.

Conventionally, when testing a memory card, a tester is required to process the test manually and gradually to ensure the performance of the memory card. For example, each memory card may be manually inserted or removed by a tester to perform the test. In the test process, various test devices are required to ensure the performance and compatibility of the memory card. It can be seen that the traditionally used memory card test procedure is time consuming and costly. The test principle of the memory card in the prior art is that the same data is written into a plurality of memory cards, then the data is read out, and the coincidence degree of the read-out data and the written-in data is verified, so that the operation of the memory card is performed.

The test operation has the characteristics that firstly, the data volume is relatively large, for example, when the storage device to be tested is a storage card, if the capacity of the storage card is 256GB, the test data is 256GB, if the storage device to be tested is a hard disk, if the capacity of the hard disk is 2T, the test data is 2T, and secondly, the data to be tested is written into a plurality of storage devices to be tested from a host computer. Writing-reading-data comparison, re-writing-erasing block-reading-data comparison. Typically, such a test procedure is repeated several times to test the stability of the stored data of the storage device. The test procedure is seen to be very lengthy and inefficient.

Disclosure of Invention

The embodiment of the application aims to provide a method, a device, computer equipment and a storage medium for testing multiple memory cards, which are used for solving the problems of very long testing process and low efficiency of the multiple memory cards in the prior art.

In order to solve the technical problems, the application provides a testing method of a multi-memory card, which adopts the following technical scheme that the method comprises the following steps:

acquiring a write command for writing data and the serial numbers of the multiple memory cards into the multiple memory cards, wherein the write command comprises the data and the serial numbers;

analyzing the writing command to obtain the data and the number, and writing the data into a multi-memory card according to the number;

And reading the data from the multi-memory cards with different numbers, storing the read data into a comparison circuit for exclusive-OR operation, and judging whether the two multi-memory cards with different numbers are normal or not according to the exclusive-OR operation result.

Further, before the step of obtaining a write command for writing the data and the serial number of the multiple memory cards into the multiple memory cards, the write command carries the data and the serial number, the method further includes:

Rules for write commands are set.

Further, the step of analyzing the writing command to obtain the data and the number, and writing the data into the multi-memory card according to the number specifically includes:

analyzing the writing command to obtain the data and the number;

Caching the obtained data into a cache region;

and writing the data in the buffer area into the multi-memory card according to the number.

Further, the step of reading the data from each two different numbered multiple memory cards, placing the read data into a comparison circuit to perform exclusive-or operation, and judging whether the multiple memory cards are normal according to the exclusive-or operation result specifically includes:

Grouping every two according to the serial numbers of the multiple memory cards;

reading the data from every two multi-memory cards with different numbers, and putting the read data into a comparison circuit for exclusive OR operation;

if the exclusive or operation result is 0, judging that the two multi-memory cards with different numbers are normal, and if the exclusive or operation result is 1, judging that one of the two multi-memory cards with different numbers is abnormal;

identifying the group of the abnormal multi-memory cards, and performing exclusive OR operation on each multi-memory card in the group of the abnormal multi-memory cards and the detected normal multi-memory card until the normal and abnormal conditions of all the multi-memory cards are detected.

Further, the rule for setting the write command includes:

the first byte of the set write command represents the number of the multi-memory card.

Further, after the step of reading the data from each two different numbered multiple memory cards, placing the read data into a comparison circuit to perform exclusive-or operation, and judging whether the multiple memory cards are normal according to the exclusive-or operation result, the method further comprises:

And displaying the abnormal multi-memory card numbers.

In order to solve the technical problems, the application also provides a testing device for multiple memory cards, which adopts the following technical scheme that:

The system comprises an acquisition module, a storage module and a storage module, wherein the acquisition module is used for acquiring a write-in command for writing data and the serial numbers of the multiple storage cards into the multiple storage cards, and the write-in command carries the data and the serial numbers;

The writing module is used for analyzing the writing command, obtaining the data and the number, and writing the data into the multi-memory card according to the number;

and the judging module is used for reading the data from each two multi-memory cards with different numbers, putting the read data into the comparison circuit for exclusive-or operation, and judging whether the multi-memory cards are normal or not according to the exclusive-or operation result.

Further, the writing module includes:

The analysis module is used for analyzing the writing command to obtain the data and the number;

The buffer module is used for buffering the data into a buffer area SRAM;

and the output module is used for writing the data into the multi-memory card by the buffer area SRAM according to the number.

In order to solve the technical problem, the application also provides a computer device, which adopts the technical scheme that the computer device comprises a memory and a processor, wherein the memory stores computer readable instructions, and the processor realizes the steps of the multi-memory card testing method when executing the computer readable instructions.

In order to solve the technical problem, the application also provides a computer readable storage medium, which adopts the technical scheme that the computer readable storage medium stores computer readable instructions, and the computer readable instructions realize the steps of the multi-memory card testing method when being executed by a processor.

Compared with the prior art, the application has the advantages that the data is written into a plurality of memory cards simultaneously by numbering the memory cards, the test of the memory cards can be automatically executed without relying on manpower, the cost is saved, the test efficiency can be improved, the test is reliable and easy to realize, and the application can be widely applied to the test of the memory cards.

Drawings

In order to more clearly illustrate the solution of the present application, a brief description will be given below of the drawings required for the description of the embodiments of the present application, it being apparent that the drawings in the following description are some embodiments of the present application, and that other drawings may be obtained from these drawings without the exercise of inventive effort for a person of ordinary skill in the art.

FIG. 1 is an exemplary system architecture diagram in which the present application may be applied;

FIG. 2 is a flow chart of one embodiment of a method of testing multiple memory cards of the present application;

FIG. 3 is a schematic diagram of a test of multiple memory cards in the prior art;

FIG. 4 is a timing diagram of test data transmission for multiple memory cards in the prior art;

FIG. 5 is a timing diagram of test data transmission for multiple memory cards of the present application;

FIG. 6 is a schematic diagram of one embodiment of the present application for writing data to multiple memory cards simultaneously;

FIG. 7 is a schematic diagram of another embodiment of the present application in which data is written to multiple memory cards simultaneously;

FIG. 8 is an eight bit exclusive OR circuit diagram of the present application;

FIG. 9 is a logic circuit diagram of the present application;

FIG. 10 is a schematic diagram of an embodiment of a multi-memory card test apparatus of the present application;

FIG. 11 is a schematic diagram of one embodiment of the write module of FIG. 10;

FIG. 12 is a schematic diagram of the architecture of one embodiment of a computer device of the present application.

In the figure, A-NOR gate, B-NAND gate, C-NOR gate.

Detailed Description

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs, the terms used in the description herein are used for the purpose of describing particular embodiments only and are not intended to limit the application, and the terms "comprising" and "having" and any variations thereof in the description of the application and the claims and the above description of the drawings are intended to cover non-exclusive inclusions. The terms first, second and the like in the description and in the claims or in the above-described figures, are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

In order to make the person skilled in the art better understand the solution of the present application, the technical solution of the embodiment of the present application will be clearly and completely described below with reference to the accompanying drawings.

As shown in fig. 1, the system architecture 100 may include a first terminal device 101, a second terminal device 102, a third terminal device 103, a network 104, and a server 105. The network 104 is a medium used to provide a communication link between the first terminal device 101, the second terminal device 102, the third terminal device 103, and the server 105. The network 104 may include various connection types, such as wired, wireless communication links, or fiber optic cables, among others.

The user may interact with the server 105 via the network 104 using the first terminal device 101, the second terminal device 102, the third terminal device 103, to receive or send messages etc. Various communication client applications, such as a web browser application, a shopping class application, a search class application, an instant messaging tool, a mailbox client, social platform software, etc., may be installed on the first terminal device 101, the second terminal device 102, and the third terminal device 103.

The first terminal device 101, the second terminal device 102, and the third terminal device 103 may be various electronic devices having a display screen and supporting web browsing, including but not limited to a smart phone, a tablet computer, an electronic book reader, an MP3 player (Moving Picture E multi-memory card test pertsGroup AudioLayer III, moving Picture expert compression standard audio plane 3), an MP4 (Moving PictureE multi-memory card test perts Group Audio Layer IV, moving Picture expert compression standard audio plane 4) player, a laptop and desktop computer, and the like.

The server 105 may be a server providing various services, such as a background server providing support for pages displayed on the first terminal device 101, the second terminal device 102, and the third terminal device 103.

It should be noted that, the method for testing multiple memory cards provided in the embodiment of the present application is generally executed by a server/terminal device, and accordingly, the device for testing multiple memory cards is generally disposed in the server/terminal device.

It should be understood that the number of terminal devices, networks and servers in fig. 1 is merely illustrative. There may be any number of terminal devices, networks, and servers, as desired for implementation.

Example 1

With continued reference to FIG. 2, a flow chart of one embodiment of a method of testing multiple memory cards of the present application is shown. The testing method of the multi-memory card comprises the following steps:

Step S201, a write command for writing data and a number of a multi-memory card into the multi-memory card is acquired, wherein the write command includes the data and the number.

Fig. 3 is a schematic diagram of a test of multiple memory cards in the prior art. As shown in fig. 3, in the prior art, a test system is generally composed of a terminal, a USB hub, and a plurality of memory cards. One end of the USB hub is a USB interface, and the other end of the USB hub can be a plurality of interfaces. The plurality of interfaces may be identical or different. The plurality of interfaces may include a SATA interface, a USB interface, a Type-C interface, and the like. And connecting the multiple memory cards through interfaces such as an SATA interface, a USB interface, a Type-C interface and the like. In the test process, a tester is required to manually insert or remove each memory card such as the multi-memory card 1, the multi-memory card 2, the multi-memory card 3, and the multi-memory card 4 to perform the test. It can be seen that the test is time consuming and laborious.

Fig. 4 is a timing diagram of test data transmission of a multi-memory card in the prior art. As shown in fig. 4, the same data is written from the terminal to a plurality of memory cards, the data is composed of W1, W2, W3, W4, the data W1 is written to the card 1 at time T1, the data W2 is written to the card 1 at time T2, the data W3 is written to the card 1 at time T3, and the data W4 is written to the card 1 at time T4. It can be seen that the data storage is done serially.

In some optional implementations of this embodiment, before the step S201 of obtaining a write command for writing data and a number of the multiple memory card to the multiple memory card, the write command includes the data and the number, the electronic device may further perform a step of setting a rule of the write command.

The rule for setting the write command includes, for example, that the first byte of the set write command represents the number of the multi-memory card. Of course, the number of bytes representing the number of the multiple memory cards can be defined according to the actual requirement and the number of the multiple memory cards to be tested. Here, no limitation is made on the number of numbered bytes of the multi-memory card.

In the application, the multiple memory cards are numbered, and the numbered information is written into the multiple memory cards, so that the tracking test is convenient.

In this embodiment, the electronic device (e.g., the server/terminal device shown in fig. 1) on which the test method for multiple memory cards operates may receive the test request for multiple memory cards through a wired connection or a wireless connection. It should be noted that the wireless connection may include, but is not limited to, 3G/4G/5G connection, wiFi connection, bluetooth connection, wiMA multi-memory card test connection, zigbee connection, UWB (ultra wideband) connection, and other now known or later developed wireless connection.

Step S202, analyzing the writing command to obtain the data and the number, and writing the data into the multi-memory card according to the number.

In some optional implementations of this embodiment, the step of analyzing the write command to obtain the data and the number, and writing the data into the multi-memory card according to the number specifically includes:

analyzing the writing command to obtain the data and the number;

Caching the obtained data into a cache region;

Fig. 5 is a timing diagram of test data transmission of the multi-memory card of the present application. As shown in fig. 5, the data W1, W2, W3, and W4 may be written to the memory card 1 at the same time in one T1 time, and the control circuit (master) may also write the data W1, W2, W3, and W4 to the memory card 2 or/and the memory card 3 or/and the memory card 4 in the T1 time. The numbers of the memory card 1, the memory card 2, the memory card 3, the memory card 4, and the like are obtained by analyzing the write command. The data W1, W2, W3 and W4 may be buffered in the buffer before the data W1, W2, W3 and W4 are written to the memory card 2 or/and the memory card 3 or/and the memory card 4 in the time T1. A data output buffer is provided for temporarily storing data during writing and a certain space is reserved in the memory area. I.e. the information output from the disk is temporarily stored using the main memory space. The purpose is to alleviate the contradiction of speed mismatch between CPU and I/O devices. The interrupt frequency of the CPU is reduced, and the limit on the interrupt response time of the CPU is relaxed. And the parallelism between the CPU and the I/O equipment is improved. It can be seen that with this embodiment, the data storage is performed in parallel, which can save time.

FIG. 6 is a schematic diagram of an embodiment of the present application for writing data to multiple memory cards simultaneously. As shown in fig. 6, the terminal issues an instruction for writing data into each memory card, the CPU executes the instruction, and the CPU controls the data of the terminal (host side) to be buffered in the buffer SRAM. The main control refers to the main control of the testing device, the main control is welded on a PCB, one end of the PCB is provided with an interface connected with a host end, and the other end is provided with a clamping groove for inserting a plurality of memory cards so as to realize the connection of the cards to the testing board.

Specifically, when the test is started, the CPU in the main control firstly writes the data W1, W2, W3 and W4 of the host end into the buffer area, and then writes the data W1, W2, W3 and W4 of the buffer area into each card, so that the data is written into each card simultaneously.

Step S203, the data are read from every two different numbered multiple memory cards, the read data are stored in a comparison circuit to carry out exclusive OR operation, and whether the two different numbered multiple memory cards are normal or not is judged according to the result of the exclusive OR operation.

In some optional implementations of this embodiment, the step of reading the data from each two different numbered multiple memory cards, and placing the read data into a comparison circuit to perform an exclusive-or operation, and determining whether the multiple memory cards are normal according to an exclusive-or operation result specifically includes:

The embodiment of the application further claims to read the data in each card at the same time so as to judge whether the data can be read and accurately read (compared with the data written by a host computer, the data has no error). Testing of the performance of individual cards is achieved based on the fact that the data can be read and accurately read.

FIG. 7 is a schematic diagram of another embodiment of the present application for writing data to multiple memory cards simultaneously. As shown in fig. 7, based on this, the master control according to the embodiment of the present application further includes a comparison circuit, more specifically an exclusive or circuit. Because the same data is written into each card, the CPU in the main control controls the data to be read from every two cards, and the data divided by the data is put into the comparison circuit for exclusive OR operation. The same data in two cards is expressed in binary '0', '1', the data is exclusive-ored by exclusive-ored circuit, if the two cards are OK, the exclusive-ored result is '0', if one card is NG (Not Good, failed), the exclusive-ored result is '1'.

Specifically, since data is read from the memory card in a byte-by-byte manner, the data comparison, i.e., exclusive or operation, is performed byte-by-byte, and the data reading/writing principle of the memory card is to read/write byte by byte.

Further, since the data is composed of a plurality of bytes, the comparison circuit, or exclusive-or circuit, is effectively a byte exclusive-or accumulation circuit, the data is continuous, exclusive-or operation byte by byte, and is effectively an accumulated logic. The accumulated hardware may be registers.

Specifically, as long as the result of one byte exclusive or operation is "1", it means that the test result of one card is NG, and the test result of the memory card can be known.

Illustratively, in fig. 7, there are 4 cards, the data in the cards 1 and 2 are xored, the data in the cards 3 and 4 are xored, if the result of the xored of the data in the cards 1 and 2 is "0" and the result of the xored of the data in the cards 3 and 4 is "1", it means that at least one card of the cards 3 and 4 is NG, the data in the cards 1 and 3 are xored, or the data in the cards 1 and 4 are xored, or the data in the cards 2 and 3 are xored, or the data in the cards 2 and 4 are xored. Thus, NG in all cards or testing all cards may be performed.

A and B are equivalent to A and B being identical or opposite, i.e

The deformation obtains the logical expression.

The corresponding logic circuit consists of two NOR gates and an AND gate. For 8-bit binary comparison, the logic circuits are connected in series with 8 groups.

The corresponding single cmos exclusive-OR gate circuit consists of a first-stage NOR gate and a first-stage AND NOR gate. For inputs A and B, the inputs are first obtained through a NOR gateAnd then the exclusive OR output of A and B is obtained through an AND NOR gate.

Truth table:

A	B	NOR gate output	And NOR gate output
				0	0	1	0
0	1	0	1
				1	0	0	1
1	1	0	0

The process of testing the memory card is that external data is firstly input into BULK FIFO of SRAM to wait for processing through multi-interface such as USB interface, 2k or other data are required to be input according to data of SRAM1235, FIFO data are then compiled and decoded according to read-write requirement of SRAM1235 (SRAM needs to be transmitted to exclusive OR circuit data, w/r), operation is completed, and then returned to SRAM, and re-stored to USB or other operations according to requirement. Each write will overwrite the previous data of the SRAM FIFO.

Data alignment illustrates:

1001 1100 0011 0001 0101 1110 1011 0111 (mother card 32 bit binary data);

9 c 31 e b 7 (32 bit 16 system);

1001 1100 0011 0011 0101 1100 1011 0111 (daughter card 32 bit binary data);

9 c3 35 c b 7 (16);

it can be seen that the 4 th and 6 th 8bit bits are erroneous.

Exclusive or comparison result:

0000 0000 0000 0010 0000 0010 0000 0000 (system 2);

00 020 200 (16 scale).

Fig. 8 is an exclusive-or circuit diagram of 8 bits according to the present application. As shown in fig. 8, two devices, NMOS and PMOS, are mainly included. The source S of PMOS1 is connected to the drain D of PMOS2, the source of PMOS2 is connected to the drain D, NMOS1 drain D of the gate G, NMOS2 of the gate G, NMOS of PMOS5, and PMOS1, PMOS2, NMOS1, NMOS2 constitute nor gate a. PMOS3, PMOS4, NMOS5, or nand gate B. The drain electrode D of the PMOS3 is connected with the drain electrode D of the PMOS4, the grid electrode of the PMOS4 is connected with the grid electrode of the NMOS4, the source electrode of the NMOS4 is connected with the drain electrode of the NMOS5, and the drain electrodes of the NMOS4 are respectively connected with the source electrode of the PMOS5 and the drain electrode of the NMOS 3. PMOS5 and NMOS3 form not gate C. The source of PMOS5 is connected to the drain of NMOS 3. And the source and the drain are conducted when the NMOS is at the high level (1) of G, otherwise, the source and the drain are conducted when the grid in the PMOS is at the low level. The operating principle is that the nor gate part outputs a high level only when a and b are simultaneously 1 (high level) for inputs a and b. The nand gate outputs a and b, and the output is 0 (low level) only when a and b are 1 at the same time. The not gate inverts the input.

Nand gate series corresponds to a logical algebraic formula: A and B are not, the output value is inverted (NOT gate) and then AND (corresponding series connection) is carried out with the NOT gates of A and B.

Fig. 9 is a logic circuit diagram of the present application. As shown in fig. 9, in the reference code formulaAnd A and B phases, and outputting the NOR value of the value A and B to perform NOR operation.

In some optional implementations of this embodiment, step S203 may further include the step of displaying the abnormal multi-memory card number after reading the data from each two different-numbered multi-memory cards, storing the read data in the comparison circuit, performing an exclusive-or operation, and determining whether the two different-numbered multi-memory cards are normal according to a result of the exclusive-or operation. Through setting up the display interface, show that there is unusual many memory card numbers, the convenience of customers knows which many memory cards need retest or need to carry out maintenance etc. like this, and the convenience of customers carries out quality follow-up to having unusual many memory cards.

Through numbering the multiple memory cards, the data are written into the multiple memory cards at the same time, the test of the memory cards can be automatically executed without relying on manpower, the cost is saved, the test efficiency can be improved, the test is reliable and easy to realize, and the method is universally applicable to the test of the memory cards.

Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by computer readable instructions stored in a computer readable storage medium that, when executed, may comprise the steps of the embodiments of the methods described above. The storage medium may be a nonvolatile storage medium such as a magnetic disk, an optical disk, a Read-Only Memory (ROM), or a random access Memory (Random Access Memory, RAM).

It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited in order and may be performed in other orders, unless explicitly stated herein. Moreover, at least some of the steps in the flowcharts of the figures may include a plurality of sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, the order of their execution not necessarily being sequential, but may be performed in turn or alternately with other steps or at least a portion of the other steps or stages.

Example two

With further reference to fig. 10, as an implementation of the method shown in fig. 2, the present application provides an embodiment of a testing apparatus for multiple memory cards, where the embodiment of the apparatus corresponds to the embodiment of the method shown in fig. 2, and the apparatus is particularly applicable to various electronic devices.

As shown in fig. 10, the multi-memory card testing device 400 according to the present embodiment includes an acquisition module 401, a writing module 402, and a discrimination module 403. Wherein:

an obtaining module 401, configured to obtain a write command for writing data and a number of a multi-memory card into the multi-memory card, where the write command includes the data and the number;

A writing module 402, configured to parse the writing command, obtain the data and the number, and write the data into the multi-memory card according to the number;

The judging module 403 is configured to read the data from each two different numbered multiple memory cards, store the read data into the comparing circuit, perform an exclusive-or operation, and judge whether the two different numbered multiple memory cards are normal according to the result of the exclusive-or operation.

Referring to fig. 11, in order to schematically illustrate the structure of one embodiment of the writing module 402, the writing module 402 further includes an analyzing module 4021, a buffering module 4022, and an output module 4023. Wherein,

The parsing module 4021 is configured to parse the write command to obtain the data and the number;

a buffer module 4022, configured to buffer the obtained data in a buffer;

The output module 4023 is configured to write the data in the buffer into the multiple memory cards according to the number.

By setting the buffer module, the contradiction of speed mismatch between the CPU and the I/O device is alleviated. The interrupt frequency of the CPU is reduced, the limit on the interrupt response time of the CPU is relaxed, and the integrity of the written data is protected.

Example III

In order to solve the technical problems, the embodiment of the application also provides computer equipment. Referring specifically to fig. 12, fig. 12 is a basic structural block diagram of a computer device according to the present embodiment.

The computer device 6 comprises a memory 61, a processor 62, a network interface 63 communicatively connected to each other via a system bus. It is noted that only the computer device 6 having the component memory 61, the processor 62 and the network interface 63 is shown in the figures, but it is understood that not all of the illustrated components are required to be implemented and that more or fewer components may be implemented instead. It will be appreciated by those skilled in the art that the computer device herein is a device capable of automatically performing numerical calculation and/or information processing according to a preset or stored instruction, and its hardware includes, but is not limited to, a microprocessor, an Application SPECIFIC INTEGRATED Circuit (ASIC), a Programmable gate array (Field-Programmable GATE ARRAY, FPGA), a digital Processor (DIGITAL SIGNAL Processor, DSP), an embedded device, and the like.

The computer equipment can be a desktop computer, a notebook computer, a palm computer, a cloud server and other computing equipment. The computer equipment can perform man-machine interaction with a user through a keyboard, a mouse, a remote controller, a touch pad or voice control equipment and the like.

The memory 61 includes at least one type of readable storage medium including flash memory, hard disk, multi-memory card, card-type memory (e.g., test memory for SD or D multi-memory card, etc.), random Access Memory (RAM), static Random Access Memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the storage 61 may be an internal storage unit of the computer device 6, such as a hard disk or a memory of the computer device 6. In other embodiments, the memory 61 may also be an external storage device of the computer device 6, such as a plug-in hard disk, a smart memory card (SMART MEDIA CARD, SMC), a Secure Digital (SD) card, a flash memory card (FLASH CARD) or the like, which are provided on the computer device 6. Of course, the memory 61 may also comprise both an internal memory unit of the computer device 6 and an external memory device. In this embodiment, the memory 61 is typically used to store an operating system and various application software installed on the computer device 6, such as computer readable instructions of a test method for multiple memory cards. Further, the memory 61 may be used to temporarily store various types of data that have been output or are to be output.

The processor 62 may be a central processing unit (Central Processing Unit, CPU), controller, microcontroller, microprocessor, or other data processing chip in some embodiments. The processor 62 is typically used to control the overall operation of the computer device 6. In this embodiment, the processor 62 is configured to execute computer readable instructions stored in the memory 61 or process data, such as computer readable instructions for executing the test method of the multi-memory card.

The network interface 63 may comprise a wireless network interface or a wired network interface, which network interface 63 is typically used for establishing a communication connection between the computer device 6 and other electronic devices.

Example IV

The present application also provides another embodiment, namely, a computer readable storage medium storing computer readable instructions executable by at least one processor to cause the at least one processor to perform the steps of the multi-memory card test method as described above.

From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal device (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to perform the method according to the embodiments of the present application.

It is apparent that the above-described embodiments are only some embodiments of the present application, but not all embodiments, and the preferred embodiments of the present application are shown in the drawings, which do not limit the scope of the patent claims. This application may be embodied in many different forms, but rather, embodiments are provided in order to provide a thorough and complete understanding of the present disclosure. Although the application has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described in the foregoing description, or equivalents may be substituted for elements thereof. All equivalent structures made by the content of the specification and the drawings of the application are directly or indirectly applied to other related technical fields, and are also within the scope of the application.

Claims

1. A method for testing multiple memory cards, comprising the steps of:

Setting a rule of a write command, wherein a first byte of the write command represents a serial number of a multi-memory card;

Reading the data from every two different numbered multiple memory cards, storing the read data into a comparison circuit for exclusive-OR operation, and judging whether the two different numbered multiple memory cards are normal according to the result of the exclusive-OR operation, wherein the data is read from every two different numbered multiple memory cards, the read data is put into the comparison circuit for exclusive-OR operation, and the step of judging whether the multiple memory cards are normal according to the result of the exclusive-OR operation specifically comprises the following steps:

2. The method for testing multiple memory cards according to claim 1 wherein said step of parsing said write command to obtain said data and said number and writing said data into multiple memory cards according to said number specifically comprises:

analyzing the writing command to obtain the data and the number;

Caching the obtained data into a cache region;

3. The method for testing multiple memory cards according to claim 1 or 2, wherein after the step of reading the data from each two different numbered multiple memory cards, placing the read data into a comparison circuit to perform exclusive-or operation, and determining whether the multiple memory cards are normal according to the exclusive-or operation result, the method further comprises:

And displaying the abnormal multi-memory card numbers.

4. A multi-memory card test apparatus, comprising:

the system comprises an acquisition module, a storage module and a storage module, wherein the acquisition module is used for setting a rule of a writing command, setting that a first byte of the writing command represents a serial number of a plurality of storage cards, and acquiring the writing command for writing data and the serial number of the plurality of storage cards into the plurality of storage cards, wherein the writing command comprises the data and the serial number;

The judging module is used for reading the data from each two multi-memory cards with different numbers, storing the read data into the comparing circuit for exclusive-OR operation, judging whether the two multi-memory cards with different numbers are normal according to the result of the exclusive-OR operation, wherein the data are read from each two multi-memory cards with different numbers, storing the read data into the comparing circuit for exclusive-OR operation, judging whether the multi-memory cards are normal according to the result of the exclusive-OR operation, specifically comprising the steps of carrying out two-by-two grouping according to the number of the multi-memory cards, reading the data from each two multi-memory cards with different numbers, storing the read data into the comparing circuit for exclusive-OR operation, judging that the two multi-memory cards with different numbers are normal if the result of the exclusive-OR operation is 0, judging that one memory card of the two multi-memory cards with different numbers is abnormal if the result of the exclusive-OR operation is 1, marking the group of the multi-memory cards with the abnormality, and carrying out exclusive-OR operation on each multi-memory card in the group of the multi-memory cards with the abnormality and the multi-memory cards detected by detecting that the multi-memory cards with the abnormality are normal until all the multi-memory cards with the abnormality are detected.

5. The multi-memory card testing device of claim 4, wherein the writing module comprises:

the caching module is used for caching the obtained data into a cache area;

And the output module is used for writing the data in the buffer area into the multi-memory card according to the number.

6. A computer device comprising a memory having stored therein computer readable instructions which when executed by a processor implement the steps of the method of testing a multi-memory card of any of claims 1 to 3.

7. A computer readable storage medium having stored thereon computer readable instructions which when executed by a processor perform the steps of the method of testing a multiple memory card according to any of claims 1 to 3.