CN114548013B - Silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) turn-on delay calculation method and application thereof - Google Patents
Silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) turn-on delay calculation method and application thereof Download PDFInfo
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Abstract
A calculation method of turn-on delay of a silicon carbide MOSFET comprises a transient analysis equivalent circuit of a silicon carbide MOSFET switch, and comprises the following steps: before u gs reaches the threshold voltage V th, the column write driving loop KVL equation and KCL equation; according to the IEC standard, when the positive driving voltage V GH with the u gs being 10 percent, after the starting point t a;ugs of the opening delay reaches the threshold voltage V th, Modeling i d and u gs into a linear relation by a row-write driving loop KCL equation and a KVL equation to obtain a u gs expression at the stage; Correcting i d by using the saturated current expression, deriving to obtain a current change rate, and obtaining an expression of u ds according to a KVL equation of the main power loop; according to the IEC standard, when u ds reaches 90% of the load voltage V DD, the value of time t is the end t b of the on delay; And obtaining the difference between t b and t a, namely the opening delay t d(on).
Description
Technical Field
The invention relates to a calculation method, in particular to a silicon carbide MOSFET (metal oxide semiconductor field effect transistor) turn-on delay calculation method and application thereof.
Background
Silicon carbide semiconductor devices have been an important part in the field of power electronics. Compared with the traditional silicon-based device, the silicon carbide MOSFET has a series of advantages of higher temperature and voltage level tolerance, lower conduction loss, higher switching speed and the like. Silicon carbide MOSFETs with voltage levels of 600V to 1700V have been widely used in various industrial fields such as renewable energy power generation, rail transit, electric automobiles, etc. With the continuous improvement of power semiconductor production process and packaging technology, the switch device gradually develops to the high frequency direction. The high frequency inevitably generates high-frequency voltage and current oscillations of high amplitude in the system, with negative effects. In order to mitigate the effects of these negative conditions, it is necessary to analyze the effects of driving loop parameters such as driving resistance, parasitic parameters on the switching characteristics for optimization. The turn-on delay is a very important parameter in the switching characteristic of the device, and comprises external circuit parameters such as R g、Lg and the like and device parameters such as C gd、Cgs and the like, so that the actual working condition is reflected. The existing opening delay calculation methods are all used for calculating the time required by the gate-source voltage to rise from the driving negative voltage to the threshold voltage, and are inconsistent with the extraction standard of the opening delay in IEC standards, so that theoretical modeling and experimental data cannot be compared. Therefore, the method for calculating the turn-on delay of the silicon carbide MOSFET under the IEC standard is not available. In addition, in the existing open transient process model established in the open delay calculation method, the driving voltage is considered to be in an ideal abrupt change state, and in the actual working condition, the driving voltage needs a certain delay time to rise from the driving negative voltage to the driving positive voltage, so that the modeling of the existing open transient process is not accurate enough, and the correction is needed.
Disclosure of Invention
Aiming at the current situation of the failure of the silicon carbide MOSFET turn-on delay calculation method and the application thereof, the invention provides a silicon carbide MOSFET turn-on delay calculation method which accords with IEC standards in the device turn-on transient process; and obtaining an opening delay expression in the opening process of the device by modeling the opening transient process of the device.
A silicon carbide MOSFET turn-on delay calculation method and application thereof are characterized in that: the method comprises the following steps:
Step one: before u gs reaches the threshold voltage V th, taking the rising delay time of the driving voltage into consideration, and solving a column-writing driving loop KVL equation and a KCL equation simultaneously to obtain a u gs expression at the stage;
step two: when the driving positive pressure V GH with the u gs being 10 percent, the value of the time t is the starting point t a of the opening delay;
Step three: after u gs reaches the threshold voltage V th, modeling i d and u gs into a linear relation by a row-write driving loop KCL equation and a KVL equation, and obtaining a u gs expression at the stage after simultaneous solving;
step four: correcting i d by using the saturated current expression, deriving to obtain a current change rate, and obtaining an expression of u ds according to a KVL equation of the main power loop;
step five: when u ds reaches 90% of the load voltage V DD, the value of time t is the end point t b of the turn-on delay;
Step six: obtaining a difference value between t b and t a, namely opening delay t d(on);
The calculation process from step one to step six is applied to the transient analysis equivalent circuit of the silicon carbide MOSFET switch in figure 1. The circuit comprises: the Q 1 device is a silicon carbide MOSFET, and R g、Lg、Ld and L s are respectively a driving resistor, a grid parasitic inductance, a drain parasitic inductance and a common source parasitic inductance; C gd、Cgs and C ds are respectively the gate-drain parasitic capacitance, the gate-source parasitic capacitance and the drain-source parasitic capacitance of the device; c bus is a bus capacitor; l p is a load inductance; SBD is a Schottky diode; v DD is the bus voltage; The gate voltage source outputs a pulse driving voltage U G.ugs with a high level V GH and a low level-V EE representing the gate-source voltage of Q 1, i d denotes the leakage current of Q 1, and u ds denotes the drain-source voltage of Q 1. On this basis, the drive circuit includes: the driving voltage source U G, the driving resistor R g, the grid parasitic inductance L g and the other end of the parasitic inductance L g which are connected in sequence are connected with the grid of the Q 1, And is in turn connected to the gate-source parasitic capacitance C gs, the common-source parasitic inductance L s. The main power loop includes: sources of Q 1, common source parasitic inductance L s, schottky diode SBD, load inductance L p, drain parasitic inductance L d, and Q 1, which are connected in sequence.
The invention also discloses a method for calculating the turn-on delay of the silicon carbide MOSFET, which is applied to a power electronic control system.
Compared with the prior art, the invention has the following advantages:
The advantages are as follows: the existing opening delay calculation methods are all used for calculating the time required by the gate-source voltage to rise from the driving negative voltage to the threshold voltage, and are inconsistent with the extraction standard of the opening delay in IEC standards, so that theoretical modeling and experimental data cannot be compared. Aiming at the extraction method of the opening delay used in the experiment, the invention obtains the opening delay expression in the opening process of the device conforming to the IEC standard by re-modeling the opening transient process of the device.
The advantages are as follows: in the existing modeling of the on transient process, the driving voltage is modeled as an ideal abrupt change state, but in the actual working condition, the delay time required for the process of rising from the driving negative voltage to the driving positive voltage cannot be ignored. Therefore, the invention provides an open transient process model considering the rising delay time of the driving voltage, and in the existing modeling, in order to facilitate the calculation of the gate-source voltage expression, the relation between the leakage current and the gate-source voltage is modeled as linearity, and the open transient modeling provided by the invention corrects the point in the subsequent calculation of the leakage current expression, so that the open transient modeling is more accurate compared with the existing model.
The method has the following advantages: according to the method for calculating the turn-on delay of the silicon carbide MOSFET and the application thereof, the method can be used for analyzing the influence of device parameters or external circuit parameters on the turn-on characteristics of the device, and has important significance for optimizing the device.
Drawings
FIG. 1 is a transient analysis equivalent circuit of a silicon carbide MOSFET switch;
FIG. 2 is an opening delay extraction requirement under IEC standard;
fig. 3 is a method for calculating turn-on delay of silicon carbide MOSFET and its application flow.
Detailed Description
Aiming at a silicon carbide MOSFET (metal oxide semiconductor field effect transistor) turn-on delay calculation method and application thereof, the invention provides a silicon carbide MOSFET turn-on delay calculation method which accords with IEC standards in the device turn-on transient process. And obtaining an opening delay expression in the opening process of the device by modeling the opening transient process of the device.
The invention provides a silicon carbide MOSFET turn-on delay calculation method and an application flow thereof, which are shown in figure 3.
Step one: before u gs reaches the threshold voltage V th, taking the rising delay time of the driving voltage into consideration, and solving a column-writing driving loop KVL equation and a KCL equation simultaneously to obtain a u gs expression at the stage;
step two: according to IEC standard, when the driving positive pressure V GH with the u gs being 10%, the value of the time t is the starting point t a of the opening delay;
Step three: after u gs reaches the threshold voltage V th, modeling i d and u gs into a linear relation by a row-write driving loop KCL equation and a KVL equation, and obtaining a u gs expression at the stage after simultaneous solving;
step four: correcting i d by using the saturated current expression, deriving to obtain a current change rate, and obtaining an expression of u ds according to a KVL equation of the main power loop;
step five: according to the IEC standard, when u ds reaches 90% of the load voltage V DD, the value of time t is the end t b of the on delay;
Step six: obtaining a difference value between t b and t a, namely opening delay t d(on);
the steps are described in detail below.
Step one: the Q 1 channel is not turned on until the threshold voltage V th is reached from u gs and the gate voltage source charges C gd and C gs. Since the rise in drive voltage is not an ideal abrupt change, a linear rise from-V EE to V GH, a delay time c must elapse, and thus the drive voltage is modeled as a linear relationship with time. Column write drive loop KVL equation and KCL equation:
The combination formula (1) and the formula (2) can be obtained:
Wherein t 0 is taken as a starting time, t 1 is taken as a starting conduction time of Q 1, c is a driving voltage rising delay time, τ 0＝Rg(Cgs+Cgd), and u gs(t1)＝Vth is obtained as an initial value of the third step.
Step two: according to the IEC standard as shown in FIG. 2, when the drive positive pressure V GH is 10% in u gs, the value of time t is the start t a of the on delay. Let u gs＝10％VGH solve to:
Step three: after u gs reaches the threshold voltage V th, the gate voltage source voltage rises to V GH to charge C gd and C gs, the Q 1 channel is turned on, I d rises from 0 to I DD, and a small drop in u ds occurs under the influence of loop parasitic inductances L d and L s. Column write drive loop KVL equation and KCL equation:
Where i g is the gate drive current.
In the process that I d rises from 0 to I DD, since the drop of u ds is relatively small, the displacement current on the drain-source capacitance can be ignored, the relation between I d and u gs is simplified to be the relation between the channel current and the gate voltage, and the relation is modeled to be a linear relation, so that the following conditions are satisfied:
id＝gfs(ugs(t)-Vth) (7)
Where g fs is the silicon carbide MOSFET transconductance.
Column write main power loop voltage equation (ignoring diode forward drop):
The simultaneous equations (5) to (8) can be obtained as the second differential equation for u gs:
Wherein a＝RgCgdgfs(Ls+Ld)+CgsLs,b＝Rg(Cgs+Cgd)+gfsLs, is substituted into the initial condition in step one, typically 4a < b 2, and thus solved:
Step four: in step three, to find the u gs expression, the relationship of i d to u gs needs to be simplified to facilitate computation. However, in order to find the expression i d, the linear relationship in the expression (7) is not accurate enough, and the device enters the saturation current operating region, so that the linear relationship between i d and u gs is corrected by using the saturation current formula, and the following conditions are satisfied:
Where μ ni is electron mobility in the inversion layer, C ox is the characteristic capacitance of the oxide layer, z is the channel width, and L CH is the channel length.
Deriving the formula (11), and obtaining the current change rate as follows:
Bringing formula (12) into formula (8), solving for the u ds expression:
step five: according to the IEC standard as shown in FIG. 2, when u ds reaches 90% of the load voltage V DD, the value of time t is the end t b of the on-delay. Let u ds＝90％VDD solve to:
Step six: the difference between t b and t a is calculated as the on delay time t d(on):
The silicon carbide MOSFET turn-on delay calculation method and the application thereof are obtained according to the device turn-on process from the first step to the sixth step, and the method comprises external circuit parameters such as R g、Lg and device parameters such as C gd、Cgs, and reflects the actual working condition.
The steps one to six adopted by the technical scheme of the invention are combined, so that the method can obtain an opening transient model and an opening delay expression which are more in line with the actual working condition than the existing model, are higher in accuracy, are applicable to IEC standards, and have important significance for opening delay analysis work in the future modeling and experiments.
The above expression (15) can be used for the following requirements:
(1) And analyzing the influence of the device parameters or the external circuit parameters on the on-state characteristics of the device, if the influence of the L s on the on-state delay is to be analyzed, giving the rest required parameters, substituting different L s to obtain corresponding on-state delay, and analyzing the change trend of the on-state delay along with the L s to obtain the influence of the L s on the on-state delay, thereby evaluating the influence of the L s on the electrical stress of the device.
(2) The threshold voltage of the silicon carbide MOSFET in the transient process is influenced by the driving negative voltage, but the threshold voltage in the transient process cannot be measured, so that the influence of the driving negative voltage on threshold hysteresis can be evaluated by calculating the threshold voltage in the transient process through the opening delay expression.
Aiming at IEC standards, the invention establishes a turn-on transient model which is more in line with actual working conditions, thereby obtaining a more accurate calculation method of the turn-on delay of the silicon carbide MOSFET. The invention obtains an opening delay expression based on analysis of the complete opening process of the device; the silicon carbide MOSFET turn-on delay calculation method and the application thereof provided by the invention have the advantages that the expression contains all relevant device parameters or external circuit parameters, and the method can be used for analyzing turn-on delay influence factors.
The foregoing has shown and described the basic principles, principal features and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that the above embodiments and descriptions are merely illustrative of the principles of the present invention, and various changes and modifications may be made therein without departing from the spirit and scope of the invention, which is defined by the appended claims. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (1)
1. A silicon carbide MOSFET turn-on delay calculation method is characterized in that: the method comprises the following steps:
Step one: before u gs reaches the threshold voltage V th, taking the rising delay time of the driving voltage into consideration, and solving a KVL equation and a KCL equation of a column writing driving loop simultaneously to obtain a u gs expression at the stage; before reaching the threshold voltage V th from u gs, the Q 1 channel is not turned on and the gate voltage source charges C gd and C gs; since the rise of the driving voltage is not an ideal abrupt change, the linear rise from-V EE to V GH, a delay time c must elapse, and thus the driving voltage is modeled as a linear relationship with time; column write drive loop KVL equation and KCL equation:
The combination formula (1) and the formula (2) can be obtained:
Taking t 0 as a starting time, t 1 as Q 1 as a starting conduction time, c as a driving voltage rising delay time, τ 0＝Rg(Cgs+Cgd), and simultaneously obtaining u gs(t1)＝Vth as an initial value of the third step;
Step two: according to IEC standard, when the driving positive pressure V GH with the u gs being 10%, the value of the time t is the starting point t a of the opening delay; according to IEC standard, when the driving positive pressure V GH with the u gs being 10%, the value of the time t is the starting point t a of the opening delay; let u gs＝10％VGH solve to:
Step three: after u gs reaches the threshold voltage V th, modeling i d and u gs into a linear relation by a row-write driving loop KCL equation and a KVL equation, and obtaining a u gs expression at the stage after simultaneous solving; after u gs reaches the threshold voltage V th, the gate voltage source voltage rises to V GH to charge C gd and C gs, the Q 1 channel is opened, I d rises from 0 to I DD, and u ds falls slightly under the influence of loop parasitic inductances L d and L s; column write drive loop KVL equation and KCL equation:
Wherein i g is the gate drive current;
In the process that I d rises from 0 to I DD, since the drop of u ds is relatively small, the displacement current on the drain-source capacitance can be ignored, the relation between I d and u gs is simplified to be the relation between the channel current and the gate voltage, and the relation is modeled to be a linear relation, so that the following conditions are satisfied:
id＝gfs(ugs(t)-Vth) (7)
Wherein g fs is the silicon carbide MOSFET transconductance;
neglecting diode forward voltage drop, the column writes the main power loop voltage equation:
The simultaneous equations (5) to (8) can be obtained as the second differential equation for u gs:
Wherein a＝RgCgdgfs(Ls+Ld)+CgsLs,b＝Rg(Cgs+Cgd)+gfsLs, is substituted into the initial condition in step one, typically 4a < b 2, and thus solved:
Step four: correcting i d by using the saturated current expression, deriving to obtain a current change rate, and obtaining an expression of u ds according to a KVL equation of the main power loop; in the third step, in order to obtain the expression u gs, the relationship between i d and u gs needs to be simplified to facilitate calculation; however, in order to find the expression i d, the linear relationship in the expression (7) is not accurate enough, and the device enters the saturation current operating region, so that the saturation current formula is used to correct the nonlinear square relationship between i d and u gs, and the following conditions are satisfied:
Wherein mu ni is electron mobility in the inversion layer, C ox is characteristic capacitance of the oxide layer, z is channel width, and L CH is channel length;
Deriving the formula (11), and obtaining the current change rate as follows:
Bringing formula (12) into formula (8), solving for the u ds expression:
Step five: according to IEC standard, when u ds reaches 90% of load voltage V DD, the value of time t is the end t b of the on delay; according to the IEC standard, when u ds reaches 90% of the load voltage V DD, the value of time t is the end point t b of the on delay; let u ds＝90％VDD solve to:
Step six: obtaining a difference value between t b and t a, namely opening delay t d(on);
The difference between t b and t a is calculated as the on delay time t d(on):
The calculation process from the first step to the sixth step is applied to a transient analysis equivalent circuit of the silicon carbide MOSFET switch; the equivalent circuit includes: the Q 1 device is a silicon carbide MOSFET, and R g、Lg、Ld and L s are respectively a driving resistor, a grid parasitic inductance, a drain parasitic inductance and a common source parasitic inductance; C gd、Cgs and C ds are respectively the gate-drain parasitic capacitance, the gate-source parasitic capacitance and the drain-source parasitic capacitance of the device; c bus is a bus capacitor; l p is a load inductance; SBD is a Schottky diode; v DD is the bus voltage; The gate voltage source outputs a pulse driving voltage U G;ugs with a high level V GH and a low level-V EE representing the gate-source voltage of Q 1, i d denotes the leakage current of Q 1, u ds denotes the drain-source voltage of Q 1; On the basis, the driving circuit structure is as follows: the driving voltage source U G, the driving resistor R g, the grid parasitic inductance L g and the other end of the parasitic inductance L g which are connected in sequence are connected with the grid of the Q 1, And is sequentially connected with the gate-source parasitic capacitance C gs and the common-source parasitic inductance L s; The main power loop structure is as follows: sources of Q 1, common source parasitic inductance L s, schottky diode SBD, load inductance L p, drain parasitic inductance L d, and Q 1, which are connected in sequence.
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