CN114546907A - Data sending and receiving method, device, equipment and storage medium - Google Patents

Abstract

The embodiments of the present application disclose a data transmission and reception method, device, device and storage medium. A first processing module accesses a FIFO (transmitting FIFO or receiving FIFO) through a first bus, and a second processing module communicates with the buffer through a buffer common interface. connected to the FIFO (transmit buffer or receive buffer), and then access the FIFO through the second bus. When performing data transmission and reception, the read data volume or the write data volume of the FIFO is determined based on the control parameters of the FIFO (transmit FIFO or receive FIFO) in the control register; based on the read data volume or the write data volume, the first processing module passes through the first bus. Read or write the FIFO, the second processing module reads or writes the FIFO through the buffer and the second bus, so that the buffered data exchange between the first processing module and the second processing module, thus realizing a friendly interface between modules data exchange, reducing the bus burden.

Description

A data transmission and reception method, apparatus, device and storage medium

technical field

The present application relates to computer technology, and in particular, to a data transmission and reception method, apparatus, device, and storage medium.

Background technique

In chip design, due to the requirements of memory management, software and hardware often need to transfer a large number of memory pointers to each other. At this time, it is necessary to apply buffers to match different processing speeds to achieve the purpose of pipeline operation.

Usually, the buffering of data within the hardware and the transmission across clock domains are inseparable from the First In First Out (FIFO) queue. The FIFO is mainly composed of a random access memory (Random Access Memory, RAM) and a FIFO controller. When writing data, the write data terminal only needs to issue the write enable and write data, the write pointer control will immediately calculate the corresponding write address, and the data will be written to the RAM when the write enable is valid. When reading data, the read data terminal only needs to issue the read enable, the read pointer control will immediately calculate the corresponding read address, and the data will be read out of the RAM in the next beat when the read enable is valid.

In the prior art, the data interaction between the software module and the hardware module usually needs to complete the read and write control of the FIFO through the bus, which increases the bus burden and also increases the design complexity of the hardware module.

SUMMARY OF THE INVENTION

In order to solve the above technical problems, the embodiments of the present application expect to provide a method, apparatus, device, and storage medium for sending and receiving data.

The technical solution of the present application is realized as follows:

In a first aspect, a data sending method is provided, including:

Determine the read data volume of the transmit FIFO based on the control parameter of the transmit FIFO in the transmit control register; wherein the first processing module writes the transmit data into the transmit FIFO through the first bus;

Based on the amount of read data, read data from the transmit FIFO into the transmit buffer through the second bus;

The sending buffer is controlled to send the data of the first processing module to the second processing module.

In a second aspect, a data receiving method is provided, including:

controlling the receiving buffer to receive the data of the second processing module;

Determine the write data volume of the receiving FIFO based on the control parameter of the receiving FIFO in the receiving control register;

Based on the write data amount, write the data in the receive buffer into the receive FIFO through the second bus, so that the first processing module can read the data from the receive FIFO through the first bus The data of the second processing module.

In a third aspect, a data sending apparatus is provided, the data sending apparatus comprising: a sending control register, a sending controller and a sending buffer;

The transmission control register is used to store the control parameters of the transmission FIFO; wherein, the first processing module writes the transmission data into the transmission FIFO through the first bus;

The transmission controller is configured to determine the read data volume of the transmission FIFO based on the control parameter of the transmission FIFO in the transmission control register; based on the read data volume, read data from the transmission FIFO through the second bus to in the send buffer;

The sending controller is further configured to control the sending buffer to send the data of the first processing module to the second processing module.

In a fourth aspect, a data receiving apparatus is provided, the data receiving apparatus comprising: a receiving control register, a receiving controller and a receiving buffer;

the receiving buffer, for receiving data of the second processing module;

The receiving control register is used to store the control parameters of the receiving FIFO;

The receiving controller is configured to determine the write data amount of the receive FIFO based on the control parameter of the receive FIFO in the receive control register; based on the write data amount, write the data in the receive buffer through the second bus into the receiving FIFO for the first processing module to read the data of the second processing module from the receiving FIFO through the first bus.

In a fifth aspect, there is provided an electronic device comprising: a processor and a memory configured to store a computer program executable on the processor,

Wherein, the processor is configured to execute the steps of the method of the first aspect or the second aspect when running the computer program.

In a sixth aspect, a computer-readable storage medium is provided, on which a computer program is stored, wherein when the computer program is executed by a processor, the steps of the method of the first aspect or the second aspect are implemented.

Embodiments of the present application provide a data transmission and reception method, device, device, and storage medium, wherein the data transmission method includes: determining the read data volume of the transmission FIFO based on a control parameter of the transmission FIFO in the transmission control register; The first processing module writes the sending data into the sending FIFO through the first bus; based on the amount of read data, reads the data from the sending FIFO into the sending buffer through the second bus; controls the The sending buffer sends the data of the first processing module to the second processing module. The data receiving method includes: controlling a receiving buffer to receive data of a second processing module; determining a write data volume of the receiving FIFO based on a control parameter of a receiving FIFO in a receiving control register; The data in the processor is written into the receiving FIFO through the second bus, so that the first processing module can read the data of the second processing module from the receiving FIFO through the first bus. In this way, the first processing module accesses the FIFO (transmitting FIFO or receiving FIFO) through the first bus, the second processing module is connected to the buffer (transmitting buffer or receiving buffer) through the buffer common interface, and then accesses the FIFO through the second bus , realizes a friendly interface data exchange between modules and reduces the bus burden. Further, by setting the control parameters in the register, the method realizes the function of high flexibility cross-module data exchange with variable FIFO depth.

Description of drawings

1 is a schematic flowchart of a data sending method in an embodiment of the present application;

2 is a schematic structural diagram of a data transmission system in an embodiment of the application;

3 is a schematic flowchart of the first processing module writing data to the sending FIFO in the embodiment of the application;

4 is a schematic flowchart of a second processing module reading data from the transmission FIFO in the embodiment of the application;

5 is a schematic flowchart of a data receiving method in an embodiment of the present application;

6 is a schematic structural diagram of a data receiving system in an embodiment of the application;

7 is a schematic flowchart of a second processing module writing data to a receiving FIFO in an embodiment of the present application;

8 is a schematic flowchart of a first processing module reading data from a receiving FIFO in an embodiment of the present application;

FIG. 9 is a schematic diagram of the composition and structure of a data sending and receiving system in an embodiment of the application;

FIG. 10 is a schematic diagram of the composition and structure of a data sending apparatus in an embodiment of the present application;

FIG. 11 is a schematic diagram of the composition and structure of a data receiving apparatus in an embodiment of the present application

FIG. 12 is a schematic diagram of the composition and structure of an electronic device in an embodiment of the present application.

Detailed ways

In order to have a more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

An embodiment of the present application provides a data sending and receiving method, wherein the data sending method is used to enable a first processing module to send data to a second processing module, and the data receiving method is used to enable the first processing module to receive data from the second processing module data. FIG. 1 is a schematic flowchart of a data sending method in an embodiment of the present application. As shown in FIG. 1 , the method may specifically include:

Step 101: Determine the read data volume of the transmission FIFO based on the control parameter of the transmission FIFO in the transmission control register; wherein, the first processing module writes the transmission data into the transmission FIFO through the first bus;

Exemplarily, in some embodiments, the control parameters of the transmit FIFO include: a base address and depth of a memory space where the transmit FIFO is located, a write pointer, a read pointer, a full flag and an empty flag of the transmit FIFO.

Base address: refers to the starting address of the memory space where the FIFO is located.

Depth: Refers to how many N bits of data can be stored in the FIFO, such as 8 bits, 16 bits, 32 bits, etc.

Read pointer: always points to the next read address, reads data temporarily at each clock edge, and points to the first address when reset;

Write pointer: always point to the current address to be written, write data at each clock edge, and point to the first address when reset;

Full flag: When the FIFO is full or about to be full, a signal is sent by the FIFO status circuit to prevent the FIFO write operation from continuing to write data to the FIFO and cause overflow (overflow).

Empty flag: When the FIFO is empty or about to be empty, a signal is sent by the FIFO status circuit to prevent the FIFO read operation from continuing to read data from the FIFO, resulting in invalid data readout (underflow).

Exemplarily, in some embodiments, the method further includes: configuring the base address and depth of the memory space where the transmit FIFO is located in the transmit control register. Here, the data is stored in the memory space. By configuring the base address and depth of the memory space where the transmission FIFO is located in the transmission control register, the FIFO depth can be flexibly set according to the usage scenario, and the data interaction is not limited by the FIFO depth, realizing highly flexible data interaction. Program.

Exemplarily, in some embodiments, the determining the read data volume of the transmit FIFO based on the control parameter of the transmit FIFO in the transmit control register includes: the empty flag in the transmit control register indicates that the transmit FIFO is not empty, and the transmit buffer is not full, the used space of the transmit FIFO is determined based on the read pointer and the write pointer of the transmit FIFO; based on the used space of the transmit FIFO, the used space of the transmit FIFO is determined. The amount of data read. Specifically, the used space of the transmit FIFO is obtained by subtracting the read pointer and the write pointer of the transmit FIFO.

Here, when the empty flag indicates that the transmission FIFO is not empty, it means that the transmission FIFO contains data sent by the first processing module to the second processing module, and the transmission buffer is not full means that the transmission buffer has available space for buffering the transmission data. When these two conditions are satisfied at the same time, the first processing module sends data to the second processing module by using the transmit FIFO and the transmit buffer.

Further, according to the used space of the sending FIFO, the amount of read data sent from the sending FIFO this time is determined, and the amount of read data does not exceed the amount of data stored in the used space of the sending FIFO. Exemplarily, the amount of read data is the amount of data stored in the used space of the sending FIFO, that is, all data in the sending FIFO is sent to the sending buffer during this sending process.

Exemplarily, in some embodiments, if the amount of read data is affected by the space of the sending buffer, the method further includes: determining the available space of the sending buffer; Using the space to determine the read data amount includes: determining a minimum space from the used space of the transmit FIFO and the available space of the transmit buffer; taking the data capacity corresponding to the minimum space as the read data amount . Here, the expression of the amount of read data may be the amount of read data=Min [the used space of the transmit FIFO, the free space of the transmit buffer].

Exemplarily, in some embodiments, the method further includes the first processing module writing data to the transmit FIFO. Specifically, the full flag in the transmit control register indicates that the transmit FIFO is not full, and the available space of the transmit FIFO is determined based on the read pointer and the write pointer of the transmit FIFO; based on the transmit FIFO The available space of the FIFO is used to determine the amount of write data that the first processing module writes into the transmit FIFO; and based on the amount of write data, the first processing module is controlled to write the transmit data into the transmit FIFO through the first bus. transmit FIFO. Specifically, the used space of the sending FIFO is obtained by subtracting the read pointer and the writing pointer of the sending FIFO, and the available space is obtained by subtracting the total space of the sending FIFO and the used space.

Here, the amount of written data does not exceed the amount of data corresponding to the available space of the transmit FIFO. Exemplarily, in some embodiments, the determining, based on the available space of the sending FIFO, the amount of write data written into the sending FIFO by the first processing module includes: corresponding to the available space of the sending FIFO; The minimum data amount among the data amount to be sent by the first processing module and the data amount to be sent by the first processing module is taken as the write data amount written into the sending FIFO by the first processing module. For example, if the amount of data to be sent is less than the amount of data corresponding to the available space in the send FIFO, the amount of data to be sent is taken as the amount of data to be written this time, and the amount of data to be sent is greater than or equal to the amount of data corresponding to the available space in the send FIFO, and the amount of data to be sent is taken as the amount of data corresponding to the available space in the send FIFO. The amount of data is used as the amount of write data.

Exemplarily, in some embodiments, after the first processing module is controlled to write the transmit data into the transmit FIFO through the first bus based on the amount of write data, the method further includes: The write pointer of the transmit FIFO in the transmit control register is updated.

Step 102: Based on the amount of read data, read data from the transmit FIFO into the transmit buffer through the second bus;

Exemplarily, in some embodiments, after the data is read from the transmit FIFO to the transmit buffer through the second bus based on the amount of read data, the method further includes: updating the transmit control the read pointer of the transmit FIFO in the register.

Step 103: Control the sending buffer to send the data of the first processing module to the second processing module.

Here, the second processing module is connected to the sending buffer through the buffer general interface, and is used for acquiring data in the sending buffer.

In practical applications, the first processing module and the second processing module may be different modules in the same electronic device, or may be different modules in different electronic devices.

Exemplarily, in some embodiments, the first processing module is a software module, and the second processing module is a hardware module. Here, the software module is connected to the sending FIFO through the first bus, and is used to write the sending data into the sending FIFO. FIFO data does not need to access the sending FIFO through the bus, so that the hardware module does not need to change the original FIFO interface, that is, the general FIFO interface is used to access the sending FIFO, so that the software module uses the bus interface to access the sending FIFO, so as to realize the buffered data across modules Swap, has good versatility.

The data sending method provided by the embodiment of the present application is implemented by a data sending device, and FIG. 2 is a schematic structural diagram of the data sending system in the embodiment of the present application. As shown in FIG. 2 , the data sending system includes a software module, a sending FIFO, a data sending device and a Hardware module, wherein, the data transmission device includes the following composition:

1. Send control register: used to set the control parameters of the send FIFO, including the base address (tx_fifo_base_addr) and depth (tx_depth) of the memory space where the send FIFO is located, the read and write pointers of the send FIFO (tx_rd_ptr (hw write) and tx_wr_ptr (sw write)), and empty full information (tx_full and tx_empty).

2. Sending controller: used to control the amount of data prefetched from the sending FIFO, send a read request to the sending FIFO through the first bus, and update the read pointer after the read is completed.

3. Sending buffer: used to connect the second processing module and the sending controller, and buffer the data prefetched from the sending FIFO.

Among them, the hardware module is connected with the sending buffer through a general interface, the sending controller is connected with the sending control register and the sending buffer, and the sending controller is connected with the sending FIFO through the second bus, which is used to read the data buffer from the sending FIFO to the sending In the buffer, the software module is connected with the sending FIFO through the first bus, and is used for writing data to the sending FIFO. Here, the first bus and the second bus may also be collectively referred to as buses, which are used to implement connection and communication between components.

FIG. 3 is a schematic flowchart of the first processing module writing data to the sending FIFO in the embodiment of the application. As shown in FIG. 3 , the specific steps of the first processing module writing data to the sending FIFO are as follows:

S1: Wait for new data.

S2: Read the transmit control register to obtain the current transmit FIFO full mark, write pointer and read pointer.

S3: The software judges whether the current sending FIFO is full: if it is not full, it will jump to S5; if it is full, it will jump to S4 waiting state.

S4: Wait until the transmit FIFO is not full before jumping to S5.

S5: Calculate the available space of the transmit FIFO according to the current read/write pointer, and then calculate the amount of write data that can be written into the transmit FIFO this time according to the following formula.

Write data volume = Min [available space in the sending FIFO, the amount of data to be sent by the first processing module]

S6: Start from the write pointer of the transmit FIFO according to the calculation result of S5, and sequentially write the corresponding amount of data to the transmit FIFO.

S7: Update the write pointer of the sending control register according to the calculation result of S5, and then jump to S1 to continue the writing operation of the next sending FIFO.

It should be noted that, the control process for the first processing module to write data to the sending FIFO can be controlled and implemented by the first processing module, or can be controlled and implemented by the sending controller in FIG. 2 .

FIG. 4 is a schematic flowchart of the second processing module reading data from the transmission FIFO in the embodiment of the application. As shown in FIG. 4 , the workflow of the transmission controller is as follows:

S1: Wait until the transmit buffer is not full and the transmit FIFO is not empty.

Here, whether the transmit FIFO is not empty is indicated by the empty flag of the control register.

S2: Calculate the available space of the sending FIFO according to the current read/write pointer, and then calculate the amount of data that can be read from the sending FIFO this time according to the following formula;

Amount of read data = Min [Used space of transmit FIFO, free space of transmit buffer]

S3: The sending controller reads the data of the amount of read data calculated by S2 through the second bus to the sending buffer.

S4: Update the read pointer of the transmit FIFO, and then jump to S1 to continue the next read operation of the transmit FIFO.

With the above technical solution, the first processing module writes data to the sending FIFO through the first bus, the second processing module is connected to the sending buffer through the buffer general interface, and reads data from the sending FIFO through the sending buffer, thereby realizing a friendly interface. The cross-module data exchange reduces the bus burden. Further, by setting the control parameters in the register, the method realizes the function of high flexibility cross-module data exchange with variable FIFO depth.

The embodiment of the present application also provides a data receiving method. FIG. 5 is a schematic flowchart of the data receiving method in the embodiment of the present application. As shown in FIG. 5 , the method may specifically include:

Step 501: control the receiving buffer to receive the data of the second processing module;

Here, the second processing module is connected to the receiving buffer through the buffer general interface, and is used for writing data to the receiving buffer.

Step 502: Determine the write data volume of the receiving FIFO based on the control parameter of the receiving FIFO in the receiving control register;

Exemplarily, in some embodiments, the control parameters of the receiving FIFO include: a base address and depth of the memory space where the receiving FIFO is located, a write pointer, a read pointer, a full flag and an empty flag of the sending FIFO.

Exemplarily, in some embodiments, the method further includes: configuring the base address and depth of the memory space where the receive FIFO in the receive control register is located. Here, by configuring the base address and depth of the memory space where the receiving FIFO is located in the receiving control register, the FIFO depth can be flexibly set according to the usage scenario, the data interaction is not limited by the FIFO depth, and a highly flexible data interaction scheme is realized.

Exemplarily, in some embodiments, the determining the write data volume of the receiving FIFO based on the control parameter of the receiving FIFO in the receiving control register includes: the full flag in the receiving control register indicates that the receiving FIFO is full. is not full, and the receive buffer is not empty, determine the available space of the receive FIFO based on the read pointer and the write pointer of the receive FIFO; determine the write based on the available space of the receive FIFO The amount of data. Specifically, the used space of the receiving FIFO is obtained by subtracting the read pointer and the writing pointer of the receiving FIFO, and the available space is obtained by subtracting the total space of the receiving FIFO and the used space.

Here, when the full flag indicates that the receiving FIFO is not full, it indicates that the receiving FIFO indicates that the sending and receiving FIFO has available space for receiving data from the second processing module, and that the receiving buffer is not empty indicates that the receiving buffer contains the second processing module and sends it to the first processing module. module data. When these two conditions are satisfied at the same time, the first processing module receives the data of the second processing module by using the transmit FIFO and the transmit buffer.

Further, the amount of write data received and written into the receive FIFO is determined according to the available space of the receive FIFO, and the amount of write data does not exceed the amount of data that can be stored in the available space of the receive FIFO. Exemplarily, the amount of write data is the amount of data that can be stored in the available space of the receiving FIFO.

Exemplarily, in some embodiments, if the amount of written data is affected by the space of the receiving buffer, the method further includes: determining the used space of the receiving buffer; The available space of the FIFO, and determining the write data volume includes: determining a minimum space from the available space of the receiving FIFO and the used space of the receiving buffer; taking the data capacity corresponding to the minimum space as the write data capacity The amount of data. Here, the expression of the write data amount may be the write data amount=Min [receive FIFO free space, receive buffer used space].

Step 503: Based on the write data volume, write the data in the receive buffer into the receive FIFO through the second bus for the first processing module to read from the receive FIFO through the first bus Get the data of the second processing module.

Exemplarily, in some embodiments, after the data in the receive buffer is written into the receive FIFO through the second bus based on the amount of write data, the method further includes: updating the receive FIFO. receiving the write pointer of the receive FIFO in the control register.

Exemplarily, in some embodiments, the method further includes the first processing module reading data from the receive FIFO. Specifically, the empty flag in the receiving control register indicates that the receiving FIFO is not empty, and based on the read pointer and the write pointer of the receiving FIFO, the used space of the receiving FIFO is determined; based on the The used space of the receiving FIFO is determined, and the read data amount read by the first processing module from the receiving FIFO is determined; based on the read data amount, the first processing module is controlled to read from the receiving FIFO through the first bus data. Specifically, the used space of the receiving FIFO is obtained by subtracting the read pointer and the write pointer of the receiving FIFO.

Here, the amount of read data does not exceed the amount of data stored in the used space of the receive FIFO. Exemplarily, in some embodiments, the controlling the first processing module to read data from the receiving FIFO through the first bus based on the amount of read data includes: changing the used space of the receiving FIFO to The amount of stored data and the minimum amount of data allowed to be received by the first processing module is taken as the amount of read data of the receiving FIFO. For example, if the amount of data allowed to be received is less than the amount of data stored in the used space of the receiving FIFO, the amount of data allowed to be received will be taken as the amount of data read this time, and the amount of data allowed to be received is greater than or equal to the amount of data stored in the used space of the receiving FIFO, and the amount of data that is allowed to be received will be used The amount of data stored in the space is used as the amount of read data.

Exemplarily, in some embodiments, after the first processing module is controlled to read data from the receiving FIFO through the first bus based on the amount of read data, the method further includes: updating the receiving FIFO the read pointer of the receive FIFO in the control register.

In practical applications, the first processing module and the second processing module may be different modules in the same electronic device, or may be different modules in different electronic devices.

Exemplarily, in some embodiments, the first processing module is a software module, and the second processing module is a hardware module. Here, the hardware module uses a general FIFO interface (that is, the interface of the receiving buffer) to connect with the receiving buffer, writes the data sent to the software module into the receiving buffer, and then writes the data in the receiving buffer through the second bus. Receiving FIFO, the software module is connected to the receiving FIFO through the first bus, and is used to read data from the receiving FIFO, so that the hardware module does not need to change the original FIFO interface, that is, the general FIFO interface is used to access the receiving FIFO, so that the software module uses the bus interface to access Receive FIFO, so as to realize the exchange of buffered data across modules, which has good versatility.

The data sending method provided by the embodiment of the present application is implemented by a data receiving device. FIG. 6 is a schematic diagram of the composition and structure of the data receiving system in the embodiment of the present application. As shown in FIG. 6 , the data receiving system includes a software module, a receiving FIFO, and a data receiving device. And the hardware module, wherein, the data receiving device includes the following composition structure:

1. Receive control register: used to set the control parameters of the receive FIFO, including the base address (tx_fifo_base_addr) and depth (tx_depth) of the memory space where the receive FIFO is located, and the read and write pointers of the transmit FIFO (tx_rd_ptr (hw write) and tx_wr_ptr (sw write)), and empty full information (tx_full and tx_empty).

2. Receive controller: used to control the amount of data prefetched from the receive buffer, send a write request to the receive FIFO through the second bus, and update the write pointer after the write is completed.

3. Receive buffer: used to interface with the second processing module and the receiving controller, and buffer the data prefetched from the second module.

The hardware module is connected with the receiving buffer through a general interface, the receiving controller is connected with the receiving control register and the receiving buffer, and the receiving controller is connected with the receiving FIFO through the second bus, which is used to write the data in the receiving buffer into the receiving buffer. In the FIFO, the software module is connected to the receiving FIFO through the first bus, and is used for reading data from the receiving FIFO.

FIG. 7 is a schematic flowchart of the second processing module writing data to the receiving FIFO in the embodiment of the application. As shown in FIG. 7 , the working process of the receiving controller is as follows:

S1: Wait until the receive buffer is not empty and the receive FIFO is not full.

Here, whether the receive FIFO is not full is indicated by the full flag of the receive control register.

S2: Calculate the available space of the receiving FIFO according to the current read and write pointer, and then calculate the amount of data that can be written to the receiving FIFO this time according to the following formula;

Amount of write data = Min[free space of receive FIFO, used space of receive buffer]

S3: The receiving controller reads the data with the amount of write data calculated by S2 through the second bus and writes it into the receiving FIFO.

S4: Update the write pointer of the receiving FIFO, and then jump to S1 to continue the writing operation of the next receiving FIFO.

FIG. 8 is a schematic flowchart of the first processing module reading data from the receiving FIFO in the embodiment of the application. As shown in FIG. 8 , the specific steps of the first processing module reading data from the receiving FIFO are as follows:

S1: Wait for the receive FIFO to receive new data.

S2: Read the receive control register to obtain the empty flag, write pointer and read pointer of the current receive FIFO.

S3: The software judges whether the current receiving FIFO is empty; if it is not empty, it will jump to S5; if it is empty, it will jump to S4 waiting state.

S4: Wait until the receive FIFO is not empty and then jump to S5.

S5: Calculate the used space of the receiving FIFO according to the current read/write pointer, and then calculate the amount of read data that can be read from the receiving FIFO this time according to the following formula.

Amount of read data=Min[used space in receiving FIFO, amount of data allowed to be received by the first processing module]

S6: Start from the read pointer of the receiving FIFO according to the calculation result of S5, and sequentially read the corresponding amount of data.

S7: Update the read pointer of the receiving control register according to the calculation result of S5, and then jump to S1 to continue the read operation of the next receiving FIFO.

By adopting the above technical solution, the second processing module is connected to the receiving buffer through the buffer universal interface, writes data to the receiving FIFO through the receiving buffer, and the first processing module reads data from the receiving FIFO through the first bus, thereby realizing a friendly interface. The cross-module data exchange reduces the bus burden. Further, by setting the control parameters in the register, the method realizes the function of high flexibility cross-module data exchange with variable FIFO depth.

On the basis of the above embodiments, the data sending and receiving methods provided by the embodiments of the present application are further illustrated. In practical applications, the sending control register and the receiving control register are the same register group, and the sending FIFO and the receiving FIFO may be the same FIFO, which controls the sending and receiving process through the clock to avoid read and write conflicts.

FIG. 9 is a schematic structural diagram of a data sending and receiving system in an embodiment of the application. As shown in FIG. 9 , the data sending and receiving system includes a software module, a sending FIFO, a data sending and receiving device, and a hardware module, wherein the data sending and receiving The device is used to realize the data interaction between the software module and the hardware module. The operation of the software module to initialize the sending and receiving FIFO is the same as the above-mentioned method of initializing the sending FIFO and the receiving FIFO, that is, the base address and depth of the memory space where the FIFO is located; the sending control The work flow of the receiver is the same as that of the transmitting controller in the above data transmitting apparatus; the work flow of the receiving controller is the same as that of the receiving controller in the above data receiving apparatus.

The software module updates the write pointer (fifo_wr_ptr) of the transmit and receive FIFO when sending data, and the hardware module 1 updates the read pointer (fifo_rd_ptr) of the transmit and receive FIFO when receiving data. The hardware module 2 updates the write pointer (fifo_wr_ptr) of the transmit and receive FIFO when sending data, and the software module updates the read pointer (fifo_rd_ptr) of the transmit and receive FIFO when receiving data. The software module and the hardware module 2 will not update the write pointer at the same time, and the software module and the hardware module 1 will not update the read pointer at the same time, so as to avoid the conflict of updating the read and write pointers.

In Figure 9, the software module is used as the reference data flow, including the sending direction and the receiving direction. In practical applications, the software module and the hardware module only update one of the read and write pointers, and the software and hardware modules will not update the same pointer at the same time, to avoid the consistency caused by Sexual issues.

In some embodiments, the functions of the receive controller and the transmit controller may be implemented in a time-sharing manner by one controller, and the functions of the receive buffer and the transmit buffer may be implemented by a buffer in time-division.

In order to realize the data sending method of the embodiment of the present application, based on the same inventive concept, the embodiment of the present application also provides a data sending device. As shown in FIG. 10, the data sending device 100 includes: a sending control register 1001, a sending controller 1002 and a send buffer 1003;

The transmission control register 1001 is used to store the control parameters of the transmission FIFO; wherein, the first processing module writes the transmission data into the transmission FIFO through the first bus;

The transmit controller 1002 is configured to determine the read data volume of the transmit FIFO based on the control parameter of the transmit FIFO in the transmit control register; based on the read data volume, read data from the transmit FIFO through the second bus into the send buffer 1003;

The sending controller 1002 is further configured to control the sending buffer to send the data of the first processing module to the second processing module.

Exemplarily, in some embodiments, the control parameters of the transmit FIFO include: a base address and depth of a memory space where the transmit FIFO is located, a write pointer, a read pointer, a full flag and an empty flag of the transmit FIFO.

Exemplarily, in some embodiments, the sending controller 1002 is configured to use the empty flag in the sending control register to indicate that the sending FIFO is not empty and the sending buffer is not full, based on the value of the sending FIFO. The read pointer and the write pointer determine the used space of the transmit FIFO; and the read data amount is determined based on the used space of the transmit FIFO.

Exemplarily, in some embodiments, the sending controller 1002 is configured to determine the available space of the sending buffer; determine the minimum space from the used space of the sending FIFO and the available space of the sending buffer; The data capacity corresponding to the minimum space is used as the read data amount.

Exemplarily, in some embodiments, the transmit controller 1002 is configured to configure the base address and depth of the memory space where the transmit FIFO is located in the transmit control register.

Exemplarily, in some embodiments, the transmit controller 1002 is configured to update the transmit buffer after reading data from the transmit FIFO through the second bus to the transmit buffer based on the read data amount. the read pointer of the transmit FIFO in the control register.

Exemplarily, in some embodiments, the transmit controller 1002 is configured to use the full flag in the transmit control register to indicate that the transmit FIFO is not full, based on the read pointer and the write pointer of the transmit FIFO. , determine the available space of the transmit FIFO; based on the available space of the transmit FIFO, determine the amount of write data written into the transmit FIFO by the first processing module; based on the amount of write data, control the first processing The module writes the transmit data into the transmit FIFO through the first bus.

Exemplarily, in some embodiments, the sending controller 1002 is configured to, based on the write data amount, control the first processing module to write the sending data into the sending FIFO through the first bus after the , and update the write pointer of the transmit FIFO in the transmit control register.

Exemplarily, in some embodiments, the first processing module is a software module, and the second processing module is a hardware module. In this way, the hardware module does not need to access the sending FIFO through the bus, so that the hardware module does not need to change the original FIFO interface, that is, the general FIFO interface is used to access the sending FIFO, so that the software module uses the bus interface to access the sending FIFO, so as to realize the buffered data between the modules. Swap, has good versatility.

In order to realize the data receiving method of the embodiment of the present application, based on the same inventive concept, the embodiment of the present application also provides a data receiving apparatus. As shown in FIG. 11 , the data receiving apparatus 110 includes: a receiving control register 1101, a receiving controller 1102 and receive buffer 1103;

The receiving buffer 1103 is used for receiving data of the second processing module;

The receiving control register 1101 is used to store the control parameters of the receiving FIFO;

The receiving controller 1102 is configured to determine the write data volume of the receive FIFO based on the control parameter of the receive FIFO in the receive control register; based on the write data volume, send the data in the receive buffer through the second bus The data is written into the receiving FIFO for the first processing module to read the data of the second processing module from the receiving FIFO through the first bus.

Exemplarily, in some embodiments, the control parameters of the receiving FIFO include: a base address and depth of the memory space where the receiving FIFO is located, a write pointer, a read pointer, a full flag and an empty flag of the sending FIFO.

Exemplarily, in some embodiments, the receive controller 1102 is configured to use the full flag in the receive control register to indicate that the receive FIFO is not full and the receive buffer is not empty, based on the receive FIFO The read pointer and the write pointer determine the available space of the receiving FIFO; and based on the available space of the receiving FIFO, the write data amount is determined.

Exemplarily, in some embodiments, the receive controller 1102 is configured to determine the used space of the receive buffer; determine the minimum space from the available space of the receive FIFO and the used space of the receive buffer ; Take the data capacity corresponding to the minimum space as the write data amount.

Exemplarily, in some embodiments, the receiving controller 1102 is configured to configure the base address and depth of the memory space where the receiving FIFO in the receiving control register is located.

Exemplarily, in some embodiments, the receiving controller 1102 is configured to, after the data in the receiving buffer is written into the receiving FIFO through the second bus based on the amount of written data, update the received FIFO. the write pointer of the receive FIFO in the receive control register.

Exemplarily, in some embodiments, the receiving controller 1102 is configured to use the empty flag in the receiving control register to indicate that the receiving FIFO is not empty, based on the read pointer and the write pointer of the receiving FIFO , determine the used space of the receiving FIFO; based on the used space of the receiving FIFO, determine the read data volume of the receiving FIFO read by the first processing module; based on the read data volume, control the first processing module A processing module reads data from the receive FIFO through the first bus.

Exemplarily, in some embodiments, the receiving controller 1102 is configured to update the receiving FIFO after controlling the first processing module to read data from the receiving FIFO through the first bus based on the amount of read data. receiving the read pointer of the receive FIFO in the control register.

Exemplarily, in some embodiments, the first processing module is a software module, and the second processing module is a hardware module. In this way, the hardware module does not need to access the receiving FIFO through the bus, so that the hardware module does not need to change the original FIFO interface, that is, the general FIFO interface is used to access the receiving FIFO, so that the software module uses the bus interface to access the receiving FIFO, so as to realize cross-module buffer data Swap, has good versatility.

Based on the hardware implementation of each unit in the above data sending and receiving apparatus, the embodiment of the present application further provides an electronic device. As shown in FIG. 12 , the electronic device 120 includes: a processor 1201 and a processor memory 1202 for running computer programs;

Wherein, the processor 1201 is configured to execute the data sending method steps in the foregoing embodiments, or execute the data receiving method steps in the foregoing embodiments when running a computer program.

Of course, in practical application, as shown in FIG. 12 , various components in the electronic device are coupled together through a bus system 1203 . It can be understood that the bus system 1203 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 1203 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, the various buses are labeled as bus system 1203 in the figure.

In practical applications, the above-mentioned processor may be an application specific integrated circuit (ASIC, Application Specific Integrated Circuit), a digital signal processing device (DSPD, Digital Signal Processing Device), a programmable logic device (PLD, Programmable Logic Device), a field programmable gate At least one of an array (Field-Programmable Gate Array, FPGA), a controller, a microcontroller, and a microprocessor. It can be understood that, for different devices, the electronic device used to implement the above processor function may also be other, which is not specifically limited in the embodiment of the present application.

The above-mentioned memory can be a volatile memory (volatile memory), such as a random access memory (RAM, Random-Access Memory); or a non-volatile memory (non-volatile memory), such as a read-only memory (ROM, Read-Only Memory) Memory), flash memory (flash memory), hard disk (HDD, Hard Disk Drive) or solid-state drive (SSD, Solid-State Drive); or a combination of the above types of memory, and provide instructions and data to the processor.

In practical applications, the above-mentioned data sending apparatus and data receiving apparatus may be electronic equipment, and may also be chips applied in electronic equipment. In this application, the data sending device and the data receiving device can implement the functions of multiple units through software, or hardware, or a combination of software and hardware, so that the data sending device can execute any of the above-mentioned embodiments. For the provided data sending method and data receiving method, the technical effect of each technical solution of the data sending device can refer to the technical effect of the corresponding technical solution in the data sending method, and the technical effect of each technical solution of the data receiving device can refer to the data receiving method. The technical effects of the corresponding technical solutions in this application will not be repeated in this application.

In an exemplary embodiment, an embodiment of the present application further provides a computer-readable storage medium, such as a memory including a computer program, and the computer program can be executed by a processor of an electronic device to complete the steps of the foregoing method.

Embodiments of the present application also provide a computer program product, including computer program instructions.

Optionally, the computer program product can be applied to the electronic device in the embodiments of the present application, and the computer program instructions cause the computer to execute the corresponding processes implemented by the electronic device in the various methods of the embodiments of the present application. Repeat.

The embodiments of the present application also provide a computer program.

Optionally, the computer program can be applied to the electronic device in the embodiments of the present application. When the computer program runs on the computer, the computer executes the corresponding processes implemented by the electronic device in the various methods of the embodiments of the present application. For the sake of brevity. , and will not be repeated here.

It should be understood that the terminology used in the present application is for the purpose of describing particular embodiments only, and is not intended to limit the present application. As used in this application and the appended claims, the singular forms "a," "the," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the term "and/or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items. The expressions "having", "may have", "including" and "including", or "may include" and "may include" in this application may be used herein to indicate the presence of a corresponding feature (eg, such as a value, function, elements such as operations or components), but does not preclude the presence of additional features.

It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, such information should not be limited by these terms. These terms are only used to distinguish the same type of information from one another, and are not necessarily used to describe a particular order or sequence. For example, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information, without departing from the scope of the present invention.

The technical solutions described in the embodiments of the present application may be combined arbitrarily if there is no conflict.

In the several embodiments provided in this application, it should be understood that the disclosed method, apparatus and device may be implemented in other manners. The above-described embodiments are only illustrative. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined, or may be integrated into Another system, or some features can be ignored, or not implemented. In addition, the coupling, or direct coupling, or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical or other forms. of.

The unit described above as a separate component may or may not be physically separated, and the component displayed as a unit may or may not be a physical unit, that is, it may be located in one place or distributed to multiple network units; Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

In addition, each functional unit in each embodiment of the present application may all be integrated into one processing unit, or each unit may be separately used as a unit, or two or more units may be integrated into one unit; the above integration The unit can be implemented either in the form of hardware or in the form of hardware plus software functional units.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited to this. should be covered within the scope of protection of this application.

Claims (22)

1. a data sending method, is characterized in that, described method comprises: Determine the read data volume of the transmit FIFO based on the control parameter of the transmit FIFO in the transmit control register; wherein the first processing module writes the transmit data into the transmit FIFO through the first bus; Based on the amount of read data, read data from the transmit FIFO into the transmit buffer through the second bus; The sending buffer is controlled to send the data of the first processing module to the second processing module. 2. The method according to claim 1, wherein the control parameters of the transmit FIFO include: the base address and depth of the memory space where the transmit FIFO is located, a write pointer, a read pointer, and a full flag of the transmit FIFO and empty sign. 3. The method of claim 2, wherein Determining the read data amount of the transmit FIFO based on the control parameter of the transmit FIFO in the transmit control register includes: The empty flag in the transmit control register indicates that the transmit FIFO is not empty and the transmit buffer is not full, and based on the read pointer and the write pointer of the transmit FIFO, it is determined that the transmit FIFO is empty. use space; The read data amount is determined based on the used space of the transmit FIFO. 4. The method according to claim 3, wherein the method further comprises: determining the available space of the transmit buffer; The determining the read data amount based on the used space of the transmit FIFO includes: determining a minimum space from the used space of the transmit FIFO and the available space of the transmit buffer; The data capacity corresponding to the minimum space is used as the read data amount. 5. The method according to claim 2, wherein the method further comprises: Configure the base address and depth of the memory space where the transmit FIFO is located in the transmit control register. 6. The method according to claim 2, wherein after the data is read from the transmit FIFO into the transmit buffer through the second bus based on the amount of read data, the method further comprises: The read pointer of the transmit FIFO in the transmit control register is updated. 7. The method according to claim 2, wherein the method further comprises: The full flag in the transmit control register indicates that the transmit FIFO is not full, and the available space of the transmit FIFO is determined based on the read pointer and the write pointer of the transmit FIFO; determining, based on the available space of the transmit FIFO, the amount of write data written into the transmit FIFO by the first processing module; Based on the write data amount, the first processing module is controlled to write the transmit data into the transmit FIFO through the first bus. 8. The method according to claim 7, wherein after the first processing module is controlled to write the transmit data into the transmit FIFO through the first bus based on the amount of write data, the The method also includes: The write pointer of the transmit FIFO in the transmit control register is updated. 9 . The method according to claim 1 , wherein the first processing module is a software module, and the second processing module is a hardware module. 10 . 10. A data receiving method, characterized in that the method comprises: controlling the receiving buffer to receive the data of the second processing module; Determine the write data volume of the receiving FIFO based on the control parameter of the receiving FIFO in the receiving control register; Based on the write data amount, write the data in the receive buffer into the receive FIFO through the second bus, so that the first processing module can read the data from the receive FIFO through the first bus The data of the second processing module. 11. The method according to claim 10, wherein the control parameters of the receiving FIFO include: a base address and depth of the memory space where the receiving FIFO is located, a write pointer, a read pointer, and a full flag of the sending FIFO and empty sign. 12. The method of claim 11, wherein: The determining of the write data volume of the receiving FIFO based on the control parameters of the receiving FIFO in the receiving control register includes: The full flag in the receive control register indicates that the receive FIFO is not full and the receive buffer is not empty, and based on the read pointer and the write pointer of the receive FIFO, it is determined that the receive FIFO is available space; The write data amount is determined based on the available space of the receive FIFO. 13. The method of claim 12, wherein the method further comprises: determining the used space of the receive buffer; The determining the write data amount based on the available space of the receiving FIFO includes: determining a minimum space from the available space of the receive FIFO and the used space of the receive buffer; The data capacity corresponding to the minimum space is used as the write data amount. 14. The method of claim 11, wherein the method further comprises: Configure the base address and depth of the memory space where the receiving FIFO is located in the receiving control register. 15 . The method according to claim 11 , wherein after the data in the receiving buffer is written into the receiving FIFO through the second bus based on the write data amount, the method further 15 . include: The write pointer of the receive FIFO in the receive control register is updated. 16. The method of claim 11, wherein the method further comprises: The empty flag in the receiving control register indicates that the receiving FIFO is not empty, and the used space of the receiving FIFO is determined based on the read pointer and the write pointer of the receiving FIFO; determining, based on the used space of the receiving FIFO, the amount of data read from the receiving FIFO by the first processing module; Based on the amount of read data, the first processing module is controlled to read data from the receive FIFO through the first bus. 17. The method according to claim 16, wherein after the first processing module is controlled to read data from the receiving FIFO through the first bus based on the amount of read data, the method Also includes: The read pointer of the receive FIFO in the receive control register is updated. 18. The method according to any one of claims 10-17, wherein the first processing module is a software module, and the second processing module is a hardware module. 19. A data transmission device, characterized in that the data transmission device comprises: a transmission control register, a transmission controller and a transmission buffer; The transmission control register is used to store the control parameters of the transmission FIFO; wherein, the first processing module writes the transmission data into the transmission FIFO through the first bus; The transmission controller is configured to determine the read data volume of the transmission FIFO based on the control parameter of the transmission FIFO in the transmission control register; based on the read data volume, read data from the transmission FIFO through the second bus to in the send buffer; The sending controller is further configured to control the sending buffer to send the data of the first processing module to the second processing module. 20. A data receiving device, characterized in that the data receiving device comprises: a receiving control register, a receiving controller and a receiving buffer; the receiving buffer, for receiving data of the second processing module; The receiving control register is used to store the control parameters of the receiving FIFO; The receiving controller is configured to determine the write data amount of the receive FIFO based on the control parameter of the receive FIFO in the receive control register; based on the write data amount, write the data in the receive buffer through the second bus into the receiving FIFO for the first processing module to read the data of the second processing module from the receiving FIFO through the first bus. 21. An electronic device comprising: a processor and a memory configured to store a computer program executable on the processor, Wherein, the processor is configured to execute the steps of the data sending method described in any one of claims 1 to 9, or execute the steps of the data receiving method described in any one of claims 10 to 18 when running the computer program. 22. A computer-readable storage medium on which a computer program is stored, characterized in that, when the computer program is executed by a processor, the steps of the data sending method according to any one of claims 1 to 9 are realized, or the right The steps of any one of 10 to 18 of the data receiving method are required.

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