CN114530427A - Semiconductor packaging structure, preparation method thereof and electronic equipment - Google Patents
Semiconductor packaging structure, preparation method thereof and electronic equipment Download PDFInfo
- Publication number
- CN114530427A CN114530427A CN202210033389.4A CN202210033389A CN114530427A CN 114530427 A CN114530427 A CN 114530427A CN 202210033389 A CN202210033389 A CN 202210033389A CN 114530427 A CN114530427 A CN 114530427A
- Authority
- CN
- China
- Prior art keywords
- substrate
- layer
- electrode
- injection molding
- conductive support
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention relates to the technical field of semiconductors, and provides a semiconductor packaging structure, a preparation method thereof and electronic equipment, wherein the semiconductor packaging structure comprises: the device comprises a substrate, a device functional layer, a first electrode layer and a supporting layer, wherein the supporting layer is positioned on one side of the device functional layer, which is far away from the substrate, and covers the first electrode layer; the support layer includes an injection molded structure and a plurality of electrically conductive support structures. The support layer is prepared on the first electrode layer, and comprises an injection molding structure and a conductive support structure arranged in the injection molding structure, and the conductive support structure is used as an electric connection channel between the first electrode structure and the second electrode structure, so that the electrode structure is led out, and external leads are convenient to connect; meanwhile, the conductive support structure is combined with the injection molding structure, so that the structural strength of the wafer can be greatly improved, better mechanical support capability is provided for substrate thinning, the wafer can be prevented from warping or being damaged, the heat dissipation performance of a semiconductor packaging device can be improved after the substrate is thinned, and the service life of a product can be prolonged.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor packaging structure, a manufacturing method of the semiconductor packaging structure and electronic equipment.
Background
Power semiconductor devices, represented by gallium nitride, typically have a relatively thick substrate. Taking gallium nitride HEMT as an example, the gallium nitride based material is grown on a thicker silicon, sapphire or silicon carbide substrate. Silicon and sapphire substrates are preferred substrate materials for many applications due to their low cost. However, the thermal conductivity of the silicon substrate and the sapphire substrate is low, and the thermal conductivity of the sapphire substrate is particularly poor. Therefore, poor heat dissipation from the substrate has become a significant challenge in the fabrication of such devices.
An existing method for improving heat dissipation of a device is to reduce the thickness of a substrate, but when the substrate is thin, the mechanical strength of a wafer is extremely poor, and the warpage of the wafer is very large, which is very unfavorable for the subsequent process. Meanwhile, since there is a high stress in the substrate and the gallium nitride epitaxial layer, the wafer is very fragile and easily broken when the substrate is thin.
Disclosure of Invention
The invention aims to provide a semiconductor packaging structure, a preparation method thereof and electronic equipment, which are used for solving the problem that the conventional substrate thinning process is easy to cause wafer warpage or breakage.
In a first aspect, an embodiment of the present invention provides a semiconductor package structure, including: the device comprises a substrate, a device functional layer, a first electrode layer, a supporting layer and a second electrode layer. The device functional layer is positioned on one side of the substrate and comprises at least one semiconductor device; the first electrode layer is positioned on one side of the device functional layer, which is far away from the substrate, the region of the first electrode layer, which corresponds to the same semiconductor device, comprises a plurality of first electrode structures, and the first electrode structures are correspondingly connected with electrodes of the semiconductor device; the supporting layer is positioned on one side of the device functional layer far away from the substrate and covers the first electrode layer; the supporting layer comprises an injection molding structure and a plurality of conductive supporting structures positioned in the injection molding structure, one end of each conductive supporting structure is connected with the corresponding first electrode structure in the corresponding area, and the other end of each conductive supporting structure is flush with one side, far away from the substrate, of the injection molding structure; the second electrode layer is located on one side, far away from the substrate, of the supporting layer, the region, corresponding to the same semiconductor device, of the second electrode layer comprises a plurality of second electrode structures, and the second electrode structures are in one-to-one correspondence with the first electrode structures and connected with the conductive supporting structures.
In an alternative embodiment, the injection molded structure surrounds the electrically conductive support structure; the conductive support structure is a metal grid structure or a plurality of metal ball structures arranged at intervals.
In an alternative embodiment, the sum of the thickness of the substrate and the thickness of the support layer is 120 to 150 micrometers; and/or the thickness of the substrate is 0-100 microns.
In an alternative embodiment, the second electrode structure overlaps with an orthographic projection of the first electrode structure on the substrate.
In an alternative embodiment, a plurality of the metal ball structures are arranged at intervals in a linear array.
In an optional embodiment, nanoparticles are further dispersed in the injection-molded structure, and the material of the nanoparticles comprises silicon oxide, titanium oxide or silicon carbide.
In an alternative embodiment, the material of the injection molded structure comprises a resin material; and/or the material of the conductive support structure comprises tin.
In an optional embodiment, the semiconductor package structure further comprises: a back gold layer; the back gold layer is positioned on one side of the substrate far away from the device function layer and is used for being connected with the base island of the frame.
In a second aspect, embodiments of the present invention further provide an electronic device, including the semiconductor package structure according to the first aspect.
In a second aspect, an embodiment of the present invention further provides a method for manufacturing a semiconductor package structure, for manufacturing the semiconductor package structure according to the first aspect, including:
providing a substrate;
preparing a device functional layer on one side of the substrate; the device functional layer comprises at least one semiconductor device;
preparing a first electrode layer on one side of the device functional layer far away from the substrate; the region of the first electrode layer corresponding to the same semiconductor device comprises a plurality of first electrode structures;
preparing a conductive support structure on the side of the first electrode structure far away from the substrate;
injection molding a first electrode layer on one side of the substrate, wherein the first electrode layer is far away from the substrate, so that the injection molding structure surrounds the conductive support structure, and one end of the conductive support structure, which is far away from the substrate, is flush with one side of the injection molding structure, which is far away from the substrate;
thinning the substrate;
and preparing a second electrode structure on the side of the injection molding structure far away from the substrate.
Optionally, preparing a device functional layer on one side of the substrate; the device functional layer comprises at least one semiconductor device comprising:
removing part of the structure of the device function layer in the cutting path region to enable the adjacent semiconductor devices to be mutually independent;
and the injection molding structure is formed by injection molding on the side, away from the substrate, of the first electrode layer, so that the injection molding structure surrounds the conductive support structure, and one end, away from the substrate, of the conductive support structure is flush with the side, away from the substrate, of the support layer, and the injection molding structure comprises:
the injection structure covers the first electrode structure and the cutting path area.
The embodiment of the invention at least has the following technical effects:
according to the semiconductor packaging structure provided by the embodiment of the invention, the supporting layer is prepared on the first electrode layer, and the supporting layer comprises the injection molding structure and the conductive supporting structure arranged in the injection molding structure, so that the conductive supporting structure is used as an electric connection channel of the first electrode structure and the second electrode structure, the electrode structures are led out, and external leads are convenient to connect; meanwhile, the conductive support structure is combined with the injection molding structure, so that the structural strength of the wafer can be greatly improved, better mechanical support capability is provided for substrate thinning, the wafer can be prevented from warping or being damaged, the heat dissipation performance of a semiconductor packaging device can be improved after the substrate is thinned, and the service life of a product can be prolonged.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of a semiconductor package structure according to an embodiment of the present invention;
fig. 2 is a top view of a conductive support structure of a semiconductor package structure according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of another semiconductor package structure according to an embodiment of the present invention;
fig. 4 is a top view of another conductive support structure of a semiconductor package structure according to an embodiment of the present invention;
fig. 5 is a flowchart of a method for manufacturing a semiconductor package structure according to an embodiment of the present invention;
fig. 6 is a process structure diagram corresponding to step S200 in the method for manufacturing a semiconductor package structure according to the embodiment of the present invention;
fig. 7 is a process structure diagram corresponding to step S300 in the method for manufacturing a semiconductor package structure according to the embodiment of the invention;
fig. 8 is a process structure diagram corresponding to step S400 in the method for manufacturing a semiconductor package structure according to the embodiment of the present invention;
fig. 9 is a process structure diagram corresponding to step S500 in the method for manufacturing a semiconductor package structure according to the embodiment of the present invention;
fig. 10 is a process structure diagram corresponding to step S600 in the method for manufacturing a semiconductor package structure according to the embodiment of the invention;
fig. 11 is a process structure diagram corresponding to step S700 in the method for manufacturing a semiconductor package structure according to the embodiment of the present invention;
fig. 12 is a process structure diagram corresponding to the back gold layer preparation in the method for manufacturing a semiconductor package structure according to the embodiment of the present invention;
fig. 13 is a process structure diagram corresponding to the dicing of the wafer in the method for manufacturing the semiconductor package structure according to the embodiment of the invention;
fig. 14 is a process diagram corresponding to a mounting frame in a manufacturing method of a semiconductor package structure according to an embodiment of the invention;
fig. 15 is a process structure diagram corresponding to wire bonding in the method for manufacturing a semiconductor package structure according to the embodiment of the present invention;
fig. 16 is a process structure diagram corresponding to the secondary injection molding in the method for manufacturing a semiconductor package structure according to the embodiment of the present invention;
fig. 17 is a process structure diagram corresponding to the electroplated tin in the method for manufacturing the semiconductor package structure according to the embodiment of the invention;
fig. 18 is a process structure diagram corresponding to the package chip cutting in the method for manufacturing a semiconductor package structure according to the embodiment of the present invention.
Icon: 100-a substrate; 200-a device functional layer; 300-a first electrode layer; 310-a first electrode structure; 400-a support layer; 410-a conductive support structure; 420-injection molding structure; 421-nanoparticles; 500-a second electrode layer; 510-a second electrode structure; 600-back gold layer; 700-a frame; 800-plastic packaging structure; 900-welding layer.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the following embodiments, and it should be understood that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes all or any element and all combinations of one or more of the associated listed items.
Referring to fig. 1 and 2, an embodiment of the present invention provides a semiconductor package structure, including: a substrate 100, a device functional layer 200, a first electrode layer 300, a support layer 400, and a second electrode layer 500. Wherein the device functional layer 200 is located on one side of the substrate 100 and comprises at least one semiconductor device. The semiconductor device in this embodiment is a gallium nitride HEMT (high electron mobility transistor) or a schottky diode device.
Specifically, the first electrode layer 300 is located on a side of the device functional layer 200 away from the substrate 100, and a region of the first electrode layer 300 corresponding to the same semiconductor device includes a plurality of first electrode structures 310, and the first electrode structures 310 are correspondingly connected to electrodes of the semiconductor device. For example: the electrodes of the semiconductor device respectively include a source, a drain and a gate, three first electrode structures 310 corresponding to the semiconductor device (see three independent regions in fig. 2) are provided, the areas of the three first electrode structures 310 may be different, and the three first electrode structures are specifically designed according to the size and performance requirements of the semiconductor package structure. For convenience of description, in the present embodiment, the first electrode structure 310 corresponding to the source is taken as the first sub-electrode, the first electrode structure 310 corresponding to the drain is taken as the second sub-electrode, and the first electrode structure 310 corresponding to the gate is taken as the third sub-electrode.
Further, the supporting layer 400 in this embodiment is located on a side of the device function layer 200 away from the substrate 100, and the supporting layer 400 covers each first electrode structure 310 of the first electrode layer 300, so as to improve the mechanical performance and bending resistance of the entire semiconductor package structure, so as to facilitate the thinning of the substrate 100. The support layer 400 specifically includes an injection structure 420 and a plurality of conductive support structures 410 located inside the injection structure 420, one end of each conductive support structure 410 is connected to the corresponding first electrode structure 310, and the other end of each conductive support structure 410 is flush with a side of the injection structure 420 away from the substrate 100, and is configured to be electrically connected to the second electrode structure 510 included in the second electrode layer 500.
It should be noted that the second electrode layer 500 is located on a side of the supporting layer 400 away from the substrate 100, a region of the second electrode layer 500 corresponding to the same semiconductor device includes a plurality of second electrode structures 510, and the second electrode structures 510 are in one-to-one correspondence with the first electrode structures 310 and connected to an end of the conductive support structure 410 away from the substrate 100.
In the semiconductor package structure provided by this embodiment, the supporting layer 400 is prepared on the first electrode layer 300, and since the supporting layer 400 includes the injection structure 420 and the conductive supporting structure 410 disposed inside the injection structure 420, the conductive supporting structure 410 is used as an electrical connection channel between the first electrode structure 310 and the second electrode structure 510, so that the electrode structures are led out, and external lead connection is facilitated; meanwhile, the combination of the conductive support structure 410 and the injection structure 420 can greatly increase the structural strength of the wafer, thereby providing better mechanical support capability for thinning the substrate 100, preventing the wafer from warping or being damaged, being beneficial to improving the heat dissipation performance of the semiconductor packaging device after thinning the substrate 100, and prolonging the service life of the product.
In an alternative embodiment, with continued reference to fig. 1 and 2, the conductive support structure 410 in this embodiment comprises a metal mesh structure surrounded by a molded plastic structure 420.
Specifically, for the same semiconductor device, each first electrode structure 310 is provided with a metal grid structure, and the metal grid structure is prepared by combining electroplating with a patterning process, or is prepared by a printing process, wherein one end of the metal grid structure close to the substrate 100 is electrically connected with the first electrode structure 310.
Further, the injection structure 420 is prepared by an injection molding process, the material for preparing the injection structure 420 is filled in the peripheral gap of the metal grid structure (including the gap inside the grid structure and the gap outside the grid structure), and the surface of the metal grid structure away from the substrate 100 is flush with the surface of the injection structure 420 away from the substrate 100, so that the contact with the second electrode structure 510 can be conveniently conducted.
In this embodiment, the metal grid structure is used as the conductive support structure 410, so that the integrity of the support layer 400 is stronger, the structural strength and bending resistance of the entire support layer 400 are further improved, and the further thinning of the substrate 100 is facilitated.
Alternatively, as shown in fig. 3 and 4, the conductive support structure 410 in the present embodiment includes a plurality of metal ball structures arranged at intervals, and the injection molding structure 420 surrounds the plurality of metal ball structures.
Specifically, for the same semiconductor device, at least one metal ball structure is disposed on each first electrode structure 310, and the metal ball structure may be prepared by electroplating, ball-planting, die-bonding, or printing. Wherein, one end of the metal ball structure near the substrate 100 is electrically connected to the first electrode structure 310.
Further, the injection structure 420 is prepared by an injection molding process, and a material for preparing the injection structure 420 is filled in a peripheral gap of the metal ball structure, and a surface of the metal ball structure away from the substrate 100 is flush with a surface of the injection structure 420 away from the substrate 100, so that the metal ball structure can be conveniently contacted with the second electrode structure 510 for conducting electricity.
In this embodiment, the metal ball structure is used as the conductive support structure 410, and meanwhile, the combination between the spherical surface of the metal ball structure and the peripheral injection molding structure 420 is tighter, so that the integrity of the support layer 400 is stronger, the structural strength and the bending resistance of the whole support layer 400 are further improved, and the further thinning of the substrate 100 is facilitated.
In an alternative embodiment, the inventors have found through experiments that the overall thickness of the support layer 400 is different, and the thickness by which the corresponding substrate 100 can be thinned is also different. Specifically, when the sum of the thickness of the substrate 100 and the thickness of the supporting layer 400 is controlled to be 120 micrometers to 150 micrometers (including 120 micrometers and 150 micrometers), the overall thickness of the whole semiconductor package structure can be ensured, and meanwhile, the wafer with the thinned substrate 100 can be ensured not to warp.
Optionally, the thickness of the substrate 100 in this embodiment may be thinned to 0-100 micrometers (including 0-100 micrometers at the end), and compared to the thickness of the substrate 100 of the existing gan on silicon or gan on sapphire devices, which is generally over 150 micrometers, due to the structural design of the support layer 400, the substrate 100 in this embodiment greatly reduces the warpage of the wafer after thinning the substrate 100.
The following are exemplary: the minimum substrate 100 thickness ideally can be 0 micron (i.e. the substrate 100 is completely removed during the thinning process), when the substrate 100 thickness needs to be thinned to 0um, the thickness of the support layer 400 is larger than 130 microns according to experimental data; when the thickness of the substrate 100 needs to be thinned to 50 micrometers, the thickness of the support layer 400 needs to be greater than 80 micrometers; when the thickness of the substrate 100 needs to be thinned to 100 micrometers, the thickness of the support layer 400 needs to be more than 30 um; i.e., the thickness of the substrate 100 plus the thickness of the support layer 400, needs to be higher than a value (e.g., 130 microns) to ensure sufficient strength of the wafer.
In this embodiment, by strictly controlling the sum of the thicknesses of the substrate 100 and the supporting layer 400, the thickness of the supporting layer 400 can be prepared in advance according to the thickness of the substrate 100 to be thinned, so that the process flow is simplified and the thickness of the semiconductor package structure can be well controlled while ensuring that the wafer is not warped after the substrate 100 is thinned.
In an alternative embodiment, with continued reference to fig. 1, in the present embodiment, the plurality of second electrode structures 510 and the plurality of first electrode structures 310 are disposed in a one-to-one correspondence, and the orthographic projections on the substrate 100 overlap. Thus, for the electrode layer prepared by the patterning process, the first electrode layer 300 and the second electrode layer 500 can be prepared by the same mask plate, thereby saving the manufacturing cost.
Optionally, for the conductive support structure 410 being a plurality of metal ball structures, the plurality of metal ball structures are arranged in a linear array at intervals, which is beneficial to further increasing the structural strength of the support layer 400, and the manufacturing process can be simplified, so as to further reduce the manufacturing cost of the semiconductor package structure.
In an alternative embodiment, with continued reference to fig. 1, the injection molded structure 420 in this embodiment includes a plurality of nano-scale particles (i.e., nano-particles 421), and the nano-particles 421 are dispersed within the injection molded structure 420. Specifically, a certain amount of nanoparticles 421 may be pre-mixed in the injection molding material before forming injection molded structure 420, and after the injection molding material is formed into injection molded structure 420, nanoparticles 421 are dispersed in injection molded structure 420.
Alternatively, the material of the nanoparticles 421 includes silicon oxide, titanium oxide, or silicon carbide, and these nanoparticles 421 can effectively improve the mechanical strength of the injection-molded structure 420.
According to the semiconductor package structure provided by the embodiment, the injection structure 420 is doped with the nanoparticles 421 of a certain amount, so that the structural strength of the support layer 400 is further improved by the nanoparticles 421, the substrate 100 is thinned, and the thickness of the whole semiconductor package structure can be further reduced on the premise of ensuring the structural strength.
Optionally, the material (i.e., the injection molding material) of the injection molding structure 420 in this embodiment includes a resin material, and the resin material is a polymer insulating material, which can provide a better insulating property between the first electrode layer 300 and the second electrode layer 500 and between the conductive support structures 410, so as to avoid short circuit. The resin material is usually softened after being heated, has a flowing tendency under the action of external force and is convenient for injection molding; the injection structure 420 after the injection material is molded has good rigidity and toughness, which is convenient for improving the mechanical support performance of the wafer.
Optionally, the conductive support structure 410 provided in this embodiment is made of tin, and the tin material is used as the conductive support structure 410, so that on one hand, due to the better plasticity of the tin material, the conductive support structure is conveniently prepared by electroplating or printing, and different shapes and structures can be manufactured according to design requirements; on the other hand, since the tin material has better solderability, the connection between the conductive support structure 410 and the first electrode structure 310 and the second electrode structure 510 is tighter, and the stability of the whole semiconductor package structure is improved.
In an alternative embodiment, with continuing reference to fig. 1, the semiconductor package structure provided in this embodiment further includes: a back gold layer 600; the back gold layer 600 is located on the side of the substrate 100 remote from the device functional layer 200 for connection with the base islands of the frame 700. The back gold layer 600, the first electrode layer 300, and the second electrode layer 500 may be made of copper materials, the back gold layer 600 may facilitate the connection and fixation of the semiconductor device and the frame 700, and especially, the back gold layer 600 may play a role in protecting the device function layer 200 when the substrate 100 is thin or the substrate 100 is completely removed.
Based on the same inventive concept, an embodiment of the present invention further provides an electronic device, which includes the semiconductor package structure described above in the embodiment of the present invention, and the electronic device may be a mobile phone, a tablet computer, or a lighting device.
The electronic device provided by the embodiment comprises the semiconductor package structure in the foregoing embodiment, the semiconductor package structure is formed by preparing the support layer 400 on the first electrode layer 300, and since the support layer 400 comprises the injection molding structure 420 and the conductive support structure 410 disposed inside the injection molding structure 420, the conductive support structure 410 is used as an electrical connection channel between the first electrode structure 310 and the second electrode structure 510, so that the electrode structures are led out to facilitate external lead connection; meanwhile, the combination of the conductive support structure 410 and the injection molding structure 420 can greatly increase the structural strength of the wafer, thereby providing better mechanical support capability for thinning the substrate 100 and being beneficial to improving the heat dissipation performance of the semiconductor packaging device.
Based on the same inventive concept, as shown in fig. 5, an embodiment of the present invention further provides a method for manufacturing a semiconductor package structure, which is used for manufacturing the semiconductor package structure in the embodiment of the present invention, and includes the following steps:
s100, a substrate 100 is provided.
Alternatively, the substrate 100 may be a silicon substrate 100 or a sapphire substrate 100, depending on the semiconductor device to be fabricated.
S200, preparing a device function layer 200 on one side of the substrate 100; the device functional layer 200 includes at least one semiconductor device.
Alternatively, referring to fig. 6, two semiconductor devices are illustrated in this embodiment, and the semiconductor device in this embodiment may be a gallium nitride HEMT or a schottky diode device. The preparation method of the semiconductor device can refer to the preparation process of the existing gallium nitride semiconductor device.
S300, preparing a first electrode layer 300 on one side of the device functional layer 200 far away from the substrate 100; the region of the first electrode layer 300 corresponding to the same semiconductor device includes a plurality of first electrode structures 310.
Alternatively, referring to fig. 7, the method for preparing the first electrode layer 300 on the device functional layer 200 refers to the existing preparation process, and it is only necessary to ensure that each first electrode structure 310 corresponding to an electrode of a semiconductor device is an independent structure, so as to avoid short circuit or signal crosstalk between each first electrode structure 310.
S400, a conductive support structure 410 is fabricated on a side of the first electrode structure 310 away from the substrate 100.
Alternatively, referring to fig. 8, the conductive support structure 410 is prepared on each first electrode structure 310, and the preparation method of the conductive support structure 410 may be selected according to the shape and structural characteristics thereof, including but not limited to electroplating, printing, ball mounting or mounting.
S500, forming a mold structure 420 on a side of the first electrode layer 300 away from the substrate 100 by injection molding, so that the mold structure 420 surrounds the conductive support structure 410, and an end of the conductive support structure 410 away from the substrate 100 is flush with a side of the mold structure 420 away from the substrate 100.
Alternatively, referring to fig. 9, the device functional layer 200, the first electrode layer 300 and the conductive support layer 400 are injection molded such that an end of the conductive support structure 410 away from the substrate 100 is flush with a side of the injection molded structure 420 away from the substrate 100. Specifically, the thickness of the conductive support layer 400 may be controlled by strictly controlling the injection molding thickness, or the injection molding thickness may exceed the thickness of the conductive support layer, and then the polishing process may be performed.
S600, thinning the substrate 100.
Alternatively, referring to fig. 10, in this embodiment, the substrate 100 on the back side may be thinned by grinding, etching, or laser, and the remaining thickness of the thinned substrate 100 may be adjusted according to the design requirement of the semiconductor package structure.
S700, a second electrode structure 510 is prepared on a side of the injection structure 420 away from the substrate 100, with continued reference to fig. 11.
According to the method for manufacturing the semiconductor package structure provided by the embodiment, the supporting layer 400 is manufactured on the first electrode layer 300, and the supporting layer 400 includes the injection structure 420 and the conductive supporting structure 410 disposed inside the injection structure 420, and the conductive supporting structure 410 is used as an electrical connection channel between the first electrode structure 310 and the second electrode structure 510, so that the electrode structures are led out, and external lead connection is facilitated; meanwhile, the combination of the conductive support structure 410 and the injection molding structure 420 can greatly increase the structural strength of the wafer, thereby providing better mechanical support capability for thinning the substrate 100 and being beneficial to improving the heat dissipation performance of the semiconductor packaging device.
In an optional embodiment, based on the content of the foregoing embodiment, step S200 further includes:
and removing part of the structure of the device function layer 200 in the scribe line region, so that adjacent semiconductor devices are independent of each other.
And, step S500 further comprises:
the injection structure 420 covers the first electrode structure 310 and the scribe line region.
In this embodiment, by removing the device function layer 200 on the scribe line in advance, the stress between the substrate 100 and the epitaxial layer can be further reduced, and the gap between the semiconductor devices is filled by the injection structure 420, thereby playing roles of insulation and sealing protection.
Optionally, between step S600 and step S700, further comprising:
referring to fig. 12, a back gold layer 600 is fabricated on a side of the substrate 100 away from the device functional layer 200. The back gold layer 600 is located on the side of the substrate 100 remote from the device functional layer 200 for connection with the base islands of the frame 700.
Optionally, after step S700, the following steps are further included:
referring to fig. 13, the wafer is diced to form individual semiconductor package chips.
Referring to fig. 14, the diced semiconductor packaged chips are mounted on the base islands of the frame 700 by means of glue or sintering.
Referring to fig. 15, a wire bonding operation is performed to connect the second electrode structures 510 to be connected by using bonding wires.
Referring to fig. 16, the frame 700 is subjected to a second injection molding package to form a plastic package structure 800, so as to implement package protection of the entire device.
Referring to fig. 17, a solder layer 900 (the material of the solder layer 900 is generally metallic tin, and the solder layer can be prepared by electroplating process) is formed on the exposed leads for facilitating connection with external circuits.
Referring to fig. 18, the frame 700 having been subjected to the plastic encapsulation is cut and tested for shipment.
Those of skill in the art will appreciate that various operations, methods, steps in the processes, acts, or solutions discussed in the present application may be alternated, modified, combined, or deleted. Further, various operations, methods, steps in the flows, which have been discussed in the present application, may be interchanged, modified, rearranged, decomposed, combined, or eliminated. Further, steps, measures, schemes in the various operations, methods, procedures disclosed in the prior art and the present invention can also be alternated, changed, rearranged, decomposed, combined, or deleted.
In the description of the present invention, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention.
The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in a specific situation by those skilled in the art.
In the description herein, particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and may be performed in other orders unless explicitly stated herein. Moreover, at least a portion of the steps in the flow chart of the figure may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed alternately or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (11)
1. A semiconductor package structure, comprising:
a substrate;
a device functional layer on one side of the substrate comprising at least one semiconductor device;
the first electrode layer is positioned on one side, far away from the substrate, of the device function layer, the region, corresponding to the same semiconductor device, of the first electrode layer comprises a plurality of first electrode structures, and the first electrode structures are correspondingly connected with electrodes of the semiconductor device;
a support layer located on a side of the device functional layer remote from the substrate and covering the first electrode layer; the support layer comprises an injection molding structure and a plurality of conductive support structures positioned in the injection molding structure, one end of each conductive support structure is connected with the corresponding first electrode structure in the corresponding area, and the other end of each conductive support structure is flush with one side, far away from the substrate, of the injection molding structure;
the second electrode layer is positioned on one side, far away from the substrate, of the supporting layer, the region, corresponding to the same semiconductor device, of the second electrode layer comprises a plurality of second electrode structures, and the second electrode structures are in one-to-one correspondence with the first electrode structures and are connected with the conductive supporting structures.
2. The semiconductor package structure of claim 1, wherein the injection molded structure surrounds the conductive support structure; the conductive support structure is a metal grid structure or a plurality of metal ball structures arranged at intervals.
3. The semiconductor package structure of claim 1, wherein the sum of the thickness of the substrate and the thickness of the support layer is 120-150 microns; and/or the thickness of the substrate is 0-100 microns.
4. The semiconductor package structure of claim 1, wherein the second electrode structure overlaps an orthographic projection of the first electrode structure on the substrate.
5. The semiconductor package structure of claim 2, wherein the plurality of metal ball structures are spaced in a linear array.
6. The semiconductor package structure according to any one of claims 1 to 5, wherein nanoparticles are further dispersed inside the injection molded structure, and a material of the nanoparticles comprises silicon oxide, titanium oxide or silicon carbide.
7. The semiconductor package structure of claim 1, wherein the material of the injection molded structure comprises a resin material; and/or the material of the conductive support structure comprises tin.
8. The semiconductor package structure of claim 1, further comprising: a back gold layer; the back gold layer is positioned on one side of the substrate far away from the device function layer and is used for being connected with the base island of the frame.
9. An electronic device comprising the semiconductor package structure according to any one of claims 1 to 8.
10. A method for manufacturing a semiconductor package structure, for manufacturing the semiconductor package structure according to any one of claims 1 to 8, comprising:
providing a substrate;
preparing a device functional layer on one side of the substrate; the device functional layer comprises at least one semiconductor device;
preparing a first electrode layer on one side of the device functional layer far away from the substrate; the region of the first electrode layer corresponding to the same semiconductor device comprises a plurality of first electrode structures;
preparing a conductive support structure on the side of the first electrode structure far away from the substrate;
injection molding a first electrode layer on one side of the substrate, wherein the first electrode layer is far away from the substrate, so that the injection molding structure surrounds the conductive support structure, and one end of the conductive support structure, which is far away from the substrate, is flush with one side of the injection molding structure, which is far away from the substrate;
thinning the substrate;
and preparing a second electrode structure on the side of the injection molding structure far away from the substrate.
11. The method for manufacturing a semiconductor package structure according to claim 10, wherein a device function layer is manufactured on one side of the substrate; the device functional layer comprises at least one semiconductor device comprising:
removing part of the structure of the device function layer in the cutting path region to enable the adjacent semiconductor devices to be mutually independent;
and the injection molding structure is formed by injection molding on the side, away from the substrate, of the first electrode layer, so that the injection molding structure surrounds the conductive support structure, and one end, away from the substrate, of the conductive support structure is flush with the side, away from the substrate, of the support layer, and the injection molding structure comprises:
the injection structure covers the first electrode structure and the cutting path area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210033389.4A CN114530427A (en) | 2022-01-12 | 2022-01-12 | Semiconductor packaging structure, preparation method thereof and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210033389.4A CN114530427A (en) | 2022-01-12 | 2022-01-12 | Semiconductor packaging structure, preparation method thereof and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114530427A true CN114530427A (en) | 2022-05-24 |
Family
ID=81620398
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210033389.4A Pending CN114530427A (en) | 2022-01-12 | 2022-01-12 | Semiconductor packaging structure, preparation method thereof and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114530427A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103681377A (en) * | 2012-09-01 | 2014-03-26 | 万国半导体股份有限公司 | Semiconductor device with bottom metal base and preparing method thereof |
| CN112701049A (en) * | 2020-12-22 | 2021-04-23 | 杰群电子科技（东莞）有限公司 | Semiconductor module and packaging method thereof |
-
2022
- 2022-01-12 CN CN202210033389.4A patent/CN114530427A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103681377A (en) * | 2012-09-01 | 2014-03-26 | 万国半导体股份有限公司 | Semiconductor device with bottom metal base and preparing method thereof |
| CN112701049A (en) * | 2020-12-22 | 2021-04-23 | 杰群电子科技（东莞）有限公司 | Semiconductor module and packaging method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7242076B2 (en) | Packaged integrated circuit with MLP leadframe and method of making same | |
| JP5492367B2 (en) | Package for gallium nitride semiconductor devices | |
| US6410363B1 (en) | Semiconductor device and method of manufacturing same | |
| US11456265B2 (en) | Semiconductor device and method of manufacturing the same | |
| CN1188019C (en) | Die leadframe assembly and method of mounting leadframe onto semiconductor die | |
| TWI395277B (en) | Wafer level chip scale packaging | |
| US20110284997A1 (en) | Chip-Exposed Semiconductor Device and Its Packaging Method | |
| CN101964332A (en) | The semiconductor packages of chip-scale surface encapsulation and preparation process thereof | |
| US11264318B2 (en) | Semiconductor device, method for manufacturing the same, and semiconductor module | |
| US20210183799A1 (en) | Ultra-thin multichip power devices | |
| TW200931545A (en) | Integrated circuit package system with array of external interconnects | |
| JP3904934B2 (en) | Semiconductor device | |
| JP2009164288A (en) | Semiconductor element and semiconductor device | |
| CN114530427A (en) | Semiconductor packaging structure, preparation method thereof and electronic equipment | |
| JP3500015B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2000150543A (en) | Manufacture of semiconductor device | |
| JP4165952B2 (en) | Semiconductor device | |
| US20240170373A1 (en) | Semiconductor device | |
| EP4148777A1 (en) | Semiconductor device | |
| US20240282657A1 (en) | Semiconductor device | |
| US20240290679A1 (en) | Semiconductor device | |
| JP2007027654A (en) | Semiconductor device | |
| CN116741738A (en) | Cascade structure device and preparation process thereof | |
| JP2004022669A (en) | Semiconductor device and manufacturing method therefor | |
| JP2024036083A (en) | Semiconductor device and its manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20220524 |
|
| RJ01 | Rejection of invention patent application after publication |