CN114530174B

CN114530174B - Memory and memory system

Info

Publication number: CN114530174B
Application number: CN202210073679.1A
Authority: CN
Inventors: 刘峻
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2022-01-21
Filing date: 2022-01-21
Publication date: 2024-08-09
Anticipated expiration: 2042-01-21
Also published as: CN114530174A

Abstract

The embodiment of the application provides a memory and a storage system, wherein the memory comprises: a peripheral circuit; a memory area located at one side of the peripheral circuit; the storage area comprises a plurality of storage arrays and a first connection structure positioned between two adjacent storage arrays; wherein, both sides of the first connection structure respectively comprise a plurality of storage arrays; a main conductive line extending from the peripheral circuit to the first connection structure; two ends of the main electric wire are respectively connected with the peripheral circuit and the first connecting structure; at least two secondary conductive wires are respectively connected with the first connecting structure and extend in the directions of two sides of the first connecting structure, which are away from each other, so as to be connected with a plurality of corresponding storage arrays.

Description

Memory and memory system

Technical Field

The present application relates to the field of semiconductor technology, and in particular, to a memory and a memory system.

Background

The memory typically includes a memory area provided with a plurality of memory arrays and peripheral circuits. The memory array in the memory is mainly used for storing data, and the peripheral circuit is mainly used for controlling access operations of the memory array in the memory area, such as programming, reading or erasing operations, and providing electrical signals for the memory array in the memory area.

As semiconductor technology advances, the demand for memory capacity increases. When the storage capacity of the memory increases, the storage arrays disposed in the storage area thereof correspondingly increase, thereby placing higher demands on the performance of the memory.

Disclosure of Invention

In view of the above, the embodiments of the present application provide a memory and a memory system.

In a first aspect, an embodiment of the present application provides a memory, including:

A peripheral circuit;

A memory area located at one side of the peripheral circuit; the storage area comprises a plurality of storage arrays and a first connection structure positioned between two adjacent storage arrays; wherein, both sides of the first connection structure respectively comprise a plurality of storage arrays;

a main conductive line extending from the peripheral circuit to the first connection structure; two ends of the main electric wire are respectively connected with the peripheral circuit and the first connecting structure;

At least two secondary conductive wires are respectively connected with the first connecting structure and extend in the directions of two sides of the first connecting structure, which are away from each other, so as to be connected with a plurality of corresponding storage arrays.

In some embodiments, the number of storage arrays on both sides of the first connection structure is equal.

In some embodiments, the dominant wire is located at the first structural layer;

The secondary conductive line is located in a second structural layer different from the first structural layer;

the first connection structure communicates the first structural layer and the second structural layer.

In some embodiments, the first connection structure is a Via (Via) connecting the first structural layer and the second structural layer.

In some embodiments, the plurality of storage arrays are located at a third structural layer, the third structural layer being different from the first structural layer and different from the second structural layer; the memory further includes:

at least one second connection structure communicating the third structural layer and the second structural layer; the second connection structure connects the slave conductive line and the corresponding memory array.

In some embodiments, the memory array includes a plurality of row units sequentially arranged along a first direction; the storage arrays are sequentially arranged along the second direction; the first direction is perpendicular to the extending direction of the secondary conductive wire; the second direction is parallel to the extending direction of the secondary conductive wire; wherein,

A plurality of parallel secondary conductive wires are respectively connected to two sides of the first connecting structure;

The plurality of slave conductive wires are sequentially arranged in the first direction and are respectively connected with a plurality of row units positioned on the same straight line in the plurality of storage arrays.

In some embodiments, the row unit includes a plurality of memory blocks sequentially arranged along the second direction, and the memory further includes:

and the first-stage conductive branch lines are connected with the secondary conductive lines and are respectively connected with the storage blocks.

In some embodiments, the memory further comprises:

And the second-stage conductive branch lines are connected with the first-stage conductive branch lines and extend into the area range of the storage block along the second direction.

In some embodiments, the memory further comprises:

the power supply connection pad is positioned in the peripheral circuit and is used for being connected with a power supply; wherein the power connection pad is connected with the main electric wire.

In some embodiments, the width of the master wire is greater than the width of the slave conductive wire.

In addition, the embodiment of the application also provides a storage system, which comprises:

the memory as in the above embodiment;

and the controller is coupled with the memory and used for controlling the memory.

According to the memory provided by the embodiment of the application, the received electric signals can be transmitted between two adjacent memory arrays through the leading wires extending from the peripheral circuit to the first connecting structure, the distribution of the signals is realized on the first connecting structure, and the distributed electric signals are respectively transmitted to the memory arrays corresponding to the two sides of the first connecting structure through the leading wires connected with the first connecting structure. Therefore, on one hand, delay and voltage drop in the signal transmission process can be reduced, and the performance of the memory is effectively improved; on the other hand, when the storage capacity is increased, the wear among the storage arrays can be improved in a balanced manner, and the reliability of the memory can be improved.

Drawings

FIG. 1A is a schematic diagram illustrating a planar structure of a phase change memory according to an embodiment of the present application;

FIG. 1B is a schematic diagram of a phase change memory according to an embodiment of the present application;

FIG. 1C is a schematic diagram of a phase change memory according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a memory according to an embodiment of the application;

FIG. 3A is a schematic diagram of a second embodiment of a memory;

FIG. 3B is a schematic diagram III of a memory according to an embodiment of the present application;

FIG. 3C is a schematic diagram of a memory according to an embodiment of the present application;

FIG. 3D is a schematic diagram of a memory according to an embodiment of the present application;

FIG. 4A is a schematic diagram illustrating a portion of a memory array according to an embodiment of the present application;

FIG. 4B is a schematic diagram illustrating a portion of a memory array according to an embodiment of the present application;

FIG. 4C is a schematic diagram of a memory array according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a row unit according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a memory block according to an embodiment of the present application;

FIG. 7 is a fifth schematic diagram of a memory according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a semiconductor structure according to an embodiment of the present application;

fig. 9 is a schematic diagram of a storage system according to an embodiment of the present application.

Detailed Description

In order to facilitate understanding of the present application, exemplary embodiments of the present disclosure will be described in more detail below with reference to the associated drawings. While exemplary embodiments of the application are shown in the drawings, it should be understood that the application may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the application may be practiced without one or more of these details. In some embodiments, in order to avoid obscuring the present application, some technical features well known in the art are not described; that is, not all features of an actual implementation may be described in detail herein, nor are well-known functions and structures described in detail.

Generally, the term may be understood, at least in part, from the use of context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe a combination of features, structures, or characteristics in a plural sense, depending at least in part on the context. Similarly, terms such as "a" or "an" may also be understood to convey a singular usage or a plural usage, depending at least in part on the context. Additionally, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

Unless otherwise defined, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In order to provide a thorough understanding of the present application, detailed steps and detailed structures will be presented in the following description in order to explain the technical solution of the present application. Preferred embodiments of the present application are described in detail below, however, the present application may have other embodiments in addition to these detailed descriptions.

Referring to fig. 1A, a planar structure of a phase change memory is shown. Wherein a plurality of memory arrays 11 (i.e., bank0, bank1, bank2 … … BankN as shown in fig. 1A) are arranged centrally and sequentially in the memory area 10; peripheral circuitry 20 is disposed adjacent to memory region 10. It is to be noted that the memory area herein may be divided into an upper memory area 10a and a lower memory area 10b according to the memory capacity, and a corresponding memory array control unit (Bank Control Unit, BCU) 12 may be provided between the upper memory area 10a and the lower memory area 10 b.

Further, referring to FIG. 1B, an input/output (I/O) interface and corresponding power devices (e.g., pads) 21, data processing module 22, voltage processing module 23, regulator 24, redundancy module 25, oscillator 26, system logic control 27, one-time programmable memory (eFuse) 28, temperature sensor 29, or other electronic components, etc. may be included in peripheral circuitry 20. The I/O interface is used for receiving a control command from the external controller and controlling the memory to transmit data; the power device is used for receiving an electrical signal provided by an external power supply of the memory, and transmitting the electrical signal to a corresponding memory array in the memory according to a control command so as to drive the corresponding memory unit to perform related operations (such as programming, reading or erasing).

It will be appreciated that fig. 1B illustrates an alternative connection structure for related circuits or electronic components in the peripheral circuit 20, where the peripheral circuit 20 may further include additional peripheral circuits not illustrated in fig. 1B, and embodiments of the present application should not be limited thereto.

Referring to fig. 1C, in particular, when an external power supply applies an electrical signal to the memory, the peripheral circuit 20 may transfer the electrical signal to the memory area 10 through the plurality of wires 30. Illustratively, a plurality of conductors 30 extend from the peripheral circuitry 20 to each of the memory arrays 11 within the memory 10 for connection to the corresponding memory array 11. If the number of memory arrays 11 increases, the length of the conductive lines 30 increases, which in turn results in an increase in the voltage drop across the conductive lines 30, i.e., a larger power supply voltage drop (V-drop), which results in reduced memory performance. On the other hand, in the process of transmitting the signal to the corresponding memory cell through the conductive line 30, a corresponding resistance-capacitance (RC) delay is generated, and as the conductive line 30 grows, the corresponding RC delay of the memory array 11 further away from the peripheral circuit 20 increases, which further reduces the reliability of the memory.

As shown in fig. 2, an embodiment of the present application provides a memory 100, including:

a peripheral circuit 110;

A storage area 120 located at one side of the peripheral circuit 110; the storage area 120 includes a plurality of storage arrays 130 and a first connection structure 140 between two adjacent storage arrays 130; wherein, both sides of the first connection structure 140 respectively include a plurality of the memory arrays 130;

A main conductive line 150 extending from the peripheral circuit 110 to the first connection structure 140; two ends of the main conductive wire 150 are respectively connected to the peripheral circuit 110 and the first connection structure 140;

At least two secondary conductive wires 160 are respectively connected to the first connection structure 140, and extend in directions away from each other at two sides of the first connection structure 140, so as to connect to a corresponding plurality of the memory arrays 130.

It should be noted that fig. 2 is a schematic plan view of a Memory 100, where the Memory may be a common semiconductor Memory, such as a dynamic random access Memory (Dynamic Random Access Memory, DRAM), a NAND flash Memory (NAND FLASH Memory), or a phase change Memory. The memory according to the embodiments of the present application may be a phase change memory or a three-dimensional (3D) phase change memory, and it is understood that the memory 100 may be applied to other semiconductor memories, and the present application is not limited thereto.

In the embodiment of the present application, referring to fig. 2, the peripheral circuit 110 is arranged adjacent to the memory area 120 and in the same plane. The peripheral circuitry 110 herein may include any suitable analog, digital, and mixed signal circuitry, and in particular may include various types of electronic components formed using metal-oxide-semiconductor (MOS) technology, such as registers, oscillators, voltage regulators, drivers, or voltage/current generators, among others.

In some embodiments, embodiments of the present application may relate to a plurality of memories 100 stacked on one another to form a three-dimensional structure in order to increase the storage capacity of the memories. Therefore, the peripheral circuit 110 and the storage area 120 adjacently arranged in the embodiment of the application can facilitate wiring and reduce the process difficulty.

It will be appreciated that the peripheral circuit 110 shown in fig. 2 may be the peripheral circuit 20 shown in fig. 1A-1C, i.e., may also include I/O interfaces and power devices.

For example, referring to fig. 3A, the peripheral circuit 110 may be extended in the y-direction and receive control commands and electrical signals from the outside, which are transferred to the plurality of memory arrays 130 in the memory area 120 through the above-described I/O interface and power device. Here, the plurality of memory arrays 130 may be sequentially arranged in the x-direction within the memory region 120.

Further, the first connection structure 140 is located between two adjacent memory arrays 130, and divides the memory area 120 into a first memory area 120a and a second memory area 120b. The first storage area 120a and the second storage area 120b are respectively located at two sides of the first connection structure 140, and each may include a plurality of storage arrays 130. As shown in fig. 3A, the first storage region 120a may be located in a negative direction of the first connection structure 140 in the x-axis, and the second storage region 120b may be located in a positive direction of the first connection structure 140 in the x-axis. It is understood that the first storage area 120a may also be located in the positive direction of the x-axis of the first connection structure 140, and the second storage area 120b is located in the negative direction of the x-axis of the first connection structure 140.

It should be noted that, in practical applications, the number of storage arrays 130 in the first storage area 120a and the second storage area 120b may be the same or different, which is not limited in this disclosure.

The first connection structure 140 may be a wire having one input terminal and two output terminals, a shunt/voltage divider circuit, or other electronic components capable of distributing electrical signals; the electronic component may be an electronic component having a plurality of input terminals and a plurality of output terminals, which can distribute the electric signal. The first connection structure 140 is used for splitting signals of one or more main conductive wires 150 and providing the signals to corresponding auxiliary conductive wires 160 on two sides. It is understood that when the first connection structure 140 is a conductive structure, two memory arrays 130 adjacent to each other on both sides of the first connection structure 140 are electrically isolated from the first connection structure 140.

In the embodiment of the present application, referring to fig. 3A, the first connection structure 140 may be disposed at a corresponding position to the peripheral circuit 110, that is, also extended in the y-axis direction, so that the first storage region 120a and the second storage region 120b may be effectively separated to reduce electrical interference between the two regions. It should be emphasized that, in the drawings corresponding to the embodiments of the present application, the area occupied by the actual electronic component represented by the first connection structure 140 is not the outline and shape of the first connection structure 140.

Further, the embodiment of the present application may transmit the electrical signal received by the peripheral circuit 10 to the first connection structure 140 through the main conductive wire 150. Illustratively, the main conductive wire 150 may be a conductive wire with a large width, a small resistance, and a high transmission speed, so that the loss of the electrical signal during the transmission process may be effectively reduced. It should be emphasized that in the memory as in fig. 1C, the plurality of wires 30 cannot be too wide due to the limitation of the number of memory arrays and the memory capacity, or otherwise cause difficulty in wiring. On the other hand, the memory array 11 (e.g., bankN in fig. 1C) that is farther from the peripheral circuit 20 is also more affected by the rc delay and voltage drop.

In contrast, the main conductive line 150 in the embodiment of the present application may directly extend from the peripheral circuit 110 to the first connection structure 140, which may make the width of the main conductive line 150 larger than the conductive line 30 in fig. 1C and reduce the transmission loss in the memory array 130.

Further, the conductive lines 160 extending from both sides of the first connection structure 140 may finally transmit the electrical signals to the respective memory arrays 130 in the memory area 120. For example, referring to fig. 3A, an embodiment of the present application may have at least two slave conductive lines 160 disposed in the first and second memory regions 120a and 120b, respectively. Here, the conductive lines 160 extend in directions (for example, positive x-axis direction and negative x-axis direction in fig. 3A) away from each other at both sides of the first connection structure 140, respectively, and are electrically connected to the plurality of memory arrays 130 in the memory area where they are located.

In the embodiment of the present disclosure, the main conductive line 150 may be disposed at a different layer from the storage region 120 and the sub-conductive line 160, and may also be located at a blank region at the periphery of the memory array 130, so that low-impedance signal transmission may be realized in the form of a wider conductive line in a sufficient space.

In some embodiments, as shown with reference to FIG. 3B, a storage array control module 170 may also be included in the storage area 120. The memory array control module 170 herein may be the same as the memory array control unit 12 in fig. 1A to 1C. Illustratively, the memory array control module 170 is electrically connected to the peripheral circuit 110 to implement signal interaction, so that the peripheral circuit 110 provides control signals, such as programming or read/write signals, for each memory array 130 in the memory area 120 through the memory array control module 170.

In particular, the memory array control module 170 may include drivers, decoders, sense amplifiers, or other electronic components that control the memory array 130, etc.

In the memory 100 provided in the embodiment of the present application, the received electrical signals may be transferred between two adjacent memory arrays 130 through the main conductive wires 150 extending from the peripheral circuit 110 to the first connection structure 140, and the signals are distributed on the first connection structure 140, and then the distributed electrical signals may be transferred to the plurality of memory arrays 130 corresponding to the two sides of the first connection structure 140 through the sub conductive wires 160 connected to the first connection structure 140 and extending away from each other on the two sides of the first connection structure 140. Therefore, on one hand, delay and voltage drop in the signal transmission process can be reduced, and the performance of the memory is effectively improved; on the other hand, when the storage capacity is increased, the wear among the storage arrays can be improved in a balanced manner, and the reliability of the memory can be improved.

In some embodiments, referring to fig. 3C, the number of the memory arrays 130 on both sides of the first connection structure 140 is equal.

In an embodiment of the present application, the closer to the memory array 130 of the first connection structure 140, the smaller the loss of the electrical signal it receives. Correspondingly, the further away from the memory array 130 of the first connection structure 140, the more wires or electronic components are required to pass through during the transmission of the electrical signal, the greater the resistance-capacitance delay and voltage drop generated by the electrical signal, and the greater the influence on the access operation performed on the memory array 130.

Referring to fig. 3C, the memory area 120 at both sides of the first connection structure 140 may be divided into a first memory area 120a and a second memory area 120b. Here, the first memory area 120a has N memory arrays 130 therein, for example, bank0_a, bankn_a in fig. 3C, and a plurality of memory arrays 130 located between the two memory arrays. Similarly, the second storage area 120b may also have N storage arrays 130, for example, bank0_b, bankn_b in fig. 3C, and a plurality of storage arrays 130 located between the two storage arrays.

It is understood that the delay and voltage drop of the received electrical signals should be the same or not different for the two memory arrays 130 (e.g., bank0_a and bank0_b in fig. 3C) that are the same or not different from the first connection structure 140 in the first memory area 120a and the second memory area 120 b.

Therefore, in the embodiment of the present application, the number of the plurality of memory arrays 130 on both sides of the first connection structure 140 is equal, so that on one hand, the electrical signal loss of the memory array 130 on the side of the first connection structure 140 far from the peripheral circuit 110 is effectively reduced, and on the other hand, the resistance-capacitance delay and the voltage drop of the electrical signals received by the two memory arrays 130 respectively located at the corresponding positions of the conductive lines are substantially consistent, which is beneficial to the balanced improvement of the performance of the memory.

In some embodiments, FIG. 3D illustrates a cross-sectional view of storage area 120 along aa' in FIG. 3A. Specifically, referring to fig. 3D, the main conductor 150 is located in the first structural layer 210;

the secondary conductive line 160 is located in a second structural layer 220 different from the first structural layer 210;

The first connection structure 140 communicates the first structural layer 210 and the second structural layer 220.

In embodiments of the present application, the components in memory 100 may be located on different structural layers. Illustratively, the dominant wire 150 may be located in a first structural layer and the slave conductive wire 160 may be located in a second structural layer, where the first and second structural layers are stacked in a direction perpendicular to the memory array surface to separate the dominant wire 150 and the slave conductive wire 160 from each other.

Further, a first connection structure 140 may be provided that communicates the first and second structural layers. Here, the connection means electrical connection. In some embodiments, if the first structural layer is in direct contact with the second structural layer, the first connection structure 140 may partially penetrate the first structural layer and the second structural layer to electrically connect the master conductive line 150 and the slave conductive line 160. If the first structural layer and the second structural layer are not in direct contact, the first connection structure 140 may be disposed between the first structural layer and the second structural layer to connect the first structural layer and the second structural layer, thereby electrically connecting the master conductive line 150 and the slave conductive line 160.

It should be emphasized that the first and second structural layers may be solid structural layers including dielectric materials (e.g., silicon oxide or silicon nitride) and/or conductive materials (e.g., metal), or may be a spatial region representing the positional relationship of the components in the memory 100.

The plane corresponding to the first structural layer may be located above the plane corresponding to the second structural layer, or may be located below the plane corresponding to the second structural layer. Specifically, when the first structural layer is, for example, a top metal layer, the second structural layer may be a secondary metal layer, and the first structural layer and the second structural layer may be connected by a contact plug, a via hole or other interconnection structures, so that the width of the main conductive wire 500 may be increased as much as possible to reduce the transmission loss of the electrical signal.

In the embodiment of the present application, the main conductive wire 150 and the secondary conductive wire 160 are located on the planes corresponding to different structural layers, so that the difficulty of wiring and the interference between electrical signals can be reduced.

In some embodiments, the first connection structure 140 is a via that connects the first structural layer and the second structural layer.

In an embodiment of the present application, the main conductive line 150 and the sub conductive line 160 may be metal interconnection lines, and the first structural layer corresponding to the main conductive line 150 and the second structural layer corresponding to the sub conductive line 160 may be two different planes representing a spatial region.

Further, the first connection structure 140 may be a via directly connecting the main conductive line 150 and the secondary conductive line 160, and indirectly connecting the first structural layer and the second structural layer, so that the influence on the electrical signal can be reduced compared with other interconnection structures, and the heat dissipation performance is also better.

Specifically, one end of the via may be connected to the master conductive line 150, and the other end may be connected to at least two slave conductive lines 160, respectively, and distribute the electrical signal in the master conductive line 150 to at least two slave conductive lines 160. It can be appreciated that if the material and the length of the secondary conductive lines 160 connected to the via hole are the same as each other, the first connection structure 140 can uniformly distribute the electrical signal to the at least two secondary conductive lines 160.

The embodiment of the application adopts the via hole as the first connection structure 140, thereby reducing the process difficulty, reducing the signal loss and realizing the distribution of the electric signals efficiently and accurately.

In some embodiments, referring to fig. 3D, the plurality of memory arrays 130 are located in a third structural layer 230, the third structural layer 230 being different from the first structural layer 210 and different from the second structural layer 220; the memory 100 further includes:

At least one second connection structure 180 communicating the third structural layer 230 and the second structural layer 220; the second connection structure 180 connects the slave conductive line 160 and the corresponding memory array 130.

Illustratively, in embodiments of the present application, the plurality of memory arrays 130 may be located at different levels than the master electrical lines 150 and the slave electrical lines 160, i.e., the third structural layer 230 is different from the first structural layer 210 and different from the second structural layer 220.

Specifically, the first, second and third structural layers 210, 220 and 230 may be sequentially stacked in a direction perpendicular to the surface of the memory array 130. Here, the first structural layer 210 may be a top metal layer and is in communication with the second structural layer 220 through the first connection structure 140, i.e., the via; the second structural layer 220 may be an intermediate metal layer and communicates with the third structural layer 230 through the second connection structure 180 described above.

In an embodiment of the present application, the second connection structure 180 may be a contact plug or an interconnection line to connect the slave conductive line 160 located in the second structure layer 220 with the plurality of memory arrays 130. In this way, the structural layers located in different planes may allow for reduced electrical signal interference between the master conductive line 150, the slave conductive line 160, and the plurality of memory arrays 130, and facilitate routing.

In some embodiments, referring to fig. 4A to 4C, the memory array 130 includes a plurality of row units 131 sequentially arranged along a first direction D1; the plurality of storage arrays 130 are sequentially arranged along the second direction D2; the first direction D1 is perpendicular to the extending direction of the secondary conductive line 160; the second direction D2 is parallel to the extending direction of the secondary conductive line 160; wherein,

A plurality of parallel secondary conductive wires 160 are connected to two sides of the first connection structure 140;

The plurality of slave conductive lines 160 are sequentially arranged in the first direction D1 and are respectively connected to the plurality of row units 131 of the plurality of memory arrays 130 on the same line.

It should be noted that, in the embodiment of the present application, the first direction D1 in fig. 4A to 4C may be the y-axis direction in fig. 3A or 3B, and the second direction D2 may be the x-axis direction in fig. 3A or 3B.

Specifically, the plurality of row units 131 are sequentially arranged in the first direction D1, where two adjacent row units 131 may be spaced apart from each other to achieve electrical isolation. The plurality of memory arrays 130 are sequentially arranged in the second direction D2, where two adjacent memory arrays 130 may be spaced apart from each other to achieve electrical isolation.

In some embodiments, referring to fig. 4A, the row units 131 between adjacent memory arrays 130 may be in one-to-one correspondence, i.e., a plurality of row units 131 arranged in a predetermined order in the first direction D1 may be located on the same line.

In other embodiments, referring to fig. 4B, a storage array control module 170 may be included between the storage arrays 130 such that a plurality of row units 131 are sequentially arranged at both sides of the storage array control module 170, i.e., in a direction facing away from each other along the first direction D1. Similarly, a plurality of row units 131 arranged in a predetermined order between adjacent memory arrays 130 may be positioned on the same straight line.

Further, referring to fig. 4C, the plurality of slave conductive lines 160 are in one-to-one correspondence with the plurality of row units 131 on the same line sequentially arranged in the first direction D1, that is, the plurality of slave conductive lines 160 are also sequentially arranged in the first direction D1 and are respectively connected to the corresponding row units 131 in each memory array 130. Here, the plurality of slave conductive lines 160 may be parallel to each other.

It will be appreciated that fig. 4C is an enlarged partial schematic view of the memory area (i.e., the second memory area 120 b) on the side of the first connection structure 140 near the peripheral circuit 110 in fig. 3A, where a plurality of the areas extend from the conductive line 160 in the positive direction of the second direction D2. Similarly, for the memory area (i.e., the first memory area 120 a) located on the side of the first connection structure 140 away from the peripheral circuit 110 in fig. 3A, a plurality of the slave conductive lines 160 in this area should extend in the negative direction of the second direction D2. A similar arrangement is provided for the configuration of fig. 4B including the memory array control module 170, and the application is not so limited.

In some embodiments, referring to fig. 5, the row unit 131 includes a plurality of memory blocks 1310 sequentially arranged along the second direction D2, and the memory 100 further includes:

A plurality of first stage conductive branches 1311 connected to the slave conductive lines 160 and respectively connected to the plurality of memory blocks 1310.

It should be noted that fig. 5 is a partial enlarged view of a certain row of cells 131 based on fig. 4C, and the embodiment of the present application will be explained by taking three memory blocks 1310 as an example. It will be appreciated that the number of memory blocks 1310 in each row unit 131 needs to be determined according to the storage capacity of the memory in actual production.

For example, the memory blocks 1310 in the same row of cells 131 may be spaced apart from each other, wherein one memory Block 1310 may be referred to as a Block, and the memory Block 1310 may include a Word line driver 1312 (Word LINE DRIVER), a Bit line driver 1313 (Bit LINE DRIVER), and other circuit structures or electronic components. In an embodiment of the present application, each memory block 1310 may have at least one first-stage conductive branch 1311 corresponding to the first-stage conductive branch 1311, so as to extend from the conductive line 160 to the first direction D1, so as to electrically connect with the memory block 1310.

In some embodiments, referring to fig. 6, the memory 100 further includes:

A plurality of second level conductive branches 1314 are connected to the first level conductive branch 1311 and extend along the second direction D2 into the area of the memory block 1310.

It should be noted that fig. 6 is a partial enlarged view of a certain memory block 1310 based on fig. 5.

For example, a three-dimensional phase change memory is taken as an example, the three-dimensional phase change memory is provided with a plurality of layers of memory cells which are stacked up and down, a word line can be shared between two memory cells which are adjacent up and down, a lower layer of memory cells is coupled to a lower layer of bit lines, and an upper layer of memory cells is coupled to an upper layer of bit lines. In addition, the bit line driver 1313 may include an upper bit line selector 1313a and a lower bit line selector 1313b.

Specifically, the first level conductive leg 1311 in fig. 6 connects the slave conductive line 160 and the corresponding memory block 1310, and a plurality of second level conductive legs 1314 may be connected to the first level conductive leg 1311. Referring to fig. 6, a second level conductive leg 1314 may connect to a first level conductive leg 1311 and a word line driver in memory block 1310 and provide a word line signal to the word line. Two other second level conductive legs 1314 may connect first level conductive leg 1311 to the upper and lower level bit line selectors 1313a and 1311 and 1313b, respectively, and provide bit line signals to the upper and lower level bit lines.

In some embodiments, the memory block includes a plurality of word lines parallel to each other and sequentially spaced apart in the first direction, the memory further including:

a plurality of third level conductive legs connected to the second level conductive legs 1314 and respectively connected to the plurality of word lines.

Illustratively, a plurality of memory cells in the memory block 1310 in an embodiment of the present application may be sequentially arranged in a row direction (e.g., the first direction D1) and a column direction (e.g., the second direction D2), thereby forming a memory cell array. The memory cell array and the word line driver, bit line driver, and circuit structure or electronic components described above constitute the memory block 1310. In addition, since the plurality of memory cells in the same line, i.e., the same row or the same column direction are connected to the same word line, the plurality of word lines may be sequentially spaced apart in the first direction D1 or the second direction D2 and parallel to each other in the memory cell array.

Further, as shown in connection with fig. 5 and 6, one of the second stage conductive legs 1314 connects the first stage conductive leg 1311 and the word line driver 1312 in the second direction D2 on the basis that the first stage conductive leg 1311 extends in the first direction D1. Further, the word line driver 1312 is connected to a plurality of third stage conductive branches (not shown) and transfers the word line signals to corresponding word lines according to external control signals.

It should be noted that, the plurality of second-stage conductive branches and the first-stage conductive branches, and the plurality of third-stage conductive branches and the second-stage conductive branches may be connected by interconnecting lines or vias. In addition, the extending direction of the plurality of third-level conductive branches needs to be determined according to the word line direction in the actual memory cell array.

It will be appreciated that in other embodiments, the bit line driver may be connected to a plurality of fourth stage conductive branches to respectively connect a plurality of bit lines in the memory cell array, and the application is not limited thereto.

In embodiments of the present application, electrical signals may be distributed efficiently and quickly and routing difficulties may be reduced by leading wire 150, trailing wire 160, first stage conductive leg 1311, second stage conductive leg 1314, and other conductive legs.

In some embodiments, as shown in fig. 7, the memory 100 further comprises:

A power connection pad 111 located in the peripheral circuit 110 for connection with a supplied power; wherein the power connection pad 111 is connected to the main electric wire 150.

The power connection pad 111 according to the embodiment of the present application may be a pad or other electronic component electrically connected to an external power supply. Illustratively, the power connection pad 111 may include an input interface thereon to introduce an electrical signal provided by a power supply into the memory 100, and an output interface to provide the electrical signal to the electronic components (e.g., oscillator or voltage regulator, etc.) and the main conductor 150 in the peripheral circuit 110.

Specifically, referring to fig. 7, one end of the main conductive wire 150 is correspondingly connected to the output interface of the power connection pad 111 and extends in the x-axis negative direction to connect the first connection structure 140. It will be appreciated that the power connection pad 111 in fig. 7 may be identical to the power device 21 in fig. 1B, and the application is not so limited.

In some embodiments, the width of the master electrical wire 150 is greater than the width of the slave electrical wire 160.

In the embodiment of the present application, the main conductive line 150 connects the peripheral circuit 110 and the first connection structure 140, and may be configured as a conductive line having a large width, thereby reducing resistance and transmission loss. On the other hand, since the slave conductive lines 160 need to be connected to the plurality of memory arrays 130 and may have a plurality of lines, the width thereof may be smaller than that of the master conductive line 150 to reduce electrical interference between the slave conductive lines 160 and to reduce wiring difficulty.

Referring to fig. 8, an embodiment of the present application further provides a semiconductor structure 1000, where the semiconductor structure 1000 includes:

A substrate 1100;

The memory 100 of the above embodiment is located on the substrate 1100.

In embodiments of the application, the substrate 1100 may include, but is not limited to, a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon-on-insulator (Silicon on Insulator, SOI) substrate, or a germanium-on-insulator (Germanium on Insulator, GOI) substrate, etc., and the substrate 1100 may be P-doped or N-doped.

In some embodiments, an isolation layer may be provided over the substrate 1100 for protecting the substrate 1100, where the isolation layer may be composed of a single layer film or a multi-layer film. Illustratively, the isolation layer may include a silicon oxide layer, a silicon nitride layer, which are stacked in order from bottom to top over the substrate 1100. In other embodiments, the number of layers and the materials of the layers of the isolation layer may be adjusted according to practical requirements, which is not limited in this disclosure.

Further, the memory 100 may be formed on the substrate 1100 by deposition, where the deposition process may include one or more of chemical vapor deposition (Chemical Vapor Deposition, CVD), atomic layer deposition (Atomic Layer Deposition, ALD), physical vapor deposition (Physical Vapor Deposition, PVD), or the like.

Therefore, the semiconductor structure 1000 provided in the embodiment of the application can reduce delay and voltage drop in the signal transmission process through the memory 100 on the substrate 1100, effectively improve the performance of the semiconductor structure 1000, and can balance and improve the loss between each memory array in the semiconductor structure 1000 and improve the reliability of the semiconductor structure 1000 when the memory capacity of the semiconductor structure 1000 is increased.

In addition, referring to fig. 9, an embodiment of the present application further provides a storage system 2000, where the storage system 2000 includes:

the memory 100 as described in the above embodiment;

A controller 2100 is coupled to the memory 100 for controlling the memory 100.

In an embodiment of the present application, the controller 2100 may be coupled with the memory 100 through a plurality of interfaces, and may control operations of reading, erasing, programming, and the like of the memory 100.

By way of example, the controller 2100 may be designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, compact Flash (CF) card, universal Serial Bus (USB) flash drive, or other medium for use in electronic devices such as personal computers, digital cameras, mobile phones, and the like. In some embodiments, the controller 2100 may also be designed to operate in a high duty cycle environment SSD or embedded multimedia card (eMMC), which serves as a data storage and enterprise storage array for mobile devices such as smartphones, tablet computers, laptop computers, and the like. Further, the controller 2100 may also be configured to manage various functions with respect to data stored or to be stored in the memory 100, including, but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, and the like; and may also be configured to process Error Correction Codes (ECC) with respect to data read from or written to memory 100. In addition, the controller 2100 may perform any other suitable function, such as formatting the memory 100, or communicating with external devices (e.g., hosts) according to a particular communication protocol. Illustratively, the controller 2100 may communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and the like.

It should be noted that the features disclosed in the several method or apparatus embodiments provided in the present application may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A memory, comprising:

A peripheral circuit;

a main conductive line extending from the peripheral circuit to the first connection structure; two ends of the main electric wire are respectively connected with the peripheral circuit and the first connecting structure; the main electric wire is positioned on the first structural layer;

At least two secondary conductive wires are respectively connected with the first connecting structure and extend in the direction of deviating from each other at two sides of the first connecting structure to be connected with a plurality of corresponding storage arrays; the secondary conductive line is located in a second structural layer different from the first structural layer; the first connection structure communicates the first structural layer and the second structural layer.

2. The memory of claim 1, wherein the number of memory arrays on both sides of the first connection structure is equal.

3. The memory of claim 1, wherein the first connection structure is a via connecting the first structural layer and the second structural layer.

4. The memory of claim 1, wherein the plurality of memory arrays are located at a third structural layer, the third structural layer being different from the first structural layer and different from the second structural layer; the memory further includes:

5. The memory of claim 1, wherein the memory array comprises a plurality of row units arranged sequentially along a first direction; the storage arrays are sequentially arranged along the second direction; the first direction is perpendicular to the extending direction of the secondary conductive wire; the second direction is parallel to the extending direction of the secondary conductive wire; wherein,

the secondary conductive wires are sequentially arranged in the first direction and are respectively connected with the row units which are positioned on the same straight line in the storage arrays.

6. The memory of claim 5, wherein the row unit includes a plurality of memory blocks arranged sequentially along the second direction, the memory further comprising:

7. The memory according to claim 6, characterized in that the memory further comprises:

8. The memory of claim 1, wherein the memory further comprises:

9. The memory of any of claims 1-8, wherein a width of the master wire is greater than a width of the slave wire.

10. A storage system, comprising:

a memory as claimed in any one of claims 1 to 9;