CN114513201A - GaN transistor drive circuit - Google Patents

Abstract

The invention relates to a GaN transistor driving circuit. The GaN transistor driving circuit is used for a driven GaN transistor and comprises an upper tube circuit, a lower tube circuit and an upper tube and lower tube control circuit, wherein the upper tube circuit and the lower tube circuit comprise upper tubes and lower tubes, the upper tubes and the lower tubes are all GaN transistors, drain electrodes of the upper tubes are connected with a power supply voltage VCC, grid electrodes of the upper tubes are connected with a digital input VIN, and source electrodes of the upper tubes are connected with drain electrodes of the lower tubes and serve as output of the GaN transistor driving circuit to be connected with grid electrodes of the driven GaN transistors; the grid of the lower tube is connected with an upper tube control circuit and a lower tube control circuit; this upper and lower pipe control circuit utilizes busbar voltage VD, mains voltage VCC and digital input VIN, right the low tube is controlled to make GaN transistor drive circuit's output and digital input VIN are homophase, upper and lower pipe control circuit includes the transistor to the transistor that includes is the GaN transistor, switches on when the grid is applyed the voltage that is higher than threshold voltage.

Description

A GaN transistor driver circuit

technical field

The present invention relates to GaN transistors, and in particular, to a GaN transistor driving circuit.

Background technique

With the rapid development of power electronic systems, the power semiconductor device market has developed rapidly. The performance of silicon-based devices has gradually reached the theoretical limit of the material, and it is increasingly unable to meet the needs of modern high-power power electronic systems. In this case, the third-generation wide-bandgap semiconductors represented by GaN and SiC have gradually replaced Si materials and become the first choice for device design in high-temperature and high-frequency environments.

The gate driver of existing Si devices is not suitable for driving GaN devices, which is mainly manifested in the low gate driving voltage (6V) of enhancement mode GaN transistors, and the difference between the gate breakdown voltage and the full turn-on voltage is also very low (3V). Conventional gate drivers using SiMOSFETs to generate gate voltages, although effective for most Si MOSFET devices, cannot provide low-voltage gate voltages for GaN devices. Not only that, the existing driver is manufactured using a Si process that is incompatible with GaN, which increases the inductance of the gate loop. Since the turn-on speed of the GaN device is in nanoseconds, the dV/dt of the power loop is generally greater than 100V/ns. This can cause huge oscillations induced in the gate loop. Therefore, using a traditional gate driver to directly drive a GaN device may not only cause device breakdown, which will make the system fail, but also introduce circuit oscillations that affect system efficiency.

On the other hand, although the fully integrated GaN driver in the prior art can effectively drive the main GaN device to work normally, the internal structure of the driver is often complicated, and the turn-on and turn-off delays are relatively long.

SUMMARY OF THE INVENTION

The present invention is made in view of the above situation in the prior art, is used to overcome or alleviate one or more technical problems existing in the prior art, and at least provides one beneficial option.

According to an aspect of the present invention, a GaN transistor drive circuit is provided, the GaN transistor drive circuit includes an upper and lower tube circuit and an upper and lower tube control circuit, and the upper and lower tube circuits include an upper tube and a lower tube. The upper tube and the The lower tubes are all GaN transistors, the drain of the upper tube is connected to the power supply voltage, the gate of the upper tube is connected to the digital input, the source of the upper tube is connected to the drain of the lower tube, and is used as a The output of the GaN transistor driving circuit is connected to the gate of the driven GaN transistor; the gate of the lower tube is connected to the upper and lower tube control circuits; the upper and lower tube control circuits use the working voltage, power supply voltage and The digital input controls the lower tube, so that the output of the GaN transistor drive circuit is in phase with the digital input. The upper and lower tube control circuits include transistors, and the included transistors are all GaN transistors, which are applied at the gate Turns on at voltages above the threshold voltage.

According to the embodiment of the present invention, the structure of the driving circuit is simple and the delay is short.

According to some embodiments of the present invention, the GaN transistor driving circuit and the GaN power device are integrated in a single chip, which can reduce the volume of the system and reduce power consumption.

Description of drawings

The present invention can be better understood in conjunction with the accompanying drawings, in which:

1 is a schematic diagram of a GaN transistor driving circuit according to an embodiment of the present invention;

FIG. 2 shows a schematic diagram of a GaN transistor driving circuit according to another embodiment of the present invention;

Fig. 3 shows the input and output waveforms according to the embodiment shown in Fig. 4;

FIG. 4 shows a schematic diagram of a GaN transistor driving circuit according to yet another embodiment of the present invention; and

FIG. 5 shows input and output waveforms according to the embodiment shown in FIG. 4 .

Detailed ways

FIG. 1 is a schematic diagram of a GaN transistor driving circuit according to an embodiment of the present invention. As shown in FIG. 1, a GaN transistor driving circuit 1 according to an embodiment of the present invention is used to drive a driven GaN transistor Q1, the drain of the driven GaN transistor Q1 is connected to the bus voltage VD, and the source is connected to the ground. connect. The GaN transistor driving circuit 1 includes an upper and lower tube circuit 10 and an upper and lower tube control circuit 20 . The upper and lower transistor circuit 10 includes an upper transistor Q5 and a lower transistor Q6, both of which are GaN transistors, specifically, enhancement-mode GaN high electron mobility transistors (HEMTs), which are applied to a gate higher than a threshold value Turns on when the voltage is high. It should be understood by those skilled in the art that, in the present invention, any voltage higher than the threshold voltage of the transistor can be referred to as a high voltage, otherwise, it can be referred to as a low voltage. According to an embodiment of the present invention, the bus voltage VD may be a high voltage of 100V-650V, the power supply voltage VCC may be 6V, the logic high level of the digital input VIN is 12V, and the logic low level is 0V. Therefore, both the power supply voltage VCC and the logic high level of the digital input VIN are high voltages.

The drain of the upper tube Q5 is connected to the power supply voltage VCC, the gate is connected to the digital input VIN, and the source is connected to the drain of the lower tube Q6, and is used as the output of the GaN transistor driving circuit 1 and the gate of the driven GaN transistor Q1. extremely connected. The gate of the lower tube Q6 is connected to the upper and lower tube control circuit 20 . The upper and lower transistors control circuit 20 uses the bus voltage VD, the power supply voltage VCC and the digital input VIN to control the lower transistors so that the output of the GaN transistor driving circuit is in phase with the digital input VIN. The upper and lower tube control circuit 20 includes transistors, and the included transistors are all GaN transistors, which are turned on when a voltage higher than a threshold voltage is applied to the gate.

According to this embodiment, the transistors used in the upper and lower tube circuit 10 and the upper and lower tube control circuit 20 are all GaN transistors, and the functions are simple, so the entire circuit structure is simple and the delay is short.

FIG. 2 shows a schematic diagram of a GaN transistor driving circuit according to an embodiment of the present invention. 1, the upper and lower tube control circuit 20 includes a first transistor Q3, a second transistor Q4 and a third transistor Q2.

The drain of the first transistor Q3 is connected to the source of the third transistor Q2 and the gate of the lower transistor Q6, the gate of the first transistor Q3 is connected to the source of the second transistor Q4, the first transistor Q3 The source is grounded.

The drain of the second transistor Q4 is connected to the digital input VIN, the gate of the second transistor Q4 is connected to the power supply voltage VCC, and the source of the second transistor Q4 is connected to the gate of the first transistor Q3.

The drain of the third transistor Q2 is connected to the working voltage VD, the gate of the third transistor Q2 is connected to the drain of the lower transistor Q6 and the source of the upper transistor Q5, and the source of the third transistor Q2 is connected to the drain of the first transistor Q3 extremely connected.

When VIN is a high voltage, the upper transistor Q5 is turned on. Meanwhile, since the second transistor Q4 is in a normally-on state, VIN is applied to the gate of the first transistor Q3 through the second transistor Q4, so that the first transistor Q3 is turned on. In this way, a low voltage is applied to the gate of the lower tube Q6, so that the lower tube Q6 is turned off. As described above, the upper transistor Q5 is turned on and the lower transistor Q6 is turned off, and the transistor Q2 is turned on, so that a high voltage is applied to the gate of the driven GaN transistor Q1. When VIN is low voltage, the upper transistor Q5 is turned off. At the same time, since the second transistor Q4 is in a normally-on state, the low voltage VIN is applied to the gate of the first transistor Q3 through the second transistor Q4, so that the first transistor Q3 is also turned off. At the moment when the transistor Q3 is turned off, due to the delay in the circuit, the transistor Q2 is still in the on state, so that the gate of the lower tube Q6 is at the same potential as the bus voltage. Due to the existence of the protection diode D1, the lower tube Q6 is both kept on and No breakdown by bus voltage. When the circuit is in steady state, the upper transistor Q5 is turned off and the lower transistor Q6 is turned on, so that a low voltage is applied to the gate of the driven GaN transistor Q1.

According to an embodiment of the present invention, the gate widths of the third transistor Q2, the first transistor Q3, the upper transistor Q5 and the lower transistor Q6 are the same, and the gate width of the second transistor Q4 is 5% of the gate width of the third transistor Q2- 30%, more preferably 10%. With such a technical solution, the response speed of the driving circuit can be improved. In the present invention, the gate widths of the two transistors are the same, which means that the difference between the gate width of one transistor and the gate width of the other transistor is within a range of 10% of the gate width of the one transistor.

According to one embodiment, the driven transistor Q1 and the GaN transistor driving circuit of the present invention are integrated on a single chip.

FIG. 3 shows input and output waveforms according to the embodiment shown in FIG. 2 . It can be seen from the waveform diagram in Figure 3 that the gate voltage of the driven device Q1 is in phase with the digital input VIN very well, the delay is short, and the output is stable.

FIG. 4 shows a schematic diagram of a GaN transistor driving circuit according to still another embodiment of the present invention. As shown in FIG. 4 , a voltage regulator circuit 30 is provided between the power supply voltage VCC and the upper and lower tube circuits.

The structure in the dashed-line box is the same as that of the embodiment shown in FIG. 2 , and thus will not be repeated.

The voltage regulator circuit outside the dashed frame is composed of transistor Q7, resistors R1, R2, capacitor C1 and diode D2 to form an LDO (low dropout linear voltage regulator) to provide the voltage required by the drain of the upper tube Q5.

In this embodiment, the drain of the transistor Q7 is connected to the power supply voltage VCC, the source is connected to one end of the capacitor C1, the other end of the capacitor C1 is connected to one end of the resistor R2, and the other end of the resistor R2 is grounded. The power supply voltage VCC is also connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the gate of the transistor Q7 and the anode of the diode D2, and the cathode of the diode D2 is grounded. The gate widths of transistors Q7 and Q4 are the same, diode D2 is a clamping diode, and the clamping voltage is 9V.

Capacitor C1 can be replaced with an enhancement mode device source-drain short and gate. In addition, the resistors R1, R2, the capacitor C1 and the diode D2 can also be composed of discrete components outside the chip.

According to this embodiment, the power supply voltage VCC and the logic high level of the digital input VIN may be 12V on average, and the logic low level of the digital input VIN is 0V.

FIG. 5 shows input and output waveforms according to the embodiment shown in FIG. 4 . It can be seen from the waveform diagram in Figure 5 that the gate voltage of the driven device Q1 is in phase with the digital input VIN very well, the delay is short, and the output is stable. At the same time, the voltage at the drain of the upper tube Q5 is also very stable.

According to embodiments of the present invention, there may be one or more of the following advantages.

(1) GaN transistors are used in the entire chip, which is more conducive to the monolithic integration of the gate driver circuit and the main device.

(2) The designed driving circuit can provide the main device (transistor Q1) with a more precise gate voltage, so that the main device can work safely and stably.

(3) On the premise of providing a gate voltage that meets the requirements for the main device, the volume and power consumption of the driver are further reduced.

However, those skilled in the art should understand that some embodiments of the present invention may not have any of the above advantages, but only provide another option.

The above detailed description of the present invention is only used to enable those skilled in the art to further connect the present invention for implementing the present invention, and does not limit the scope of the present invention. Only the claims should be used to determine the scope of this invention. Thus, combinations of features in the foregoing detailed description are not necessarily indicative of the broadest scope of the invention. The various features of the teachings presented in the specification may be combined in various ways, all within the scope of the invention, in order to obtain additional useful embodiments of the invention.

Claims (8)

1. A GaN transistor drive circuit for a driven GaN transistor (Q1), wherein the GaN transistor drive circuit comprises an upper and lower tube circuit and an upper and lower tube control circuit, The upper and lower tube circuits include an upper tube (Q5) and a lower tube (Q6), and the upper tube and the lower tube are both GaN transistors, The drain of the upper tube is connected to the power supply voltage (VCC), the gate of the upper tube is connected to the digital input (VIN), the source of the upper tube is connected to the drain of the lower tube, and serves as the The output of the GaN transistor driving circuit is connected to the gate of the driven GaN transistor; The grid of the lower tube is connected with the upper and lower tube control circuit; The upper and lower tubes control circuit uses the power supply voltage (VCC) and the digital input (VIN) to control the lower tubes, so that the output of the GaN transistor drive circuit is in phase with the digital input (VIN), and the upper and lower tubes control The circuit includes transistors, and the included transistors are all GaN transistors that conduct when a voltage above a threshold voltage is applied to the gate. 2 . The GaN transistor driving circuit according to claim 1 , wherein the upper and lower tube circuits further comprise a GaN diode, the anode of the GaN diode is connected to the gate of the lower tube, and the cathode is connected to the ground. 3 . 3. The GaN transistor drive circuit according to claim 1, wherein the upper and lower tube control circuit comprises a first transistor (Q3), a second transistor (Q4) and a third transistor (Q2), The drain of the first transistor (Q3) is connected to the source of the third transistor (Q2) and the gate of the lower transistor (Q6), and the gate of the first transistor (Q3) is connected to the The source of the second transistor (Q4) is connected, and the source of the first transistor (Q3) is grounded; The drain of the second transistor (Q4) is connected to the digital input (VIN), the gate of the second transistor (Q4) is connected to the supply voltage VCC, and the source of the second transistor (Q4) The pole is connected to the gate of the first transistor (Q3); The drain of the third transistor (Q2) is connected to the bus voltage (VD), the gate of the third transistor (Q2) is connected to the drain of the lower transistor (Q6), the third transistor The source of (Q2) is connected to the drain of the first transistor (Q3). 4. The GaN transistor drive circuit according to claim 1, characterized in that a voltage regulator circuit is provided between the power supply voltage (VCC) and the upper and lower tube circuits (10). 5. The GaN transistor drive circuit according to claim 4, wherein the voltage regulator circuit comprises a GaN transistor (Q7), a first resistor (R1), a second resistor (R2), a capacitor (C1) and a diode (D2), The drain of the GaN transistor (Q7) is connected to the power supply voltage (VCC), the source is connected to one end of the capacitor (C1), and the other end of the capacitor (C1) is connected to one end of the second resistor (R2) , the other end of the second resistor (R2) is grounded, the power supply voltage (VCC) is also connected to one end of the first resistor (R1), and the other end of the first resistor (R1) is connected to the GaN The gate of the transistor (Q7) and the anode of the diode (D2) are connected, and the cathode of the diode (D2) is grounded. 6 . The GaN transistor driving circuit according to claim 1 , wherein the GaN transistor driving circuit and the driven GaN transistor are integrated on a single chip. 7 . 7. The GaN transistor driving circuit according to claim 3, wherein the third transistor (Q2) is a high-voltage transistor, the first transistor (Q3), the second transistor (Q4), the upper transistor (Q5) and the The lower tube (Q6) is a low voltage transistor. 8. The GaN transistor driving circuit according to claim 7, wherein the gate width of the third transistor (Q2), the first transistor (Q3), the upper transistor (Q5) and the lower transistor (Q6) are the same, The gate width of the second transistor (Q4) is 5-30% of the gate width of the third transistor (Q2).

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