CN114510902B - Simulation result verification method, device, equipment and computer storage medium - Google Patents
Simulation result verification method, device, equipment and computer storage medium Download PDFInfo
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Abstract
The embodiment of the application provides a verification method, a verification device and a verification computer storage medium of a simulation result, wherein the verification method of the simulation result comprises the steps of obtaining target simulation data to be verified and waveform description information, wherein the waveform description information is generated according to first waveform information and marking information of the first waveform information, the first waveform information is obtained by simulating the first simulation data, and the waveform description information comprises waveform information corresponding to the marking information in the first waveform information; simulating target simulation data to be verified to obtain target waveform information; comparing the waveform description information with the target waveform information; and outputting verification passing information under the condition that the waveform description information and the target waveform information meet the preset condition. According to the embodiment of the application, the verification result is compared without manual operation of a verification worker, so that the simulation verification cost is reduced, and the verification efficiency and accuracy are improved.
Description
Technical Field
The present application relates to the field of simulation verification, and in particular, to a method, an apparatus, a device, and a computer storage medium for verifying a simulation result.
Background
At present, in the integrated circuit design process, each design link needs to verify the changed data, and even if the data is not changed, a large amount of verification work is still needed during the regression test.
In the prior art, integrated circuit design simulation verification is mainly to manually add simulation results and related signals to a designated simulation vector by a verifier during verification, and search key verification information in a large number of simulation signals, so as to verify whether an actual result is consistent with an expected result. However, as the scale of the integrated circuit design is increased, the labor cost is increased, and the correctness of the verification result of the manual operation is low, so the above method has the problems of low verification efficiency of the simulation result and inaccurate verification result.
Disclosure of Invention
The embodiment of the application provides a method, a device and equipment for verifying a simulation result and a computer storage medium, which can solve the problems of low verification efficiency and inaccurate verification result of the simulation result in the prior art.
In a first aspect, an embodiment of the present application provides a method for verifying a simulation result, where the method includes:
acquiring target simulation data to be verified and waveform description information, wherein the waveform description information is generated according to first waveform information and label information of the first waveform information, the first waveform information is obtained by simulating the first simulation data, and the waveform description information comprises waveform information corresponding to the label information in the first waveform information;
simulating target simulation data to be verified to obtain target waveform information;
comparing the waveform description information with the target waveform information;
and outputting verification passing information under the condition that the waveform description information and the target waveform information meet the preset condition.
In one embodiment, before obtaining target simulation data to be verified and waveform description information, the verification method of the simulation result comprises the following steps:
simulating the first simulation data based on a preset simulation excitation signal to obtain first waveform information;
labeling a preset signal and a preset time node of the first waveform information to obtain labeling information of the first waveform information;
and generating waveform description information corresponding to the labeling information according to the first waveform information and the labeling information.
In one embodiment, generating waveform description information corresponding to annotation information according to the first waveform information and the annotation information includes:
and generating waveform description information corresponding to the labeling information according to the first waveform information and the labeling information based on a preset conversion program.
In one embodiment, generating waveform description information corresponding to annotation information according to the first waveform information and the annotation information includes:
generating a script file according to the waveform information and the labeling information corresponding to the labeling information;
and generating waveform description information corresponding to the labeling information according to the first waveform information and the labeling information in the script file.
In one embodiment, simulating the target simulation data to obtain the target waveform information includes:
and simulating the target simulation data based on a preset simulation excitation signal to obtain target waveform information.
In one embodiment, the target simulation data includes regression test data or second simulation data, the second simulation data being modified data of the first simulation data.
In a second aspect, an embodiment of the present application provides an apparatus for verifying a simulation result, where the apparatus for verifying a simulation result includes:
the acquisition module is used for acquiring target simulation data to be verified and waveform description information, wherein the waveform description information is generated according to first waveform information and label information of the first waveform information, the first waveform information is obtained by simulating the first simulation data, and the waveform description information comprises waveform information corresponding to the label information in the first waveform information;
the simulation module is used for simulating target simulation data to be verified to obtain target waveform information;
the comparison module is used for comparing the waveform description information with the target waveform information;
and the output module is used for outputting verification passing information under the condition that the waveform description information and the target waveform information meet the preset conditions.
In one embodiment, the verification device of the simulation result further comprises a labeling module and a generating module;
the simulation module is further used for simulating the first simulation data based on a preset simulation excitation signal before acquiring target simulation data to be verified and waveform description information to obtain first waveform information;
the labeling module is used for labeling a preset signal and a preset time node of the first waveform information to obtain labeling information of the first waveform information;
and the generating module is used for generating waveform description information corresponding to the labeling information according to the first waveform information and the labeling information.
In an embodiment, the generating module is further configured to generate, based on a preset conversion program, waveform description information corresponding to the label information according to the first waveform information and the label information.
In one embodiment, the generating module is further configured to generate a script file according to the waveform information and the labeling information corresponding to the labeling information;
and the generating module is further used for generating waveform description information corresponding to the marking information according to the first waveform information and the marking information in the script file.
In an embodiment, the simulation module is further configured to simulate the target simulation data based on a preset simulation excitation signal to obtain target waveform information.
In one embodiment, the target simulation data includes regression test data or second simulation data, the second simulation data being modified data of the first simulation data.
In a third aspect, an embodiment of the present application provides an electronic device, including: a processor and a memory storing computer program instructions;
the processor, when executing the computer program instructions, implements a method of verification of simulation results as described in any of the embodiments of the first aspect.
In a fourth aspect, an embodiment of the present application provides a computer storage medium, on which computer program instructions are stored, and when the computer program instructions are executed by a processor, the method for verifying a simulation result as described in any embodiment of the first aspect is implemented.
In a fifth aspect, the present application provides a computer program product, where when executed by a processor of an electronic device, an instruction of the computer program product causes the electronic device to perform the verification method of the simulation result as described in any embodiment of the first aspect.
According to the verification method, the verification device, the verification equipment and the computer storage medium of the simulation result, the target simulation data to be verified are simulated by acquiring the target simulation data to be verified, and the target waveform information is obtained. Then, waveform description information generated according to the first waveform information and the label information of the first waveform information is obtained, and the waveform description information comprises waveform information corresponding to the label information in the first waveform information. And then comparing the waveform description information with the target waveform information, and outputting verification passing information under the condition that the waveform description information and the target waveform information meet preset conditions. Therefore, the waveform description information can be automatically generated to verify the consistency of the simulation result, the verification personnel do not need to manually operate to compare the verification result, the simulation verification cost is reduced, and the verification efficiency and accuracy are improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly described below, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic flowchart of a verification method of a simulation result according to an embodiment of the present application;
FIG. 2 is a second flowchart illustrating a method for verifying simulation results according to an embodiment of the present application;
FIG. 3 is a signal schematic of a waveform viewer provided by an embodiment of the present application;
FIG. 4 is a schematic structural diagram of a verification apparatus for simulation results according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are intended to be illustrative only and are not intended to be limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
As described in the background art, in the integrated circuit design process, each link of the design needs to verify the changed data, which results in an increase in the verification workload. And even if no modification is made, a large amount of work is still required when performing the regression test. Furthermore, when multiple modifications are carried out, if verification is carried out on each modification, the repeatability of the data verification work is high.
In the prior art, when the integrated circuit design is simulated and verified, a verification worker needs to manually add a simulation result and related signals, and finds key verification information in a large number of simulation signals to verify whether an actual result is consistent with an expected result, so that along with the continuous increase of the design scale of the integrated circuit and the continuous increase of complexity, the manpower required by simulation verification and regression testing is increased, and the correctness of a verification result of manual operation is low, and therefore, the above mode has the problems of low verification efficiency of the simulation result and inaccurate verification result.
In order to solve the above problem, embodiments of the present application provide a verification method, an apparatus, a device, and a computer storage medium for a simulation result, where the verification method for a simulation result can obtain target waveform information by obtaining target simulation data to be verified and simulating the target simulation data to be verified. And then, acquiring waveform description information generated according to the first waveform information and the label information of the first waveform information, wherein the waveform description information comprises waveform information corresponding to the label information in the first waveform information. And then comparing the waveform description information with the target waveform information, and outputting verification passing information under the condition that the waveform description information and the target waveform information meet preset conditions. Therefore, the waveform description information can be automatically generated, the consistency of the simulation result is verified, manual operation of verification personnel is not needed for comparing the verification result, the simulation verification cost is reduced, and the verification efficiency and accuracy are improved. First, a method for verifying a simulation result provided in the embodiment of the present application is described below.
Fig. 1 shows a schematic flowchart of a verification method of a simulation result according to an embodiment of the present application.
As shown in fig. 1, the method for verifying the simulation result may specifically include the following steps:
s110, target simulation data to be verified and waveform description information are obtained, wherein the waveform description information is generated according to first waveform information and label information of the first waveform information, the first waveform information is obtained by simulating the first simulation data, and the waveform description information comprises waveform information corresponding to the label information in the first waveform information.
The target simulation data may be test data for simulation verification of the integrated circuit design, and the waveform description information may be waveform description information generated for tagging information of first waveform information, for example, may be information of a waveform value change corresponding to the tagging information, where the first waveform information may be information obtained by simulation of the first simulation data, and the first simulation data may be initial design data for simulation verification of the integrated circuit design. The labeling information may be obtained by labeling the preset waveform information in the first waveform information, or by labeling the waveform information that is consistent with the expectation in the first waveform information, and may be, for example, information such as a key signal and a key time node, where the key time node may be a start time node, an end time node, a node of a key verification value, and the like.
As one example, the initial Design data a is simulation-verified using an Electronic Design Automation (EDA) tool, and a verification result waveform file (1. fsdb) file is generated. In the process of debugging and verifying results, a carrier waveform file (1. fsdb) is added in a waveform viewer, the waveform file (1. fsdb) contains waveform information of a large number of signal waveforms, and the waveform information of key signal waveforms in the large number of signal waveforms is labeled to obtain labeled information. And automatically generating a waveform description information file (wave.v) of the verification vector according to the waveform file (1. fsdb) and the marking information, and further acquiring the waveform description information from the waveform description information file (wave.v).
In some embodiments, the target simulation data includes regression test data or second simulation data, the second simulation data being modified data of the first simulation data.
The regression test data may be used for acceptance data or for a return test of the data, in which case the regression test data is the first simulation data.
The second simulation data may be used for data modification testing, which is typically used for testing when optimizing functions. Specifically, a complete design includes multiple functions, when the design is completed and simulation verification is performed, and a certain function needs to be optimally designed, simulation verification is performed again, that is, a data modification test is performed, and at this time, the second simulation data may be data modified by the first simulation data. The verification target is that the rest functions are unchanged except the optimization function, namely, the simulation result is unchanged.
And S120, simulating the target simulation data to be verified to obtain target waveform information.
As an example, simulation data b to be verified is simulated, and a verification result waveform file (2. fsdb) file is generated, where the waveform file (2. fsdb) includes waveform information of the simulation data b.
And S130, comparing the waveform description information with the target waveform information.
In one embodiment, the waveform description information is compared with the target waveform information by a preset waveform comparison procedure.
In one example, when verifying whether the regression test result is consistent with the expectation, it is necessary to simulate the regression test data to obtain a waveform file (2. fsdb), then read the waveform file (2. fsdb) through a preset waveform comparison program, and extract a signal waveform corresponding to the waveform of the waveform description information file (wave.v) from the waveform file (2. fsdb) during the simulation process of the regression test, so as to perform comparison verification according to the value corresponding to the waveform.
And S140, outputting verification passing information under the condition that the waveform description information and the target waveform information meet preset conditions.
As an example, the waveform file (2. fsdb) is read, whether the value of the corresponding simulation waveform in the waveform file (2. fsdb) is consistent with the value of the simulation waveform in the waveform description information file (wave.v) or not is automatically judged, if so, verification is passed, verification passing information is output, if not, verification is failed, data needs to be re-verified, failure information is output, and simulation is stopped.
Illustratively, if the print statement during the simulation of the regression test is "simulation is pass! ", this indicates that the simulation result is consistent with the expectation, and if the print statement is" simulation failed! ", the simulation result is different from the expected result, and the regression test data needs to be verified.
In the embodiment of the application, the target simulation data to be verified is simulated by acquiring the target simulation data to be verified, so that the target waveform information is obtained. And then, acquiring waveform description information generated according to the first waveform information and the label information of the first waveform information, wherein the waveform description information comprises waveform information corresponding to the label information in the first waveform information. And then comparing the waveform description information with the target waveform information, and outputting verification passing information under the condition that the waveform description information and the target waveform information meet preset conditions. Therefore, the waveform description information can be automatically generated to verify the consistency of the simulation result, and the verification personnel do not need to manually operate to compare the verification result, so that the simulation verification cost is reduced, and the verification efficiency and accuracy are improved.
In some embodiments, as shown in fig. 2, before S110, the verification method of the simulation result may further include S150-S170, which is specifically as follows:
s150, simulating the first simulation data based on a preset simulation excitation signal to obtain first waveform information.
And S160, labeling the preset signal and the preset time node of the first waveform information to obtain labeled information of the first waveform information.
And S170, generating waveform description information corresponding to the labeling information according to the first waveform information and the labeling information.
The preset simulation excitation signal may be an excitation signal preset by a user, and may be stored in an excitation file. The preset signal may be a signal of a key design module and a key signal that need to be observed, which are preset by a user, and the preset time node may be a time node of the preset signal that needs to be observed, which is preset by the user.
As an example, the data of the original design and the simulation stimulus signals 1 are subjected to simulation verification in an EDA tool, and the generated simulation verification result is embodied in a common format fsdb, i.e., a verification result waveform file (1. fsdb) file is generated. In the process of debugging and verifying results, a carrier waveform file (1. fsdb) is added in a waveform viewer, and signals of a key design module and key signals needing to be observed in the waveform file (1. fsdb) and time nodes of the signals needing to be observed are marked to obtain marking information. For example, as shown in fig. 3, the waveform file (1. fsdb) stores all signals, but it is only necessary to observe whether the waveforms of the Clock signal (Clock, CLK), the level output signal Q signal, and the Test Mode Select (TMS) signal are correct or not in a certain time period as a result of the simulation verification, so that the waveforms of the signals CLK, Q, and TMS that need to be observed are loaded in the waveform viewer, and the time nodes of the time period to be observed, that is, the start time 31 and the end time 32, are marked by using a marker (marker), and the marked time period is the start time 31 to the end time 32.
According to the waveform file (1. fsdb) and the label information, extracting the waveform information corresponding to the label information from the waveform file (1. fsdb), generating a description information file (wave.v) corresponding to the label information, and automatically adding a suffix _ ref to the signal name of the description information in the description information file (wave.v).
In the embodiment of the application, the first simulation data are simulated based on the preset simulation excitation signal to obtain the first waveform information, and the preset signal and the preset time node of the first waveform information are labeled to obtain the labeled information of the first waveform information, so that the accuracy of the labeled information can be improved, the waveform description information corresponding to the labeled information is generated according to the first waveform information and the labeled information, and the accuracy of the generated waveform description information is improved.
Based on this, the embodiments of the present application provide the following two ways of generating waveform description information, which are specifically shown as follows.
In some embodiments, the S160 may specifically include:
and generating waveform description information corresponding to the labeling information according to the first waveform information and the labeling information based on a preset conversion program.
The preset conversion program may be a program capable of converting the waveform information corresponding to the annotation information into the waveform description information, and may be a conversion program implemented in Verilog language, for example.
In the embodiment of the application, based on the preset conversion program, the waveform description information corresponding to the labeling information is generated according to the first waveform information and the labeling information, and the accuracy of generating the waveform description information is further improved.
In some embodiments, the S160 may further include:
generating a script file according to the waveform information and the labeling information corresponding to the labeling information;
and generating waveform description information corresponding to the marking information according to the first waveform information and the marking information in the script file.
The script file may be a file that includes signal information and annotation information for the currently loaded waveform, and may be an rc format file, such as a signal. And reading the labeling information in the script file, extracting the waveform information corresponding to the labeling information from the first waveform information, and generating the waveform description information corresponding to the labeling information.
Based on this, in one embodiment, the script file is read through a preset conversion program, and the waveform information corresponding to the label information is extracted from the first waveform information according to the label information in the script file, so as to generate the waveform description information corresponding to the label information.
As an example, a script file and a waveform file (1. fsdb) are read by a script-to-Verilog program, waveform information corresponding to annotation information is extracted from the waveform file (1. fsdb) according to the annotation information in the script file, and a description information file (wave.v) corresponding to the annotation information is generated, the description information file (wave.v) including information such as a waveform value change of a key signal corresponding to the annotation information.
Further, in one embodiment, the target waveform description information is compared with the target waveform information by a preset waveform comparison procedure.
Illustratively, the preset waveform comparison program is a Verilog and waveform comparison program, before the target simulation data is simulated, the Verilog and waveform comparison program is called in the simulation excitation file, and then the Verilog and waveform comparison program reads the waveform file (2. fsdb) obtained by simulating the target simulation data and extracts the signal waveform corresponding to the waveform of the waveform description information file (wave.v) from the waveform file (2. fsdb), so as to perform comparison verification according to the value corresponding to the waveform.
In the embodiment of the application, the script file is generated according to the labeling information, and the waveform description information corresponding to the labeling information is generated according to the first waveform information and the labeling information in the script file, so that the labeling information is convenient to extract, the subsequent generation of the waveform description information is convenient, and the efficiency of generating the waveform description information is improved.
In some embodiments, S120: simulating the target simulation data to obtain target waveform information, which may specifically include:
and simulating the target simulation data based on a preset simulation excitation signal to obtain target waveform information.
Illustratively, the target simulation data and the simulation excitation signal 1 are subjected to simulation verification in an EDA tool, and the generated simulation verification result is embodied in a common format fsdb, i.e. a verification result waveform file (2. fsdb) is generated, and the waveform file (2. fsdb) includes waveform information of the target simulation data.
In the embodiment of the application, the target simulation data is simulated based on the same preset simulation excitation signal as that used for simulating the first simulation data, the first waveform information and the target waveform information can be obtained according to the same excitation signal, and the consistency of the simulation result and the expectation can be observed conveniently.
FIG. 4 is a block diagram illustrating a verification apparatus 400 for simulation results according to an exemplary embodiment.
As shown in fig. 4, the verification apparatus 400 of the simulation result may include:
the obtaining module 401 is configured to obtain target simulation data to be verified and waveform description information, where the waveform description information is generated according to first waveform information and label information of the first waveform information, the first waveform information is obtained by simulating the first simulation data, and the waveform description information includes waveform information corresponding to the label information in the first waveform information;
a simulation module 402, configured to simulate target simulation data to be verified to obtain target waveform information;
a comparing module 403, configured to compare the waveform description information with the target waveform information;
and an output module 404, configured to output verification passing information when the waveform description information and the target waveform information meet a preset condition.
In one embodiment, the verification apparatus 400 of the simulation result may further include a labeling module and a generating module;
the simulation module 402 is further configured to, before obtaining target simulation data to be verified and waveform description information, simulate the first simulation data based on a preset simulation excitation signal to obtain first waveform information;
the marking module is used for marking a preset signal and a preset time node of the first waveform information to obtain marking information of the first waveform information;
and the generating module is used for generating waveform description information corresponding to the marking information according to the first waveform information and the marking information.
In an embodiment, the generating module is further configured to generate, based on a preset conversion program, waveform description information corresponding to the label information according to the first waveform information and the label information.
In one embodiment, the generating module is further configured to generate a script file according to the waveform information and the labeling information corresponding to the labeling information;
and the generating module is further used for generating waveform description information corresponding to the labeling information according to the first waveform information and the labeling information in the script file.
In an embodiment, the simulation module 402 is further configured to simulate the target simulation data based on a preset simulation excitation signal to obtain target waveform information.
In one embodiment, the target simulation data includes regression test data or second simulation data, the second simulation data being modified data of the first simulation data.
Therefore, the target simulation data to be verified is simulated by acquiring the target simulation data to be verified, and the target waveform information is obtained. And then, acquiring waveform description information generated according to the first waveform information and the label information of the first waveform information, wherein the waveform description information comprises waveform information corresponding to the label information in the first waveform information. And then comparing the waveform description information with the target waveform information, and outputting verification passing information under the condition that the waveform description information and the target waveform information meet preset conditions. Therefore, the waveform description information can be automatically generated to verify the consistency of the simulation result, the verification personnel do not need to manually operate to compare the verification result, the simulation verification cost is reduced, and the verification efficiency and accuracy are improved.
Fig. 5 shows a hardware schematic diagram of an electronic device provided in an embodiment of the present application.
The electronic device may comprise a processor 501 and a memory 502 in which computer program instructions are stored.
Specifically, the processor 501 may include a Central Processing Unit (CPU), or an Application Specific Integrated Circuit (ASIC), or may be configured to implement one or more Integrated circuits of the embodiments of the present Application.
The memory may include Read Only Memory (ROM), Random Access Memory (RAM), magnetic disk storage media devices, optical storage media devices, flash memory devices, electrical, optical, or other physical/tangible memory storage devices. Thus, in general, the memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software comprising computer-executable instructions and when the software is executed (e.g., by one or more processors), it is operable to perform operations described with reference to the methods according to an aspect of the present disclosure.
The processor 501 reads and executes the computer program instructions stored in the memory 502 to implement the verification method of the simulation result in any of the above embodiments.
In one example, the electronic device can also include a communication interface 503 and a bus 510. As shown in fig. 5, the processor 501, the memory 502, and the communication interface 503 are connected to each other through a bus 510 to complete communication therebetween.
The communication interface 503 is mainly used for implementing communication between modules, apparatuses, units and/or devices in the embodiments of the present application.
The electronic device may execute the verification method of the simulation result in the embodiment of the present application based on the acquired target simulation data to be verified and the waveform description information, thereby implementing the verification method of the simulation result described in conjunction with fig. 1.
In addition, in combination with the verification method of the simulation result in the above embodiment, the embodiment of the present application may provide a computer storage medium to implement. The computer storage medium having computer program instructions stored thereon; the computer program instructions, when executed by a processor, implement a method of verifying a simulation result as in any of the above embodiments.
It is to be understood that the present application is not limited to the particular arrangements and instrumentalities described above and shown in the attached drawings. A detailed description of known methods is omitted herein for the sake of brevity. In the above embodiments, several specific steps are described and shown as examples. However, the method processes of the present application are not limited to the specific steps described and illustrated, and those skilled in the art can make various changes, modifications, and additions or change the order between the steps after comprehending the spirit of the present application.
The functional blocks shown in the above-described structural block diagrams may be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, it may be, for example, an electronic circuit, an Application Specific Integrated Circuit (ASIC), suitable firmware, plug-in, function card, or the like. When implemented in software, the elements of the present application are the programs or code segments used to perform the required tasks. The program or code segments may be stored in a machine-readable medium or transmitted by a data signal carried in a carrier wave over a transmission medium or a communication link. A "machine-readable medium" may include any medium that can store or transfer information. Examples of a machine-readable medium include electronic circuits, semiconductor memory devices, ROM, flash memory, Erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, Radio Frequency (RF) links, and so forth. The code segments may be downloaded via computer networks such as the internet, intranets, etc.
It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, the present application is not limited to the order of the above steps, that is, the steps may be performed in the order mentioned in the embodiments, may be performed in an order different from the order in the embodiments, or may be performed at the same time.
Aspects of the present disclosure are described above with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, implement the functions/acts specified in the flowchart and/or block diagram block or blocks. Such a processor may be, but is not limited to, a general purpose processor, a special purpose processor, an application specific processor, or a field programmable logic circuit. It will also be understood that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware for performing the specified functions or acts, or combinations of special purpose hardware and computer instructions.
As described above, only the specific embodiments of the present application are provided, and it can be clearly understood by those skilled in the art that, for convenience and simplicity of description, the specific working processes of the system, the module and the unit described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again. It should be understood that the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the present application, and these modifications or substitutions should be covered within the scope of the present application.
Claims (9)
1. A method for verifying a simulation result is characterized by comprising the following steps:
acquiring target simulation data to be verified and waveform description information, wherein the waveform description information is generated according to first waveform information and label information of the first waveform information, the first waveform information is obtained by simulating first simulation data, and the waveform description information comprises waveform information corresponding to the label information in the first waveform information;
simulating the target simulation data to be verified to obtain target waveform information;
extracting signal waveform information corresponding to a waveform of the waveform description information from the target waveform information;
comparing the waveform description information with the signal waveform information;
outputting verification passing information under the condition that the waveform description information and the signal waveform information meet preset conditions;
the labeling information is obtained by labeling a preset signal and a preset time node of the first waveform information; the first simulation data is initial design data of integrated circuit design simulation verification.
2. The method of claim 1, wherein prior to said obtaining target simulation data and waveform description information to be verified, the method comprises:
simulating first simulation data based on a preset simulation excitation signal to obtain first waveform information;
labeling a preset signal and a preset time node of the first waveform information to obtain labeling information of the first waveform information;
and generating the waveform description information corresponding to the labeling information according to the first waveform information and the labeling information.
3. The method of claim 2, wherein generating waveform description information corresponding to the label information according to the first waveform information and the label information comprises:
and generating waveform description information corresponding to the labeling information according to the first waveform information and the labeling information based on a preset conversion program.
4. The method of claim 2, wherein the generating waveform description information corresponding to the label information according to the first waveform information and the label information comprises:
generating a script file according to the waveform information corresponding to the labeling information and the labeling information;
and generating waveform description information corresponding to the labeling information according to the first waveform information and the labeling information in the script file.
5. The method according to any one of claims 2 to 4, wherein the simulating the target simulation data to obtain target waveform information comprises:
and simulating the target simulation data based on the preset simulation excitation signal to obtain the target waveform information.
6. The method of claim 1, wherein the target simulation data comprises regression test data or second simulation data, the second simulation data being modified data of the first simulation data.
7. An apparatus for verifying simulation results, the apparatus comprising:
the device comprises an acquisition module, a verification module and a verification module, wherein the acquisition module is used for acquiring target simulation data to be verified and waveform description information, the waveform description information is generated according to first waveform information and label information of the first waveform information, the first waveform information is obtained by simulating first simulation data, and the waveform description information comprises waveform information corresponding to the label information in the first waveform information;
the simulation module is used for simulating the target simulation data to be verified to obtain target waveform information;
an extraction module, configured to extract, from the target waveform information, signal waveform information corresponding to a waveform of the waveform description information;
a comparison module for comparing the waveform description information with the signal waveform information;
the output module is used for outputting verification passing information under the condition that the waveform description information and the signal waveform information meet preset conditions;
the labeling information is obtained by labeling a preset signal and a preset time node of the first waveform information; the first simulation data is initial design data for simulation verification of the integrated circuit design.
8. An electronic device, characterized in that the device comprises: a processor, and a memory storing computer program instructions; the processor reads and executes the computer program instructions to implement the verification method of the simulation result according to any one of claims 1 to 6.
9. A computer storage medium, characterized in that it has stored thereon computer program instructions which, when executed by a processor, implement a method of verification of a simulation result according to any one of claims 1-6.
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