CN114501781B

CN114501781B - Plasma etched catalytic laminate with traces and vias

Info

Publication number: CN114501781B
Application number: CN202210060248.1A
Authority: CN
Inventors: 肯尼斯·S·巴尔; 康斯坦丁·卡拉瓦克斯
Original assignee: Katram LLC
Current assignee: Katram LLC
Priority date: 2016-08-18
Filing date: 2017-08-16
Publication date: 2024-12-20
Anticipated expiration: 2037-08-16
Also published as: EP3501242A1; CN114501781A; CN109906670A; KR102649271B1; EP3501242A4; KR20190049736A; WO2018035184A1; KR20220070580A

Abstract

The present application relates to plasma etched catalytic laminates with traces and through holes. The circuit board is formed from a catalytic laminate having a resin-rich surface in which catalytic particles are dispersed below the surface exclusion depth. The catalytic laminate is subjected to drilling and blanket surface plasma etching operations to expose the catalytic particles, followed by an electroless plating operation that deposits a thin layer of conductive material on the surface. A photomask step then defines the circuit traces, after which electroplating deposition occurs, followed by a resist stripping operation and flash etching to remove the electroless copper previously covered by the photoresist.

Description

Plasma etch catalyzed laminate with traces and vias

The application is a divisional application of application number 201780064641.5, entitled "plasma etching catalytic laminate with traces and vias", with application number 2017, month 08 and 16.

Technical Field

The present invention relates to a catalytic laminate and its use in the manufacture of circuit boards. In particular, the laminate has the property of providing fine pitch circuit interconnects that may be formed on the surface of the catalytic laminate or in the trenches to form a circuit board layer having a planar surface embedded with surface conductors or having surface conductors.

Background

Prior art Printed Circuit Boards (PCBs) are formed using conductive metal interconnects (referred to as "traces") formed on a dielectric substrate, with each surface carrying a conductor referred to as a "layer. Each dielectric core has traces formed on one surface or on both surfaces, and a multilayer printed circuit can be formed by stacking several such dielectric cores (which have traces formed therein interspersed with bare dielectric layers) and laminating them together under temperature and pressure. The dielectric substrate comprises an epoxy resin embedded in a fibrous matrix, such as glass fibers woven into a cloth. In one prior art fabrication method, copper is laminated onto the outer surface of a dielectric layer, the copper surface is patterned (such as with a photoresist or photosensitive film) to create masked and unmasked areas, and then etched to form a conductive trace layer on one or both sides of the core dielectric. The stack of dielectric cores with conductive traces can then be laminated together to form a multi-layer board as well as any layer interconnect (layerinterconnect) made with vias, which are drilled holes plated with copper to form annular rings that provide connections from one layer to another.

Printed Circuit Boards (PCBs) are commonly used to provide conductive traces between various electronic components mounted on the PCB. One type of through-hole device mounts an electronic component on a PCB by positioning leads through one or more holes in the PCB, wherein the PCB holes include conductive annular ring pads on each trace connection layer, and the component leads are soldered to the annular ring pads of the PCB holes. The through-hole component has leads that tend to be difficult to align with the relevant PCB mounting holes, but Surface Mount Technology (SMT) provides a preferred mounting system in which component leads are simply placed on the surface of the PCB pads and soldered, which is preferred for PCB assembly due to higher density and ease of mechanical assembly. The surface mount component requires only surface mount pads on the outer finished PCB layer. In two or more layer PCBs, vias are used to effect interconnection of conductive traces from one layer to another, with conductive traces on one trace layer leading to holes that are typically drilled through one or more dielectric layers of the PCB and plated with copper or other conductive metal to complete the trace layer connections. Holes drilled through all dielectric layers are referred to as through holes (thru-via), holes drilled through only the outer layers (typically as part of the manufacture of the individual layers) are referred to as micro-vias (micro-via), and holes drilled through one or more inner layers are referred to as blind holes. For any of these via types, the vias are patterned to include annular ring conductor areas on opposite trace layers of the PCB, and the borehole is lined with a conductive material that connects the annular ring conductors on either side of the laminate or PCB.

Electroplating may be used to increase the thickness of copper before or after patterning on a printed circuit board laminate, where a PCB or dielectric layer with traces is placed in an electrolytic cell and a DC source is connected between a sacrificial anode conductor (such as a copper bar) and the existing conductive layer of the PCB. In the case where there is no pre-existing conductive copper layer on the PCB that is convenient to electroplate (such as in the case of bare dielectric materials or drilled vias), a seed layer of copper must be deposited first. This is accomplished using an electroless plating process that electroless plates with the aid of a "seed" catalytic material deposited on the surface of the dielectric (which enhances the deposition of the specific conductive material), and then the plate is placed in an electroless plating solution. For catalysts (such as electroless plating solutions of copper and palladium), copper ions in solution deposit on the palladium until the surface is sufficiently covered to provide uniform conductivity, after which the copper deposited using the electroless plating process provides a conductive support for the subsequent addition of material using the electroplating process. Electroplating is preferred for accomplishing the electroplating operation because it has a faster deposition rate than electroless plating processes.

As electronic assemblies increase in complexity, it is desirable to increase the component density on PCB assemblies, such as by using smaller trace widths (referred to as fine pitch traces) in conjunction with increasingly dense Integrated Circuit (IC) lead patterns. One problem with prior art surface mount PCB manufacturing and assembly methods is that, because the traces are formed on the surface of the dielectric, for narrower conductor line widths (referred to as fine pitch traces), the adhesion between the copper traces and the underlying laminate is reduced, allowing the fine pitch traces and component pads to separate (lift) during component replacement operations, destroying the entire circuit board assembly and expensive components thereon. Another problem with fine pitch surface traces is that when manufacturing multi-layer circuit boards, individual trace layers are laminated together under pressure in a high temperature environment. During lamination, fine pitch traces tend to migrate laterally across the surface of the dielectric. In high speed circuit designs, it is desirable to maintain a fixed impedance between the traces, especially for differential pair (edge coupled) transmission lines. This lateral migration of the traces during lamination causes the transmission line impedance of the finished PCB differential pair to change with the length of the traces, which causes kinks and losses in the transmission line compared to transmission lines with fixed impedance characteristics resulting from constant spacing.

It is desirable to form the traces using a catalytic prepreg material that provides a blanket etched surface that exposes the catalytic particles, followed by a combination of electroless plating to provide a conductive deposit layer and then electroless plating to form traces of the desired thickness for fine trace linewidths and trace separations. It is also desirable to provide a catalytic prepreg for use in printed circuit processing wherein the catalytic prepreg has a non-catalytic surface and removal of the surface of the catalytic prepreg exposes catalytic particles that are used to form traces in areas where surface material has been removed.

Object of the Invention

A first object of the present invention is a catalytic prepreg comprising catalytic particles, wherein the catalytic prepreg conceals the catalytic particles under a resin-rich outer surface that does not expose the catalytic particles unless the outer surface of the catalytic prepreg has been removed, wherein surface removal can be accomplished using any one of laser cutting, mechanical abrasion, mechanical cutting, chemical or plasma etching or any other means of removing the outer surface of the prepreg and exposing the underlying catalytic particles under the surface of the prepreg, followed by drilling and performing blanket etching on the surface, plating the entire surface, patterning the surface with photoresist, plating the surface without photoresist, stripping the photoresist and rapidly etching for a time sufficient to remove the exposed electroless copper plating to form traces.

A second object of the present invention is a method for manufacturing a catalytic prepreg having a resin-rich outer surface free of exposed catalytic particles and a catalyst-rich layer below the resin-rich outer surface, wherein the catalytic prepreg is formed using a method having the steps of:

a fiber infusion step in which the fiber cloth is infused with a catalyzed resin formed by mixing the resin with catalyzed particles;

a vacuum compression step performed at a high temperature, whereby the outer surface of the fiber cloth impregnated with the catalytic resin is subjected to externally applied pressure in an ambient vacuum condition during a temperature ramp-up time;

A gel point step whereby an applied pressure is maintained on the outer surface of the fiber cloth impregnated with the catalytic resin to maintain a liquid/solid equilibrium for a duration sufficient for the catalytic particles to be sucked away from the outer surface;

A dwell step whereby a high temperature is applied to the laminate for the duration of the dwell time at the gel point temperature;

A cooling step whereby the fibrous cloth impregnated with the catalytic resin is cooled into a substantially flat sheet.

Summary of The Invention

In a first embodiment of the invention, a catalytic prepreg is formed by mixing a resin, a volatile solvent, and catalytic particles to form a catalytic resin mixture, infusing the catalytic resin into a fibrous fabric (such as woven glass fibers) or other fabric to form an "A-stage" catalytic prepreg, baking the fibers and resin together at an elevated temperature to remove most of the volatile solvent and form a partially cured "B-stage" catalytic prepreg such as in sheet form, thereafter placing the B-stage prepreg in a laminator, heating the B-stage prepreg at the gel point such that the prepreg is in a liquid/solid equilibrium, and thereafter curing the prepreg at an elevated temperature and pressure for a residence time sufficient to cause the catalytic particles to migrate away from the outer surface of the prepreg and form a finished "C-stage" prepreg having a resin-rich surface that is free of exposed surface catalytic particles. The resin-rich surface is mechanically removed, exposing the underlying catalytic particles, forming a surface suitable for electroless plating using copper ions in solution or any suitable electroless plating ions in solution.

In a second embodiment of the invention, a single-layer or multi-layer PCB is formed by patterning an exposed surface onto a catalytic prepreg having a resin-rich surface that excludes catalytic particles from the surface, wherein the catalytic particles are distributed below the resin-rich surface and are not exposed. In the first step, the catalytic particles are exposed by removing the surface of the material using any of these techniques with or without a patterned mask using any removal means including laser ablation, plasma etching, chemical etching, mechanical abrasion or cutting. In a second step, the catalytic laminate is placed in an electroless plating bath, wherein the electroless plated metal (such as Cu) is attracted to and bound to the exposed catalytic particles (such as Pt) in the patterned areas where the resin rich surface has been removed. The second step continues until the electroless plating fills the sides and bottom of the patterned trenches to the level of the surrounding natural surface of the catalytic laminate. In an optional third step, the surface of the patterned trench is planarized, such as by polishing, grinding, machining or etching, to match the electroless plating level to the surrounding natural surface of the catalytic laminate. In an optional third or fourth step, a solder mask is applied to cover the area of the catalytic laminate and the area of the patterned trace.

In a third embodiment of the invention, the catalytic prepreg of the first embodiment has holes formed by drilling or ablating or other means for removing material to form holes in the catalytic prepreg adjacent to the land areas where the surface of the catalytic prepreg adjacent to the holes is removed to expose the underlying catalytic particles of the catalytic prepreg in the inner surface of the holes and also the outer surface of the catalytic prepreg, which is then plated into an electroless plating solution. The resulting catalytic prepreg then forms conductive surface traces that are electrically connected to conductive vias, which may optionally form component mounting pads. The through-holes may also include conductive surface traces on opposite sides of the catalytic prepreg, wherein the first surface trace, the through-holes, and the second surface trace are all produced in a single electroless plating step. After electroless plating, the outer surface of the catalytic laminate may be planarized such that the conductive traces are flush with the natural surface of the catalytic laminate such that the individual layers of the catalytic laminate formed with the traces may be stacked and laminated into a multi-layer PCB.

In a fourth embodiment of the present invention using a conventional non-catalytic prepreg, a single-layer or multi-layer PCB is formed by a process having a first step of applying a catalytic adhesive to one or both sides of the non-catalytic prepreg, wherein the catalytic adhesive includes a resin mixed with catalytic particles, and a catalytic adhesive layer is formed on the non-catalytic prepreg. In a second step, the catalytic prepreg surface layer is selectively partially removed, such as by using a plasma cleaning or plasma etching process for a duration sufficient to expose the catalytic particles while leaving an underlying adhesive resin that secures the catalytic particles to the non-catalytic prepreg. In a third step, the partially removed or etched catalytic binder is exposed to electroless plating using the metal ions in solution bound to the catalytic particles, which is performed until a substantially continuous conductive layer of metal is deposited. In a fourth step, a pattern mask is applied that provides open areas where traces are needed. In the fifth step, the continuous conductive layer is used as an electrode for electroplating in a metal plating solution, so that metal ions in the solution are electrodeposited onto the patterned exposed conductive layer formed in the third step of electroless deposition. In the sixth step, the pattern mask is stripped, and in the seventh step, a rapid etch is performed long enough to remove electroless plating in previously unexposed areas under the pattern mask.

In a fifth embodiment of the invention, conductive vias are formed in a non-catalytic laminate by forming a first hole in the non-catalytic laminate (optionally adjacent to a first pad or a second pad formed by a conductor on a first surface or a second surface of the non-catalytic laminate), filling the first hole with a catalytic resin or a catalytic adhesive, allowing the catalytic resin or adhesive to cure, drilling a second hole in the first hole that is smaller in diameter than the hole, and electroless plating the second hole and surrounding pads, thereby forming a connection from the inner surface of the second hole to the first pad or the second pad.

In a sixth embodiment of the invention, the non-catalytic laminate layer has a coated catalytic adhesive comprising a resin and catalytic particles, the catalytic adhesive having a thickness at least twice greater than the largest catalytic particle in the adhesive, the catalytic adhesive curing and developing a resin-rich surface and an exclusion zone below the resin-rich surface in which catalytic particles are excluded, the removal of the resin-rich surface providing exposed catalytic particles suitable for electroless plating, the non-catalytic laminate optionally also having holes that can be filled with the catalytic adhesive and drilled to provide exposed catalytic particles for electroless plating of drilled holes along with conductive traces formed by electroless copper deposition.

In a seventh embodiment of the invention, a catalytic laminate has a catalytic adhesive applied to at least one surface, the catalytic laminate comprising a prepreg with catalytic particles, the adhesive comprising a resin and catalytic particles, the catalytic adhesive and the catalytic laminate being drilled to form through holes, the traces being patterned on the surface of the catalytic adhesive by removing a surface layer of the catalytic adhesive, after which the traces are formed by electroless plating on the patterned traces, after which the at least one surface is planarized.

In an eighth embodiment of the invention, a circuit board is formed by blanket etching a catalytic prepreg to expose catalytic particles below an exclusion depth, drilling through holes, electroless plating the circuit board, patterning the circuit board with photoresist, electroplating the circuit board to form traces on areas not coated with photoresist, thereafter removing the photoresist, and rapidly etching the exposed electroless copper plating to form the circuit board with traces.

The application also provides the following contents:

1) A process for forming conductive traces on a catalytic laminate having a resin-rich surface with catalytic particles of insufficient density for surface electroless plating, the catalytic laminate having catalytic particles dispersed below a catalytic particle exclusion depth sufficient for electroless plating when exposed, the process comprising:

drilling holes in the catalytic laminate;

Etching the outer surface of the catalytic laminate until the catalytic particles are exposed;

Electroless plating the catalytic laminate until conductive metal is plated on the outer surface and also within the drilled holes;

Attaching a pattern mask to an outer surface of the catalytic laminate;

electroless plating the outer surface of the catalytic laminate;

stripping the pattern mask;

the circuit board is etched quickly enough to remove any electroless conductive metal previously masked.

2) The process of 1), wherein the electroless plating and the electroplating deposit copper.

3) The process of 1), wherein the electroplated deposition thickness is greater than the electroless deposition thickness.

4) The process of 1), wherein the pattern mask is a dry film.

5) The process of 1), wherein the pattern mask is a liquid photoresist.

6) The process of 1), wherein plasma etching the outer surface uses at least one of reactive plasma, chemical etchant, laser cutting, water jet cutting, mechanical abrasion, or mechanical cutting.

7) The process of 1), wherein the exclusion depth is less than 25u.

8) The catalytic laminate of 1), wherein the catalytic particles are non-uniform.

9) The catalytic laminate of 8), wherein the catalytic particles comprise a catalyst coated filler.

10 The catalytic laminate according to 9), wherein the filler is at least one of clay minerals, hydrated aluminosilicates, silica, kaolinite, polysilicates, kaolin or members of the porcelain clay family or high temperature plastics.

11 The catalytic laminate according to 9), wherein the particle size is on the order of 3u or less than 3 u.

12 The catalytic laminate according to 9), wherein the ratio of the catalytic particles to the resin by weight is in the range of 8% to 16%.

13 The catalytic laminate according to 9), wherein the catalytic particles are silica or kaolin coated with a catalytic material.

14 The catalytic laminate of 9), wherein the catalyst is palladium.

15 The catalytic laminate according to 9), wherein the catalyst is at least one of palladium (Pd), platinum (Pt), rhodium (Rh), iridium (Ir), nickel (Ni), gold (Au), silver (Ag), cobalt (Co) or copper (Cu) or other compounds or salts thereof.

16 The catalytic laminate of 1), wherein the catalytic particles are uniform.

17 The catalytic laminate according to 16), wherein the catalyst is palladium.

18 The catalytic laminate according to 16), wherein the catalyst is at least one of palladium (Pd), platinum (Pt), rhodium (Rh), iridium (Ir), nickel (Ni), gold (Au), silver (Ag), cobalt (Co) or copper (Cu) or other compounds or salts thereof.

19 The catalytic laminate according to 16), wherein a majority of the catalytic particles have a size of less than 25 u.

Brief Description of Drawings

FIG. 1A shows a schematic diagram of a process for forming a raw catalytic prepreg.

FIG. 1B shows a vacuum laminator for forming finished catalytic prepreg from raw catalytic prepreg.

Fig. 1C illustrates a vacuum lamination stage for forming multiple layers of catalytic prepreg during lamination.

Fig. 2 shows the processing time of the vacuum lamination step of fig. 1A-1C.

Fig. 3 shows the process steps for forming the catalytic prepreg.

Fig. 4 shows a graph of the catalytic particle distribution in a prepreg material relative to a cross-sectional view of the prepreg material.

Fig. 5A shows a cross-sectional view of a natural catalytic prepreg.

Fig. 5B shows a cross-sectional view of the catalytic prepreg after a surface removal step.

Fig. 5C shows a cross-sectional view of the catalytic prepreg during an electroless plating step during a time series.

Fig. 5D shows a cross-sectional view of the catalytic prepreg after the surface smoothing step.

Fig. 5E shows a cross-sectional view of the catalytic prepreg after a solder resist step.

Fig. 5F shows a cross-sectional view of a prior art etched copper trace on a non-catalytic prepreg.

Fig. 6A shows a cross-sectional view of a catalyzed adhesive applied to a non-catalyzed prepreg.

Fig. 6B shows the cross-sectional view of fig. 6A after a plasma etching step.

Fig. 6C shows a cross-sectional view of electroless plating on a pre-impregnated substrate.

Fig. 6D shows a cross-sectional view of a mask material patterned on a prepreg substrate.

Fig. 6E shows a cross-sectional view of copper plating on a prepreg substrate.

Fig. 6F shows a cross-sectional view of the copper plating after stripping the mask.

Fig. 6G shows a cross-sectional view of the pre-impregnated substrate after rapid etching to remove surface copper.

Figure 7A shows a cross-sectional view of a non-catalytic prepreg with foil lamination.

Fig. 7B shows a cross-sectional view of the etched non-catalytic prepreg after patterning.

Fig. 7C shows a cross-sectional view of the non-catalytic prepreg after the holes are drilled.

Fig. 7D shows a cross-sectional view of the non-catalytic prepreg after filling the holes with catalytic filler.

Fig. 7E shows a cross-sectional view of the non-catalytic prepreg after the second annular hole is drilled.

Fig. 7F shows a cross-sectional view of the non-catalytic prepreg after electroless plating of the annular aperture.

Fig. 7G shows a perspective transparent view of a via formed using the process of fig. 7A-7F.

Figure 8A shows a cross-sectional view of a non-catalytic prepreg laminate.

Fig. 8B shows fig. 8A after application of the catalytic adhesive.

Fig. 8C shows fig. 8B after a drilling/perforating operation.

Fig. 8D shows fig. 8C after a surface removal operation.

Fig. 8E shows fig. 8D after an electroless plating operation.

Fig. 9A, 9B, 9C, 9D and 9E show various stages of a cross-sectional view of a catalytic adhesive coated on a catalytic laminate that has been drilled, etched, electroless plated and planarized.

10A, 10B, 10C, 10D, 10E, 10F, 10G, 10H and 10I illustrate various stages of a cross-sectional view of a catalytic laminate having traces formed on exposed catalytic surfaces.

Detailed description of the invention

Fig. 1A shows an example process for manufacturing a prepreg (matrix of prepreg fibers incorporated in a resin). Many different materials may be used for the fibers of the prepreg, including woven fiberglass cloth, carbon fibers, or other fibers, and a variety of different materials may be used for the resin, including epoxy resins, polyimide resins, cyanate ester resins, PTFE (teflon) blend resins, or other resins.

One aspect of the present invention is a printed circuit board laminate capable of supporting fine pitch conductive traces on the order of 1 mil (25 u), and while the present description focuses on the use of catalysts for electroless copper formation to form copper traces, it should be understood that the scope of the present invention extends to other metals suitable for electroless plating and electroplating. For the electroless deposition of copper (Cu) channels, elemental palladium (Pd) is preferred as catalyst, however selected periodic table transition metal elements such as group 9 to 11 platinum (Pt), rhodium (Rh), iridium (Ir), nickel (Ni), gold (Au), silver (Ag), cobalt (Co) or copper (Cu) or other compounds of these including other metals such as iron (Fe), manganese (Mn), chromium (Cr), molybdenum (Mo), tungsten (W), titanium (Ti), tin (Sn) or any of the mixtures or salts of the above may be used as catalytic particles. The present candidate list is intended to be exemplary, rather than comprehensive, and other catalysts for attracting copper ions are known in the art. In one example of the invention, the catalytic particles are homogeneous catalytic particles. In another example of the invention, the catalytic particles are inorganic particles or refractory plastic particles coated with catalytic metal of a thickness of a few angstroms to form heterogeneous catalytic particles having a thin catalytic outer surface encapsulating non-catalytic inner particles. For larger catalytic particles (such as particles with a longest dimension on the order of 25 u), this formulation may be desirable. The heterogeneous catalytic particles of this formulation may include inorganic, organic or inert fillers such as silica (SiO 2), inorganic clays such as kaolin, or high temperature plastic fillers coated with a catalyst on the surface such as palladium adsorbed onto the surface of the filler by vapor deposition or chemical deposition. In order for the catalytic particles to have desirable properties that facilitate electroless plating, only a few atomic layers of catalyst are required.

In one example of forming heterogeneous catalytic particles, a filler plating solution (organic or inorganic) is sized to include particles smaller than 25u in size, these sized inorganic particles are mixed into the aqueous plating solution in a tank, stirred, and then a palladium salt, such as PdCl (or any other catalyst, such as a silver salt of other catalyst) is introduced in the presence of an acid, such as HCl, and in the presence of a reducing agent, such as hydrazine hydrate, the mixture thereby reducing the metallic palladium coating the inorganic particles, providing a thickness of a few angstroms of Pd coated on the filler, thereby producing heterogeneous catalytic particles having catalytic properties of uniform Pd particles with greatly reduced volume requirements of Pd compared to using uniform Pd metal particles.

Exemplary inorganic fillers include clay minerals that may contain varying amounts of iron, magnesium, alkali metals, alkaline earth metals, and other cations, such as hydrated aluminosilicates. Exemplary inorganic fillers of this family include silica, aluminum silicate, kaolinite (Al ₂Si₂O₅(OH)₄), polysilicates, or other clay minerals belonging to the kaolin or china clay families. Exemplary organic fillers include PTFE (teflon) and other polymers with high temperature resistance.

Examples of palladium salts are :BrPd、CL₂Pd、Pd(CN)₂、I₂Pd、Pd(NO₃)₂*2H₂O、Pd(NO3)₂、PdSO₄、Pd(NH₃)4Br₂、Pd(NH₃)4Cl₂H₂O. the catalytic powders of the invention may also contain a mixture of heterogeneous catalytic particles (e.g., catalytic material coated on inorganic filler particles), homogeneous catalytic particles (such as elemental palladium), and non-catalytic particles (selected from the group of inorganic fillers).

Among the catalysts, palladium is the preferred catalyst due to comparative economy, availability and mechanical properties, but other catalysts may also be used.

Fig. 1A shows that as a set of rollers directs the fabric into reservoir 108, a roll of fabric cloth 102 (such as woven fiberglass) is fed through, reservoir 108 is filled with epoxy mixed with catalytic particles and mixed with a volatile liquid to reduce viscosity, forming a stage a (liquid) prepreg.

The resin may be a mixture of polyimide resin, epoxy resin and cyanide ester (which provides cure at high temperature) or any other suitable resin formulation having a selectable viscosity during coating and thermosetting after cooling. Flame retardants may be added, for example, to meet flammability standards or to be compatible with one of the standard FR series of prepregs (such as FR-4 or FR-10). Additional requirements for high speed circuits are the dielectric constant epsilon (permittivity), which is often about 4 and controls the characteristic impedance of the transmission line formed on the dielectric, and the loss tangent delta, which is a measure of the frequency dependent energy absorption over a distance, whereby the loss tangent is a measure of how the dielectric interacts with the high frequency electric field to undesirably reduce the signal amplitude by a calculable amount of dB/cm of the transmission line length. The resin is mixed with catalytic particles classified by size. In one example formulation, the catalytic particles comprise at least one of uniform catalytic particles (metallic palladium) or non-uniform catalytic particles (palladium coated on inorganic particles or high temperature plastics), and for either formulation, the catalytic particles preferably have a maximum range of less than 25u, and 50% by total number of the particles have a particle size between 12u and 25u or in the range of 1-25u or less. These are exemplary catalytic particle size examples and are not intended to limit the scope of the invention. In one example embodiment, the catalytic particles (uniform or non-uniform) are in the size range of 1u-25 u. In another example of the invention, uniform catalytic particles are formed by grinding metallic palladium into particles and passing the resulting particles through a screen having a mesh with 25u rectangular openings. In another example, the catalyzed resin mixture is formed by mixing homogeneous or heterogeneous catalyzed particles into a pre-impregnated resin at a weight ratio (such as a ratio of substantially 12% by weight of catalyzed particles to the weight of the resin). The ratio of the catalytic particles in the resin mixture by weight may alternatively be in the range of 8-16% by weight of the catalytic particles relative to the total weight of the resin. It should be understood that other mixing ratios may be used and that the use of smaller particles may be preferred. In one example of the invention, the catalytic particle density is selected to provide an average distance between catalytic particles on the order of 3u-5 u.

After immersing the fabric in the catalyzed resin plating solution 106 with the roll 104, the catalyzed resin impregnated cloth is directed to the roll 110, the roll 110 establishing the thickness of the uncured liquid a stage prepreg 105, which also establishes the percentage of resin as a function of the resin/glass+resin ratio. The a-stage prepreg 105 is then passed through an oven 103, the oven 103 driving out organics and other volatile compounds of the a-stage prepreg and greatly reducing the liquid content to form a non-tacky B-stage prepreg 107 that is conveyed by rollers 111. In an exemplary embodiment, oven 103 dries the volatile compounds from about 80% solvent ratio of the a-stage prepreg to less than about 0.1% solvent ratio of the B-stage prepreg. The resulting B-stage prepreg 107 is then provided to a material handling apparatus and may be cut into sheets for ease of handling and storage and then placed into the laminator 126 of fig. 1B, which applies pressure under vacuum across the entire surface of the sheets, changing the temperature profile while the prepreg core is in the laminator, following the temperature profile 202 shown in fig. 2. In one example of the invention, to create a resin-rich surface, prepreg sheets located near the outer surface that will later have the surface removed to expose the underlying catalytic particles are selected to have greater than 65% resin, such as glass 106 (71% resin), glass 1067, or glass 1035 (65% resin), and the inner prepreg sheets (which are not subjected to surface removal) are selected to have less than 65% resin. Further, to reduce the likelihood that glass fibers are present near the surface of the catalytic prepreg, woven glass fibers may be used with the inner prepreg layer, and flat non-woven glass fibers may be used in the outer resin-rich prepreg layer. The combination of the resin-rich prepreg and the flat non-woven glass fibers on the outer surface layer resulted in a 0.7 mil (17 u) to 0.9 mil (23 u) exclusion zone between the outer surface and the encapsulation glass fibers. Glass types 106, 1035 and 1067 are preferred for use on resin-rich outer surfaces because the glass fiber thickness (1.3-1.4 mil/33-35 u) is less than that found in typical prepreg sheets having greater than 65% of the resin used in the central region of the laminate, such as glass type 2116 having 3.7 mil (94 u) fibers. These values are given as examples, and the minimum glass fibers available in the market are expected to continue to decrease in diameter. The temperature versus time curve 202 is modified in the present invention to cause the catalytic particles and glass fibers to migrate away from the outer surface of the laminate, being repelled by the surface tension of the epoxy during the liquid state at the gel point temperature. After the cooling cycle of curve 202, the cured C-stage prepreg sheet is unloaded 114. The process of forming the cured C-stage prepreg sheet may use single or multiple fibrous fabric sheets to vary the finished thickness, which may vary from 2 mils (51 u) to 60 mils (1.5 mm).

Fig. 3 shows a flow chart of a process for manufacturing a prepreg laminate with impregnated but catalytic particles removed from the outer surface of the prepreg. Step 302 is to mix catalytic particles into the resin, and organic volatiles are often added to reduce the viscosity of the mixture, which forms a catalyzed resin that is placed in reservoir 108. Step 304 is infusing catalyzed resin into the fabric (such as roll 104 of fig. 1A may be provided to form an a-stage prepreg), and step 306 is, for example, passing catalyzed resin infused fabric through roll 110 to form the most primary grinding of the B-stage prepregs, step 307 is a bake step for removing the organic solvent to form the B-stage prepregs, and step 308 is pressing catalyzed resin infused fabric 130 into a sheet of catalyzed C-stage prepregs in laminator 126, which follows the temperature cycle of curve 202, and vacuum pump 128 evacuates chamber 124 throughout the lamination process to remove air bubbles from the epoxy and reduce any air pockets that may form in the epoxy. The cooled finished catalytic C-stage prepreg sheet is cut and stored for later use.

The temperature versus time curve 202 of fig. 2 shows the temperature profile of the prepreg in the laminator 126, which is critical for catalyzing the formation of a prepreg having surface properties of catalytic particles that are excluded from the resin-rich outer surface but that are present just below the resin-rich outer surface. The resin is in a liquid state in the reservoir 108 and after the resin is impregnated into the glass fibers and the prepreg is passed through the roller 110, the prepreg is in stage a. The prepreg is in a B-stage after baking, where volatile organics are baked out, with an initial resin cure, which at the end of the lamination cycle (e.g., the cool-down stage of fig. 2) will convert the B-stage prepreg into a C-stage prepreg. The B-stage prepreg was placed into a laminator and a vacuum was pulled to prevent the formation of trapped air between the lamination layers. Heat is applied during the temperature ramp-up time 204 to reach a pre-impregnated gel point 205 (gel point being defined as the state where the liquid and solid states are near equilibrium with each other) of determined temperature and pressure within a duration of about 10-15 seconds, which is critical to the process of migrating catalytic particles away from the surface, after which the temperature of the prepreg is maintained at a residence temperature and residence time 206, which may be in the range of 60-90 minutes, followed by a cooling cycle 208. The residence temperature and gel point temperature are pressure and resin dependent, in the exemplary range of 120 ℃ (for epoxy) to 350 ℃ (for teflon/polyimide resin). Maintaining the prepreg at the gel point 205 for too short a duration will result in the undesirable presence of catalytic particles or glass fibers at the surface of the finished prepreg.

Fig. 4 shows the resulting catalytic prepreg 402 formed by the processes of fig. 1A-1C, 2, and 3, wherein the catalytic particles 414 are uniformly distributed within the central region of the prepreg 402, but are not present below the first boundary 408 below the first surface 404, or below the second boundary 410 below the second surface 406. For an example particle distribution of particles less than 25u, the catalytic particle boundaries are typically 10-12u below the surface (about half the particle size), so in order for embedded catalytic particles to be available for electroless plating, surface material at this depth or greater must be removed.

The catalytic laminates of the prior art have an activated surface that must be masked to prevent unwanted electroless plating on the activated surface of the catalytic laminate. In contrast, the catalytic laminate of the present invention excludes catalytic particles in the thickness range from the first surface 404 to the first boundary 408 and from the second surface 406 to the second boundary 410, providing the benefit that a separate masking layer to prevent contact with catalytic particles is not required for electroless plating, as it is in the prior art. Thus, removal of surface material from the depth of the first surface 404 to the first boundary 408 or greater or removal of surface material from the second surface 406 to the second boundary 410 results in exposure of catalytic material available for electroless plating. It is also desirable for processes that provide a resin-rich surface to exclude not only catalyst but also fiber fabrics, because in subsequent steps that result in exposure of the fibers, removal of the surface layer requires an additional cleaning step, so surface removal is only preferred for the resin to expose the underlying catalytic particles. This is achieved by using a combination of a resin-rich outer prepreg layer and a flat non-woven glass fiber layer with smaller diameter fibers on the outer layer. Another advantage of using electroless plating to form traces in the vias is that the traces are mechanically supported on three sides, which provides greatly improved trace adhesion to the dielectric laminate.

The sequence of fig. 5A-5E shows process steps (but not to scale) identifying various structures and provides a simplified view of the process steps for an understanding of the present invention only. Fig. 5A shows an enlarged cross-sectional view of a catalytic prepreg 508 formed by the processes of fig. 1A-1C, 2, and 3. The catalytic particles 502 may be in the size range of 25u and smaller, which are shown in the range of 12u to 25u for clarity in this example. As previously mentioned, the catalytic particles may include heterogeneous catalytic particles (organic or inorganic particles with catalytic surface coatings) or homogeneous particles (catalytic metal particles). The first boundary 504 is about 25u below the first surface layer 506. The second surface layer 505 and the second surface boundary 503 on the opposite surface are shown for reference, but may be formed in the same manner as described for the sequence of fig. 5A to 5E. Also shown is a borehole 511 that would provide a connection between the trace on the first surface layer 506 and the trace on the second surface layer 505.

Fig. 5B shows the laminate of fig. 5A with channels 510, the channels 510 being formed by removing the first surface layer 506 in areas where traces are desired. Prepreg is also removed at the same or a different depth in the annular ring 513 surrounding the via than the trace channel 510. The surface material may be removed by laser ablation, wherein the temperature of the catalytic prepreg is immediately raised until the catalytic prepreg is evaporated, while the surrounding prepreg is kept structurally unchanged, keeping the catalytic particles exposed. For ablated prepreg materials, it may be preferable to use a laser having a wavelength with low reflectivity, such as an Ultraviolet (UV) wavelength, and high absorption of that optical wavelength. Examples of such UV lasers are UV excimer lasers or Yttrium Aluminum Garnet (YAG) lasers, which are also good choices due to the narrow beam range and high available power used to form channels with precise mechanical depth and well-defined sidewalls. An example laser may remove material at a 0.9-1.1 mil (23 u to 28 u) diameter width with depth controlled by laser power and speed of movement across the surface. Another surface removal technique for forming the channels 510 and annular ring 513 is plasma etching, which may be accomplished locally or by preparing the surface with a patterned mask (such as a dry film photoresist or other mask material having a low etch rate compared to the etch rate of the catalytic prepreg) that excludes plasma from the first surface layer 506 or the second surface layer 505. The photoresist thickness is typically selected based on the epoxy/photoresist etch selectivity (such that the plasma etch used to remove the desired depth of cured epoxy leaves sufficient photoresist at the end of the etch), or in the case where the photoresist is used as a plating mask, the thickness is selected according to the desired deposition thickness. Typically, the dry film thickness is in the range of 0.8-2.5 mils (20-64 u). The plasma suitable for etching the resin-rich surface includes a mixture of oxygen (O) and CF ₄ plasma mixed with an inert gas such as nitrogen (N), or argon (Ar) may be added as a carrier gas for the reaction gas. The mask pattern may also be formed using a dry film mask, a metal mask, or any other type of mask having holes. In the case of using a mechanical mask, the resist may be applied using a photolithography method, screen printing, stencil printing, brushing with a squeegee, or any method of applying a resist. Another method for removing the surface layer of the prepreg is mechanical grinding, such as a linear or rotary cutting tool. In this example, the prepreg may be held in a vacuum panel chuck and a rotary cutter (or a stationary cutter with a movable vacuum panel) may travel a pattern defining a trace such as that defined by the x, y coordinate pair of a Gerber format photo file. In another example of removing surface material, a water cutting tool may be used, wherein a water jet with abrasive particles entrained in a stream may impinge on the surface, thereby removing material below the first boundary 504. Any of these methods may be used alone or in combination to remove surface material from the catalytic prepreg 508 and form channels 510, preferably extending below the first boundary 504. Thus, the minimum channel depth is the depth required to expose the underlying catalytic particles (which is characteristic of cured prepreg). Because the catalytic material is uniformly dispersed throughout the cured prepreg below the first boundary 504, the maximum channel depth is limited by the depth of the woven fiber (such as fiberglass) fabric, which tends to complicate channel cleaning, as the fibers may fracture and redeposit in the channels intended for electroless plating, or otherwise interfere with subsequent process steps. Typical channel depths are 1 mil (25 u) to 2 mils (70 u). The final step after removing the surface material to form the channels 510 is to clean out any particles of the removed material, which may be done using ultrasonic cleaning, a water jet mixed with a surfactant, or any other cleaning means that does not result in the removal of material of the first surface layer 506 around the channels.

Fig. 5C shows a contour plot of the progress of electroless plating over time, wherein the catalytic prepreg of fig. 5B is placed in an electroless plating solution using a dissolved reducing agent to reduce metal ions on the catalytic prepreg to a metallic state. One example electroless copper plating bath formulation uses a mixture of rochelle salt as a complexing agent, copper sulfate as a copper metal source, formaldehyde as a reducing agent, and sodium hydroxide as a reactant. In this example, tartrate (rochelle salt) plating solutions are preferred for ease of waste treatment, rochelle salt not being as strongly sequestered as alternatives such as EDTA or ethylenediamine. In this example, tartrate (rochelle salt) is the finishing agent, copper sulfate is the metal source, formaldehyde is the reducing agent, and sodium hydroxide is the reactant. Other electroless plating formulations are also possible, examples of which are given for reference. Electroless plating is initially formed on the surface of the exposed catalytic particles as shown in the shadow pattern 520 and the matching shadow pattern in the through holes 535 at time t 1. As electroless plating proceeds to the hash region for the deposition shown at subsequent times t2 522, t3 524, and t4, copper deposition progresses, at which point the deposition 526 may extend above the first surface layer 506 and the vias 535 are also filled with copper.

One key advantage of electroless plating with channels etched in the catalytic material is that electroless plating progresses simultaneously on all three sides compared to plating that is treated from only the bottom (initially plated) layer.

Fig. 5D shows the result of the surface smoothing operation, wherein the completed electroless trace 534 and via 535 are coplanar with surface 532. Surface smoothing can be achieved in many different ways, for example using a 420 to 1200 grit abrasive coated on a flat surface with gentle pressure and linear or rotational agitation between the flat surface to provide the abrading operation. Other methods for planarizing a surface may be used, including milling or machining using chemical processes, mechanical processes, or other methods for forming a planar surface. Fig. 5E shows a solder mask 536, which may be screen printed on the traces 534 for isolation and protection, such as a finished outer layer of a multilayer board.

Fig. 5F shows a prior art etched copper trace for comparison purposes. The trace 554 is formed using a subtractive etching process of the prior art, where trace 554 is what remains after etching the remainder of the copper present on the surface layer on the non-catalytic prepreg 550. The copper outer layer is patterned with a photoresist (such as a dry film) and then the surface is etched, which creates a trapezoidal cross-sectional profile of trace 554, as the top of the trace undergoes a greater lateral etch than the bottom of the trace adjacent to the non-catalytic prepreg 550. Another advantage of the additive process of the present invention is that, for traces formed using prior art processes that etch all copper except the desired trace copper, surface contamination on the surface causes adjacent traces to short because copper bridges (where contamination is present on the surface of the copper) remain, which does not occur in the additive electroless plating of the present invention. For comparison with the figures of the present invention, a solder mask layer 552 is also shown. As seen in the figure, trace 554 is supported by adhesion to non-catalytic prepreg 550 only, while trace 534 of fig. 5E is supported on three sides and locked into its associated channels in catalytic prepreg 508.

Fig. 6A through 6G illustrate another embodiment of the present invention using non-catalytic prepreg 602, which may be conventional prepreg without catalytic particles. In this example of fig. 6A, a through hole 603 is first punched or drilled in the non-catalytic prepreg 602. The catalytic binder is formulated by mixing a resin and catalytic particles, which may be in the same proportions and manner as the catalytic resin described previously (although for certain surface coating applications (such as by brushing with a squeegee), it may have a higher viscosity), the main difference being that the catalytic binder is applied to a (typically) non-catalytic substrate, although it may also be applied to a catalytic substrate. For use in the catalytic binder, the catalytic particles are stirred until sufficiently wetted such that the catalytic binder 604 ensures that the catalytic particles 606 are not exposed until a subsequent surface coating removal operation (such as the plasma cleaning of fig. 6B). In this example, catalyzed resin is sprayed or brushed onto the surface of the non-catalyzed prepreg 602 and into the through holes 603 as shown in FIG. 6A. The catalytic binder 604 comprises a resin containing a distribution of catalytic particles (such as palladium particles less than 25 u), or in one example of the invention, 50% by number of the particles fall within the range of 12-25u in terms of the longest particle size or have a particle range of 1-25u as possible examples. The catalytic binder may be formed using a ratio of catalyst weight to resin weight of 8-16% (with 12% being the preferred value), as previously described for the catalytic resin. The resulting catalyzed adhesive may be applied to a non-catalyzed substrate and both baked to cure the catalyzed adhesive to the non-catalyzed prepreg 602. In one application method, the catalyzed adhesive is applied to the leading edge of a mechanized applicator that includes a flexible blade carrying the catalyzed adhesive and passing over the surface of the non-catalyzed laminate, and the pressure and spacing between the flexible blade and the non-catalyzed laminate is adjusted such that any drilled holes are filled with catalyzed laminate and the catalyzed laminate of the desired thickness is uniformly disposed on the surface of the non-catalyzed laminate in a single pass of the applicator. The catalytic adhesive is typically 12-75u thick. The catalytic binder thickness should be at least 2 times thicker than the largest catalytic particle to ensure that the catalytic particles remain below the surface of the catalytic binder.

The surface of fig. 6A is then subjected to a plasma cleaning step that strips the resin from the area above the surface of the catalyzed particles and the non-catalyzed resin, leaving catalyzed particles 606 adhered to the surface of the non-catalyzed prepreg 602 as shown in fig. 6B. Fig. 6C shows the result of placing the plasma cleaned surface of fig. 6B in an electroless plating solution, which is completed long enough to form a thin but continuous coating of electroless copper deposit that initially forms on the catalytic particles 606 and spreads over the entire top surface. Fig. 6D shows the addition of a pattern mask 610 on the electroless copper layer 608. Because the electroless plating now covers the surface of the non-catalytic prepreg 602, a plating operation may then occur to plate additional copper onto the exposed patterned areas, as shown by trace 612 of fig. 6E, which may deposit copper to a level below or above the mask 610. In fig. 6F, a mask stripping operation is shown that removes the pattern mask 610, leaving behind copper traces 612 and electroless copper layer 608. Fig. 6G shows the result of a rapid etch that removes the surface of the thin electroless copper layer 608 and an equal amount of trace 612, leaving a trace comprising a uniform trace comprising electroplated copper and underlying electroless copper deposition, thereby providing a conductive circuit trace.

10A, 10B, 10C, 10D, 10E, 10F, 10G, 10H, and 10I illustrate a series of steps that may be performed on the catalytic laminate previously described in FIG. 4, the catalytic laminate having catalytic particles 414 distributed throughout the catalytic laminate and having catalytic particle exclusion depths 418 below the first surface 404 and the second surface 406 such that electroless plating does not occur unless the second surface 406 or the first surface 404 is removed below the exclusion depths 418, thereby exposing the catalytic particles. The catalytic particle exclusion depth 418 is 1/2 of the average catalytic particle size.

Fig. 10A shows prepregs associated with the outer surfaces 1004 and 1008, the outer surfaces 1004 and 1008 being free of catalytic particles until the outer surfaces are removed to depths 1002 and 1010, respectively, sufficient to expose the underlying catalytic particles below the removal depth.

Fig. 10B shows an example through-hole or through-hole 1012 that, when drilled, exposes catalytic particles on the inner surface 1014 of the drilled hole.

Fig. 10C shows the catalytic laminate 1006 after blanket etching the entire outer surface of the catalytic laminate 1006 below the exclusion depth, thereby producing an outer surface 1018 exposed to catalytic particles. The original pre-etch catalytic laminate surface 1016 is shown for reference. The sequence of operations of fig. 10B for the drilling of holes/vias 1012 and the outer surface blanket etching of fig. 10C may be performed in any order. The blanket etching may preferably be performed using a reactive plasma, chemical etchant, however laser cutting, water jet cutting, mechanical abrasion, mechanical cutting, or any other means of uniformly etching the outer surface of the prepreg and exposing the underlying catalytic particles below the surface and into the exclusion depth may be used. The step of fig. 10C is performed without any pattern mask of the previous catalytic laminate etching operation, as the goal is to remove the resin rich surface below the exclusion depth to expose catalytic particles on the entire surface of the catalytic laminate 1006.

The deposition of surface conductors, such as copper, may be performed on the surface using two different electroplating techniques. In a first electroless plating technique, a dielectric layer having exposed catalytic particles (such as palladium) is immersed in a plating solution containing metal ions (such as copper). The electroless deposition of metallic copper onto the catalytic surface is slower than the electroplating deposition rate of metallic copper, but electroless plating occurs on all surfaces with exposed catalytic particles and also on surfaces with copper. Electroplating requires a uniform conductive surface, and electroless plating is used as a front indicator of electroplating. Electroplating also requires an external voltage source, resulting in a faster rate of copper deposition than electroless deposition. A sacrificial copper anode with a positive voltage is placed in an electrolyte plating solution and the conductive surface to be plated is connected to a negative voltage. Anode copper migrates from the anode and through the electrolyte to the cathode surface as metal ions, which deposit on the cathode surface. In this example, the cathode surface is a PCB that requires copper plating. Electroplating requires that all surfaces have a common potential, which is typically accomplished by using copper foil or an electroless plating step on dielectric surfaces with exposed catalytic particles, until the continuous conductivity across the plate allows the plate to function as an anode, as required for a cathodic copper source.

Fig. 10D illustrates the completion of the electroless plating step wherein the drilled and surface etched catalytic laminate 1006 is placed in an electroless plating bath of metal ions (typically copper) deposited onto the outer surface 1018 of the laminate and inside the drilled holes of fig. 10C to create a continuous conductive surface required for subsequent electroplating operations. The thickness of electroless copper 1020 should be the minimum thickness required to ensure continuous coverage for successful plating and is typically on the order of 0.15 mils.

Fig. 10E shows a subsequent step of applying a patterned photoresist 1024 over the previously applied electroless copper 1020, wherein the photoresist 1024 covers all areas except the areas where traces or loop conductors around the drilled holes or vias 1012 are needed. The patterned photoresist 1024 has the effect of isolating the patterned area from subsequent electroplating.

Fig. 10F shows a subsequent step of electroplating copper 1022 onto electroless copper plating 1020, with electroless copper plating 1020 serving as an electrode in the electroplating operation. The thickness of electroplated copper 1022 can be any thickness, preferably less than the thickness of resist 1024 and greater than 1 times (or preferably 2 times or more) the thickness of electroless metal deposition.

Fig. 10G shows a subsequent step of stripping the resist 1024 of fig. 10F, thereby exposing the initially coated thin electroless copper areas 1026. Preferably, the thickness of the electroplated copper 1022 is greater than the thickness of the electroless copper 1020 such that the rapid etching step of fig. 10H preferentially removes the exposed electroless copper areas 1026 and leaves substantially all of the electroplated copper 1022.

Fig. 10I shows the completed process. For clarity in understanding the invention and the processing steps, the boundary between electroless copper 1020 and electroplated copper 1022 is presented in the foregoing. When electroplated copper 1022 is deposited on exposed electroless copper 1020 during the step of fig. 10F, the resulting via plating around the hole of fig. 10I and electroless copper 1020/electroplated copper 1022 is continuous copper, as shown.

The series of fig. 7A through 7G show cross-sectional views of a series of steps for forming a through hole in a conventional non-catalytic prepreg 702 having an upper foil laminate layer and a lower foil laminate layer. Fig. 7G shows a perspective view of the finished through hole, while fig. 7A to 7F are sectional views through A-A of fig. 7G at the end of various intermediate processing steps.

Fig. 7B shows a cross-sectional view of the upper trace 704 and the lower trace 706 after patterning, where the upper trace 704 will be connected to the lower trace 706 on the opposite surface of the non-catalyst prepreg 702. Fig. 7B shows a through hole 708 that may be formed by punching or drilling, the hole 708 being located in the center of the annular ring of pads 716 formed by the upper trace 704 and 718 formed by the lower trace 706. Fig. 7D shows a catalytic filler 710, such as a formulation with plugged through-holes of catalytic particles. Catalytic filler 710 is typically a thick fluid having a viscosity in the range of 70,000-80,000 centipoise (cP) that is placed in through-hole 708 of fig. 7C, and fig. 7E shows secondary holes 712 drilled into catalytic filler 710 that expose catalytic filler particles present in catalytic filler 710, thereby making the catalyst available for electroless plating operations. An electroless copper deposition step follows and electroless copper cu++ is formed on the upper trace 704, annular ring top land 716, through the secondary hole 712 with exposed catalytic particles, on the lower land 718, and on the lower trace 706 to form a conductive deposition layer 714, which completes the circuit from the upper trace 704 through the via structure to the lower trace 706. As will be clear to those skilled in the art, although an annular ring conductor is shown on each connection surface, the traces may be directly connected into the vias with or without an annular ring.

Fig. 8A illustrates another method for electroless plating of traces onto a laminate using a non-catalytic substrate or prepreg 802, with optional holes 804 drilled or punched for layer-to-layer connection. Fig. 8B illustrates application of the catalytic adhesive 806, such as using a squeegee, screen printing, stencil, or any other method as previously described with respect to fig. 6A. During this coating operation, the holes 804 are also filled with catalytic adhesive 806. Fig. 8C shows a secondary borehole 808 in the annular ring of holes 804 that activates the catalytic adhesive 806 in the borehole 808 by exposing catalytic particles. Fig. 8D shows removal 814 of the surface layer sufficient to expose catalytic particles for forming electroless conductive traces, pads, and vias. Fig. 8E shows the completion of electroless plating, wherein copper 816 is plated onto the catalytic bond that has been drilled, etched, or otherwise removed. Planarization may optionally be performed, or a solder mask may be applied, as described for fig. 5D. In certain applications, such as high frequency applications where dielectric loss tangent is critical, it may be desirable to use a non-uniform mixture of a non-catalytic laminate, such as PTFE, with a resin-based catalytic laminate. In such a case, it may be necessary to roughen the surface of the non-catalytic laminate (such as PTFE) using plasma etching, chemical etching, or other methods known in the art for disrupting long chain polymer molecules, to provide better adhesion to the catalytic adhesive at the catalytic adhesive/PTFE boundary. In one example of the invention, the PTFE non-catalytic substrate is uniform PTFE, in another example it is a laminate, and in either case the substrate may or may not include a fibrous (such as fiberglass) reinforcement.

Variations of the laminated structure of fig. 8A-8E are shown in fig. 9A-9E, wherein a catalytic adhesive 906 is used on the catalytic laminate. This approach has several advantages. One advantage is that the application of the catalytic adhesive 906 does not require pre-drilling the through holes 908 prior to the application of the catalytic adhesive as shown in 804 of fig. 8A. Another advantage is that the resin-rich surface may be formed by the catalytic adhesive 906 instead of the catalytic substrate 904, so that the catalytic particles of the substrate 902 need not have an exclusion zone near the surface as shown in fig. 4, as this is now provided by the catalytic adhesive 906 applied to one or both sides of the substrate 902. Fig. 9C shows a cross-sectional view after the hole 908 is drilled, step 9D shows surface removal 914, and fig. 9E shows electroless plating 916 using the methods previously described.

The foregoing description provides examples of the invention for the purpose of illustration only, and is not intended to limit the scope of the invention to the particular method or structure shown, except as may be explicitly indicated. For example, the sequence of fig. 5A to 5E and 6A to 6G shows a single sided structure with trace channels cut only on the first surface, while the same structure and method can be applied to the second surface layer 505 without loss of generality, as the electroless plating step can be applied to the channels or exposed catalyst on both sides of the plate in a single step. Furthermore, the layers as manufactured in fig. 5A to 5E, 6A to 6G, 8A to 8E, 9A to 9E, 10A to 10I and the through holes of fig. 7A to 7F may be formed on separate layers which are then laminated together into a single board having a mixed layer of catalyzed prepreg and non-catalyzed prepreg, and the scope of the claims in connection with "multi-layer PCB" will be construed to include such structures. Similarly, although the trace structures and via structures of fig. 5A-5E, 6A-6G, 8A-8E, and 7A-7F are shown in combination as they typically appear on a PCB, these examples are for illustration only and are not intended to limit the invention to these structures. For example, in accordance with novel aspects of the process, mounting holes for via components without electrical connections may be formed without connection traces or annular rings.

In this specification, "approximately" is understood to mean less than 4 times or more or less and "substantially" is understood to mean less than 2 times or more or less. The "order of magnitude" of a value includes a range from 0.1 times the value to 10 times the value.

Certain post-processing operations common to printed circuit board manufacture are not shown and may be performed on boards produced according to the new process using prior art methods. Such operations include tin plating for improved solder flow, flash for improved conductivity and reduced etching, solder resist operations, screen printing information (part numbers, reference indicators, etc.) on the circuit board, scoring the finished board or providing a separator tab, etc. Some of these operations may produce improved results when performed on the planarization plate of certain aspects of the present invention. For example, screen printed lettering on traces or vias has traditionally split due to trace and via thicknesses on circuit board surfaces, and these operations will provide excellent results on flat surfaces.

Claims

1. A catalytic laminate having at least one surface enriched in resin compared to other areas of the catalytic laminate;

the catalytic laminate has catalytic particles having a maximum catalytic particle range;

The catalytic laminate has a catalytic particle exclusion zone of 1/2 of the average size of catalytic particles below the at least one surface, the catalytic particles not being present in the catalytic particle exclusion zone;

whereby electroless plating deposits metal on the at least one surface from which surface material is removed and electroless plating deposition does not occur on other portions of the at least one surface.

2. The catalytic laminate of claim 1, wherein the catalytic particles are non-uniform.

3. The catalytic laminate of claim 2, wherein the catalytic particles comprise a catalyst coated filler.

4. A catalytic laminate according to claim 3, wherein the filler is at least one of clay minerals, hydrated aluminosilicates, silica, polysilicates, or high temperature plastics.

5. A catalytic laminate according to claim 3, wherein the filler is kaolinite.

6. A catalytic laminate according to claim 3, wherein the catalytic particles are on the order of 3 μm or less in size.

7. A catalytic laminate according to claim 3, wherein the ratio of catalytic particles to the resin by weight is in the range 8% to 16%.

8. A catalytic laminate according to claim 3, wherein the catalytic particles are silica or kaolin coated with a catalytic material.

9. A catalytic laminate according to claim 3, wherein the catalyst is palladium.

10. The catalytic laminate of claim 3, wherein the catalyst is at least one of palladium (Pd), platinum (Pt), rhodium (Rh), iridium (Ir), nickel (Ni), gold (Au), silver (Ag), cobalt (Co), or copper (Cu), or salts thereof.

11. The catalytic laminate of claim 1, wherein the catalytic particles are uniform.

12. The catalytic laminate of claim 11, wherein the catalytic particles are palladium.

13. The catalytic laminate of claim 11, wherein the catalytic particles are at least one of palladium (Pd), platinum (Pt), rhodium (Rh), iridium (Ir), nickel (Ni), gold (Au), silver (Ag), cobalt (Co), or copper (Cu), or salts thereof.

14. The catalytic laminate of claim 11, wherein the ratio of catalytic particles to the resin by weight is in the range of 8% to 16%.

15. The catalytic laminate of claim 11, wherein a majority of the catalytic particles have a size of less than 25 μιη.

16. A method for forming a catalyzed prepreg laminate having a resin-rich surface that excludes catalytic particles at a depth of exclusion below the resin-rich surface, the method comprising:

Forming a catalyzed resin by blending catalytic particles into a resin and a solvent;

Infusing the catalyzed resin into a fabric;

Grinding the fabric impregnated with the catalyzed resin to a desired first thickness;

Baking the resin infused with the catalytic particles until a majority of the solvent is removed;

Placing the baked catalytic prepreg in a laminator having a flat pressure surface;

heating the catalytic prepreg under vacuum while applying a lamination pressure, changing the temperature of the laminator to provide heating to ramp up to a residence temperature at which the gel point is maintained, maintaining the residence temperature for a residence time sufficient to migrate the catalytic particles away from the outer surface of the catalytic prepreg, and thereafter reducing the temperature in a cooling cycle;

wherein the residence time, the residence temperature, and the lamination pressure are selected such that the catalytic particles are excluded in a region below the resin-rich surface.

17. The method of claim 16, wherein the catalytic particle is at least one of palladium (Pd), platinum (Pt), rhodium (Rh), iridium (Ir), nickel (Ni), gold (Au), silver (Ag), cobalt (Co), or copper (Cu), or salts thereof.

18. The method of claim 16, wherein the resin comprises at least one of an epoxy resin, a polyimide resin, a cyanate ester resin, or a Teflon blended resin.

19. The method of claim 16, wherein the gel temperature is in the range of 120 ℃ to 350 ℃.

20. The method of claim 16, wherein the gel time is in the range of 5 seconds to 15 seconds during the temperature ramp time interval.

21. A catalytic prepreg comprising:

A fabric impregnated with a resin having catalytic particles of less than 25 μm;

The prepreg having at least a first planar surface and the catalytic particles being uniformly distributed in an interior region of the prepreg, the prepreg further having a resin-rich surface excluding the catalytic particles, the resin-rich surface having a depth of 1/2 of an average size of the catalytic particles;

thus, removing material from the resin-rich surface exposes some of the catalytic particles sufficient for electroless plating to occur.

22. The catalytic prepreg of claim 21, wherein the fabric is formed from woven fiberglass.

23. The catalytic prepreg of claim 21, wherein the catalytic particles comprise at least one of palladium (Pd), platinum (Pt), rhodium (Rh), iridium (Ir), nickel (Ni), gold (Au), silver (Ag), cobalt (Co), or copper (Cu), or salts thereof.

24. A catalytic prepreg according to claim 21, wherein the catalytic particles are incorporated into the resin in a proportion in the range of 8% to 16% by weight of the resin.