CN114500767B - Input video source adjusting method and device, video input card and video processing equipment - Google Patents
Input video source adjusting method and device, video input card and video processing equipment Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/268—Signal distribution or switching
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/06—Generation of synchronising signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/08—Separation of synchronising signals from picture signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
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Abstract
The embodiment of the invention relates to an input video source adjusting method, which comprises the following steps: acquiring a clock cycle of an input video source and determining a plurality of continuous clock phases according to the clock cycle; sequentially adjusting the clock phases of the input video source to be the clock phases and sampling the input video source based on the current clock phase in the clock phases to obtain a plurality of sampling data sets; acquiring test reference data of a test reference source; detecting the plurality of sampling data sets according to the test reference data to obtain a plurality of corresponding detection results; determining a target clock phase according to the detection results; and adjusting the clock phase of the input video source to the target clock phase; according to the embodiment, the target clock phase is obtained according to the detection result by determining and detecting the clock phases, so that the dynamic adjustment of the input video source clock phase is realized.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to an input video source adjustment method, an input video source adjustment device, a video input card, and a video processing apparatus.
Background
In the LED industry, a video source is connected with a video input card, then is output to an output card through the video input card, and then is output to an LED display screen for display through the output card.
When different video sources need to be replaced, a user is required to manually modify the clock phase of the video input card so that the video sources can be stably output to the LED display screen, in the prior art, firstly, the video sources are required to be subjected to screen effect test, whether the video sources have problems or not is judged manually, then, the clock phase of the video input card is modified to test out the optimal clock phase, and then, the optimal clock phase is taken as the clock phase of the current video input card and is not changed.
However, because the clock phase of the video input card is fixed, when the video input card is switched to different video sources, the different video sources possibly have compatibility problems after being output by the video input card, the quality output to the LED display screen is not up to standard or stable enough, and the video input card cannot be adjusted in real time, so that the compatibility of the video input card is poor.
Disclosure of Invention
Accordingly, to overcome at least some of the shortcomings and drawbacks of the prior art, embodiments of the present invention provide an input video source adjustment method, an input video source adjustment device, a video input card, and a video processing apparatus.
In one aspect, an input video source adjusting method provided by an embodiment of the present invention includes: acquiring a clock cycle of the input video source and determining a plurality of continuous clock phases according to the clock cycle; sequentially adjusting the clock phases of the input video source to be the clock phases and sampling the input video source based on the current clock phase in the clock phases to obtain a plurality of sampling data sets; acquiring test reference data of a test reference source; detecting the plurality of sampling data sets according to the test reference data to obtain a plurality of detection results in one-to-one correspondence; determining a target clock phase according to the detection results; and adjusting a clock phase of the input video source to the target clock phase.
Because the clock phase is required to be manually determined and fixed in the prior art, after the input source is changed, the adjustment cannot be dynamically performed after the compatibility problem occurs, and the compatibility is poor. According to the invention, firstly, the clock period of the input video source is acquired, a plurality of clock phases are determined, then the clock phases are sequentially and respectively sampled and then detected, and finally, whether the target clock phase is correctly obtained or not is detected, wherein the target clock phase is the optimal clock phase of the input video source, so that the dynamic adjustment of the clock phase of the input video source is realized, and the compatibility of a video input card is improved.
In one embodiment of the invention, the plurality of clock phases includes a first clock phase, the plurality of sample data sets includes a first sample data set including first video data and a first synchronization signal; the sequentially adjusting the clock phases of the input video source to the plurality of clock phases and sampling the input video source based on a current clock phase of the plurality of clock phases to obtain a plurality of sampled data sets includes: adjusting the current clock phase of the input video source to the first clock phase; and sampling the input video source according to the first clock phase to obtain the first video data and the first synchronous signal.
In one embodiment of the present invention, the plurality of detection results includes a first detection result; the detecting the plurality of sampling data sets according to the test reference data to obtain a plurality of detection results corresponding to one respectively includes: comparing whether the test reference data is the same as the first video data or not to obtain a first video data detection result; judging whether the resolutions of the multi-frame continuous pictures of the first synchronous signals in the first sampling data set are the same and/or whether the frame rates are the same to obtain a first synchronous signal detection result; and determining the first detection result according to the first video data detection result and the first synchronous signal detection result.
In one embodiment of the present invention, the determining the target clock phase according to the plurality of detection results includes: judging whether the detection results are correct or not and counting the continuous correct detection results to obtain a count value; and when the count value reaches a correct detection result quantity threshold value, taking the clock phase corresponding to a target detection result in the continuous correct detection results as the target clock phase.
In one embodiment of the invention, the clock period is generated by the resolution of the input video source and the interface chip output mode.
In another aspect, an embodiment of the present invention provides an input video source adjustment device, adapted to perform the input video source adjustment method according to any one of the preceding claims, including: the clock cycle acquisition module is used for acquiring the clock cycle of the input video source and determining a plurality of continuous clock phases according to the clock cycle; the sampling data obtaining module is used for sequentially adjusting the clock phases of the input video source to be the multiple clock phases and sampling the input video source based on the current clock phase in the multiple clock phases so as to obtain multiple sampling data sets; the reference data acquisition module is used for acquiring test reference data of the test reference source; the detection result obtaining module is used for respectively detecting the plurality of sampling data sets according to the test reference data to obtain a plurality of detection results in one-to-one correspondence; the clock phase determining module is used for determining a target clock phase according to the detection results; and the clock phase adjustment module is used for adjusting the clock phase of the input video source to the target clock phase.
In yet another aspect, an embodiment of the present invention provides a first video input interface for accessing an input video source and a test reference source; the communication interface is used for receiving an input video source adjusting instruction; a programmable logic device connecting the first video input interface and the communication interface; wherein the programmable logic device is configured to perform the method for input video source adjustment as described in any one of the preceding claims.
In one embodiment of the present invention, the programmable logic device includes: the device comprises a mixed clock management module, a data sampling module, a data detection module and a mixed clock management configuration module; the mixed clock management configuration module is used for acquiring the input video source adjusting instruction through the communication interface, acquiring the clock period of the input video source and determining a plurality of continuous clock phases according to the clock period; the mixed clock management module is used for sequentially adjusting the clock phases of the input video source into a plurality of clock phases; the data sampling module is used for sampling the input video source based on the current clock phase in the clock phases to obtain a plurality of sampling data sets, and acquiring the test reference data of the test reference source through the first video input interface; the data detection module is used for respectively detecting the plurality of sampling data sets according to the test reference data to obtain a plurality of detection results corresponding to each other one by one; the mixed clock management configuration module is further used for determining the target clock phase according to the detection results; the hybrid clock management module is further configured to adjust a clock phase of the input video source to the target clock phase.
In one embodiment of the present invention, the data detection module includes a video data detection unit and a synchronization signal detection unit; the video data detection unit is used for comparing whether the video data in the plurality of sampling data sets are identical one by one according to the test reference data to obtain a plurality of video data detection results; the synchronous signal detection unit is used for judging whether the resolutions of the multi-frame continuous pictures of the synchronous signals in the plurality of sampling data sets are the same and/or whether the frame rates are the same one by one to obtain a plurality of synchronous signal detection results.
In still another aspect, an embodiment of the present invention provides a video processing apparatus, including: a video input card as claimed in any one of the preceding claims; and the main control card is connected with the communication interface of the video input card.
In yet another aspect, an embodiment of the present invention provides an input video source processing system, including: a processor and a memory coupled to the processor; wherein the memory stores instructions for execution by the processor and the instructions cause the processor to perform operations to perform any of the previously described methods of input video source adjustment.
In yet another aspect, an embodiment of the present invention provides a computer-readable storage medium that is a nonvolatile memory and stores program code that when executed by a computer implements any one of the aforementioned input video source adjustment methods.
From the above, the technical features of the present invention may have one or more of the following advantages:
1. According to the embodiment of the invention, firstly, the clock period of the input video source is acquired, a plurality of clock phases are determined, the clock phases are sequentially and respectively sampled and then detected, and finally, the target clock phase is obtained through the detection result, namely the optimal clock phase of the input video source, so that the dynamic adjustment of the clock phase of the input video source is realized, and the compatibility of a video input card is improved;
2. In the embodiment of the invention, the video input card can use different clock phases by accessing different input video sources, thereby effectively improving the compatibility of the video input card.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart illustrating a method for adjusting an input video source according to a first embodiment of the present invention.
Fig. 2 is a flowchart illustrating specific steps of step S102 in the method for adjusting an input video source shown in fig. 1.
Fig. 3 is a flowchart illustrating a specific step of step S104 in the input video source adjustment method shown in fig. 1.
Fig. 4 is a flowchart showing a specific step of step S105 in the input video source adjustment method shown in fig. 1.
Fig. 5 is a schematic diagram of an input video source adjustment method according to an embodiment of the present invention.
Fig. 6 is a schematic block diagram of an input video source adjusting apparatus according to a second embodiment of the present invention.
Fig. 7A is a schematic structural diagram of a video input card according to a third embodiment of the present invention.
Fig. 7B is a schematic structural diagram of a programmable logic device according to a third embodiment of the present invention.
Fig. 8 is a schematic structural diagram of a video processing apparatus according to a fourth embodiment of the present invention.
Fig. 9 is a schematic structural diagram of an input video source adjusting system according to a fifth embodiment of the present invention.
FIG. 10 is a schematic diagram showing a structure of a computer-readable storage medium according to a sixth embodiment of the present invention
[ Reference numerals description ]
S101-S106, S201-S202, S301-S303, S401-S402: inputting a video source adjusting method;
600: inputting a video source adjusting device; 601: a clock period acquisition module; 602: a sampling data obtaining module; 603: a reference data acquisition module; 604: a detection result obtaining module; 605: a clock phase determination module; 606: a clock phase adjustment module; 6021: a clock phase adjusting unit; 6022: a video source sampling unit; 6041: a video data obtaining unit; 6042: a synchronization signal obtaining unit; 6043: a detection result determination unit; 6051: a count value obtaining unit; 6052: a clock phase determining unit;
700: a video input card; 701: a first video input interface; 703: a communication interface; 704: a programmable logic device; 7041: a hybrid clock management module; 7042: a data sampling module; 7043: a data detection module; 7044: a mixed clock pipeline configuration module; 70431: a video data detection unit; 70432: a synchronization signal detection unit;
800: a video processing device; 801: a video input card; 802: a master control card; 8011: a communication interface;
900: inputting a video source adjusting system; 901: a processor; 903: a memory;
1000: computer readable storage media.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In this embodiment, the input video source adjustment methods are all run in the video input card. The video input card comprises a plurality of interfaces, an interface chip and a programmable logic device.
The plurality of interfaces comprise a video input interface and a communication interface, wherein the video input interface is used for accessing a plurality of input video sources, and the communication interface is used for receiving an input video source adjusting instruction; in this embodiment, the adjustment instruction is a clock phase adjustment instruction, and in other embodiments, the adjustment instruction may be an adjustment frequency instruction or other adjustment function instructions, and different adjustment instructions may be set according to actual situations, which is not limited herein.
The interface chip is used for converting the video source accessed by the video input interface into video data and then inputting the video data into the programmable logic device, and the programmable logic device is used for executing the input video source adjusting method in the embodiment.
[ First embodiment ]
As shown in fig. 1, a first embodiment of the present invention provides an input video source adjustment method, for example, including:
s101, acquiring a clock cycle of an input video source and determining a plurality of continuous clock phases according to the clock cycle;
s102, sequentially adjusting the clock phases of the input video source to be the clock phases and sampling the input video source based on the current clock phase in the clock phases to obtain a plurality of sampling data sets;
S103, acquiring test reference data of a test reference source;
S104, respectively detecting the plurality of sampling data sets according to the test reference data to obtain a plurality of detection results in one-to-one correspondence;
s105, determining a target clock phase according to the detection results;
S106, adjusting the clock phase of the input video source to the target clock phase.
Because the clock phase is required to be manually determined and fixed in the prior art, after the input source is changed, the compatibility problem is solved, the dynamic adjustment is not realized, and the compatibility is poor. According to the invention, firstly, the clock period of the input video source is acquired, a plurality of clock phases are determined, then the clock phases are sequentially and respectively sampled and then detected, and finally, the target clock phase, namely the optimal clock phase of the input video source, is obtained through the detection result, so that the dynamic adjustment of the clock phase of the input video source is realized, and the compatibility is improved.
It should be noted that, for the access sequence of the input video source and the test reference source, for example, before the clock phase adjustment and the data sampling of the input video source, the test reference source is accessed through the video input interface, the test reference data is acquired under the initial clock phase and stored on the video input card, for example, a nonvolatile memory on the video input card or a programmable logic device in the video input card, for example, an internal RAM thereof, is directly stored, then the input video source is accessed again through the video input interface, and the data sampling of the input video source is started, and the dynamic adjustment of the clock phase is performed according to the test reference data of the test reference source obtained by the sampling and the sampling data of the input video source; of course, the method includes that an input video source is accessed through the video input interface, clock phases of the input video source are divided to obtain a plurality of clock phases, the clock phases are adjusted to the current clock phase in the clock phases, the input video source is subjected to data sampling based on the current clock phase, sampling data are recorded, then a test reference source is accessed through the video input interface, test reference data are obtained under the initial clock phase and stored on a video input card, and finally detection and clock phase dynamic adjustment are carried out according to the test reference data of the test reference source obtained through sampling and sampling data of the input video source; even the method can be that an input video source is accessed through a video input interface, clock phases of the input video source are divided to obtain a plurality of clock phases, the clock phases are adjusted to the current clock phase in the clock phases, the input video source is subjected to data sampling based on the current clock phase, sampling data are recorded, a test reference source is accessed through another interface, test reference data are obtained under the initial clock phase and stored on a video input card, and the clock phases are dynamically adjusted according to the test reference data of the test reference source obtained through sampling and the sampling data of the input video source.
The method for adjusting the input video source in this embodiment has a plurality of application scenarios, for example, when the video input card is corrected for the first time before leaving the factory and when the video source is accessed, the problem of compatibility of the video input card is found.
In step S101, a clock cycle of an input video source is acquired and a plurality of continuous clock phases are determined according to the clock cycle, and in this embodiment, one clock cycle is equally divided into a plurality of equal clock phases according to the clock cycle of the input video source; in other embodiments, one clock period is divided into a plurality of unequal clock phases according to the clock period of the input video source, and the method is not limited herein. The clock period is generated by the programmable logic device according to the resolution of the input video source and the output mode of the interface chip.
Wherein, in step S102, the plurality of sampled data sets includes, for example, a plurality of video data and a plurality of synchronization signals, the synchronization signals including: a field sync signal VS, a line sync signal HS, and an effective display data signal DE. The video data is, for example, image data of an input video source, such as data represented in RGB format.
In step S104, the plurality of detection results include, for example: video data detection results and synchronization signal detection results.
In step S106, the clock phase of the input video source is adjusted to the target clock phase, and after the target clock phase is determined, since the divided clock phases are all required to be detected, the current clock phase is the last clock phase of the clock phases, i.e. the current clock phase is adjusted from the last clock phase to the target clock phase in one step. For example, dividing the clock cycle into 32 clock phases equally, and obtaining that the target clock phase is the 18 th clock phase through a plurality of detection results, directly adjusting the clock cycle from the last clock phase, i.e. the 32 th clock phase, of the plurality of clock phases to the 18 th clock phase is equivalent to shifting the clock cycle from the 32 th clock phase to the 18 th clock phase, and completing the phase adjustment work.
In another specific embodiment, as shown in fig. 2, the plurality of clock phases includes a first clock phase, the plurality of sampling data sets includes a first sampling data set, and the first sampling data set includes first video data and a first synchronization signal, and the step S102 includes, for example:
s201, adjusting the current clock phase of the input video source to be the first clock phase;
S202, sampling the input video source according to the first clock phase to obtain the first video data and the first synchronization signal.
In another specific embodiment, as shown in fig. 3, the plurality of detection results includes a first detection result, and the foregoing step 104 includes, for example:
S301, comparing whether the test reference data are identical to the first video data to obtain a first video data detection result;
s302, judging whether the resolutions of the multi-frame continuous pictures of the first synchronous signals in the first sampling data set are the same and/or whether the frame rates are the same to obtain a first synchronous signal detection result;
S303, determining the first detection result according to the first video data detection result and the first synchronous signal detection result.
Judging whether the resolutions of the field synchronization signal VS, the line synchronization signal HS and the effective display data signal DE in the multi-frame continuous pictures are the same and/or whether the frame rates are the same or not; wherein the resolution of the multi-frame continuous picture comprises: judging whether the resolutions of the multiple frames of continuous pictures are the same or not, namely judging whether the data and the quantity of the pixel points in the lines of the frame picture data and/or the columns of the frame picture data are the same or not, and obtaining a first synchronous signal detection result; determining whether the frame rates are the same includes: the time intervals between a preset number of adjacent frames in the input video source are compared over a continuous time, e.g., 250 milliseconds, e.g., the time interval between a first frame and a second frame is compared to the time interval between a second frame and a third frame, to determine if the two time intervals are the same.
In another specific embodiment, as shown in fig. 4, the aforementioned step S105 includes, for example:
S401, judging whether the detection results are correct or not, and counting continuous correct detection results to obtain a count value;
and S402, when the count value reaches a correct detection result quantity threshold, taking a clock phase corresponding to a target detection result in the continuous correct detection results as the target clock phase.
In step S401, the first detection result is determined by the first video data detection result and the first synchronization signal detection result, and when the video data detection result is the same and the synchronization signal detection result is the same, the first detection result is correct, otherwise the first detection result is incorrect.
In step S402, the correct detection result number threshold may be set manually, or may be set by a command sent by the host computer or another host card, for example, it is determined that 15% of the number of the multiple clock phases is used as the correct detection result number threshold, for example, it is determined that the number of the clock phases is 32, and then the correct detection result number threshold is 5.
In step S402, the target detection result is a detection result at an intermediate position among the continuous correct detection results, for example, if the count of the continuous correct detection results is 5 count values, the target detection result is a third detection result in the middle, that is, if the count of the continuous correct detection results is an odd number, the target detection result takes the intermediate value among the count values; if the count of the continuous correct detection results is 6 count values, the target detection result is optionally selected from the third detection result and the fourth detection result in the middle to be used as the target detection result, namely, if the count value of the continuous correct detection result is even, the target detection result takes any one value of the two middle values in the count value.
In order to more clearly understand the present embodiment, the following describes the input video source adjustment method of the present embodiment in detail with reference to the specific embodiment of fig. 5.
In this embodiment, the execution body is a programmable logic device (also referred to as FPGA) in the video input card. Next, the implementation of the method for adjusting an input video source according to the embodiment of the present invention will be described in detail.
As shown in fig. 5, an embodiment of the present invention provides a specific method for adjusting an input video source, for example, including:
the FPGA acquires an input video source adjustment instruction, where the input video source adjustment instruction may be sent by an upper computer, or may be an adjustment instruction issued by a main control card, and may be determined according to an actual situation, and the specific application is not limited herein.
The clock period of the input video source is then obtained according to the input video source adjustment instruction and divided equally into a plurality of consecutive clock phases, in this embodiment, the clock period of the input video source is divided equally into a plurality of consecutive clock phases, for example, one clock period of the input video source is divided equally into 32 consecutive clock phases, for example, a first clock phase, a second clock phase, a third clock phase, and so on.
The FPGA sequentially adjusts the clock phases of the input video source into 32 continuous clock phases, samples video data and samples synchronous signals of the input video source based on the current clock phase in the 32 clock phases, for example, adjusts the clock phases into a first clock phase, samples the input video source based on the first clock phase to obtain first video data and first synchronous signals respectively, adjusts the clock phases into a second clock phase, samples the clock phases based on the second clock phase to obtain second video data and second synchronous signals, sequentially samples the 32 clock phases to obtain 32 sampling data sets and records, and each sampling data set comprises video data and synchronous signals. The sampling synchronization signals are three signals, i.e., the collected field synchronization signal VS, the line synchronization signal HS, and the effective display data signal DE, and in other embodiments, the collected synchronization signals may be other synchronization signals, which is not limited herein. The video data is image data of an input video source, for example, image data expressed in RGB format.
After the FPGA performs video data sampling and synchronous signal sampling on the input video source based on the current clock phase in the 32 clock phases, judging the current clock phase, judging whether the current clock phase is detected by 32 clock phases, for example, the current clock phase is the 32 th clock phase, after the FPGA performs video data sampling and synchronous signal sampling on the input video source based on the 32 th clock phase, judging that the current 32 th clock phase is detected by 32 clock phases, determining a target clock phase by the FPGA according to 32 detection results, otherwise, continuously adjusting the clock phase of the input video source by the FPGA and detecting.
The FPGA acquires test reference data of a test reference source. The test reference source at this time may be, for example, image data of a test image sent by an external device such as a host computer, and stored on the video input card such as a non-volatile memory thereon. The test image may be, for example, a still image for detecting video data in a plurality of sampled data sets. The test reference data is video data acquired by the test reference source through a first clock phase of 32 clock phases, and then whether a plurality of video data acquired by the input video source through the 32 clock phases are respectively identical with the test reference data or not is compared to obtain a video data detection result, wherein the video data detection result comprises: the current video data is the same as the test reference data or the current video data is the same as the test reference data, the current video data is obtained by sampling the input video source through the current clock phase in the 32 clock phases, for example, the current video data is 01010101, the test reference data is 01010111, the current video data and the test reference data are compared to obtain different detection results of the current video data, if the current video data is 01010101, the test reference data is 01010101, and the current video data and the test reference data are compared to obtain the same detection results of the current video data.
Then, judging the frame rate and/or resolution and the like of the three sampled synchronous signals, and then obtaining a synchronous signal detection result, wherein the frame rate is judged by comparing the time intervals among a preset number of adjacent frame pictures in an input video source, such as the time interval between a first frame picture and a second frame picture and the time interval between the second frame picture and a third frame picture, in 250 milliseconds continuously, and judging whether the time intervals are the same or not, if so, the synchronous signal detection result is the same, namely the synchronous signal is stable; if the detection results are different, judging that the detection results of the synchronous signals are different, namely the synchronous signals are unstable, wherein the error of the time interval between the detection results and the synchronous signals is within 0.01%, and if the detection results are different, the time interval between the detection results and the synchronous signals is the same, otherwise, the detection results are different; the 250 milliseconds can be set by a user, and can also be set by an upper computer or a main control card; the resolution includes a horizontal resolution and a vertical resolution, and the determination of whether the resolutions of the frames of continuous pictures are the same may determine the horizontal resolution and/or the vertical resolution of the frames of continuous pictures, and may set a determination condition according to an actual situation, which is not limited herein. The judging condition of the resolution is whether the data and the number of the pixel points in the row of the frame picture data and/or the column of the frame picture data are the same or not under the condition of continuous multi-frame pictures, if the data and the number of the pixel points are the same, the synchronous signal detection result is judged to be the same, namely the synchronous signal is stable; if the synchronous signals are different, judging that the synchronous signal detection results are different, namely that the synchronous signals are unstable. When the judging result of the synchronous signals is the same, namely the time intervals are the same and the pixel points of the rows of the frame picture data and/or the columns of the frame picture data are the same; when the judging result of the synchronous signals is different, namely the time intervals are different or the pixel points of the rows of the frame picture data and/or the columns of the frame picture data are different, the synchronous signals are obtained; then determining the detection result according to the video data detection result and the synchronous signal detection result, and when the detection result is correct, namely the video data detection result is the same, and the synchronous signal detection result is the same; when the detection result is incorrect, namely, any one of the video data detection result or the synchronous signal detection result is different.
After the FPGA obtains the detection result, it is determined whether the detection result is correct, for example, when the video data detection result is the same and the synchronization signal detection result is the same, it is determined that the detection result is correct; when any one of the video data detection result or the synchronous signal detection result is different, the detection result is judged to be incorrect.
When the detection result is judged to be correct, counting the correct detection result to obtain a count value, and when the count value reaches a correct detection result quantity threshold, taking a clock phase corresponding to a target detection result in continuous correct detection results as the target clock phase, wherein the target detection result is a detection result in a middle position in the continuous correct detection results; the correct detection result number threshold may be set manually, or may be set by a command sent by the host computer or another host card, for example, it is determined that 15% of the number of the plurality of clock phases is used as the correct detection result number threshold, for example, the determined clock phases are 32, the correct detection result number threshold is 5, when it is determined that the detection results are correct and all of the continuous 5 detection results are correct, the clock phase corresponding to the middle result of the continuous 5 detection results is used as the target clock phase, when the continuous correct detection result is 5, the target detection result is the middle third detection result, the target clock phase is the clock phase corresponding to the third detection result, and when the count value of the continuous correct detection result is an odd number, the target detection result takes the middle value of the count value; if the count of the continuous correct detection results is 6 count values, the target detection result is optionally selected from the third detection result and the fourth detection result in the middle to be used as the target detection result, namely, if the count value of the continuous correct detection result is even, the target detection result takes any one value of the two middle values in the count value.
After the FPGA obtains the target clock phase, the FPGA adjusts the clock period to the target clock phase, and as a plurality of equally divided clock phases are required to be detected, the current clock phase is the last clock phase in the plurality of clock phases during adjustment, namely, the current clock phase is adjusted to the target clock phase from the last clock phase in one step. For example, dividing the clock cycle into 32 clock phases, obtaining 32 detection results through the 32 clock phases, and determining that the target clock phase is the 18 th clock phase from the 32 detection results, so that the clock cycle is directly adjusted from the last clock phase, i.e. the 32 th clock phase, in the 32 th clock phase to the 18 th clock phase, which is equivalent to shifting the clock cycle from the 32 th clock phase to the 18 th clock phase, thereby completing the process of dynamically adjusting the clock phases. In summary, the invention firstly obtains the clock period of the input video source, determines a plurality of continuous clock phases according to the clock period, sequentially and respectively samples the plurality of continuous clock phases, then detects the continuous clock phases, and finally obtains the target clock phase through the detection result, wherein the target clock phase is the optimal clock phase output by the FPGA, thereby realizing the dynamic adjustment process of the clock phase, improving the compatibility of the video input card, and simultaneously achieving the effect of reducing the labor cost through the automatic adjustment process.
[ Second embodiment ]
As shown in fig. 6, a second embodiment of the present invention provides an input video source adjusting apparatus 600, for example, including: a clock period acquisition module 601, a sampling data obtaining module 602, a reference data acquisition module 603, a detection result obtaining module 604, a clock phase determining module 605 and a clock phase adjusting module 606.
The clock cycle obtaining module 601 is configured to obtain a clock cycle of an input video source and determine a plurality of continuous clock phases according to the clock cycle; a sampling data obtaining module 602, configured to sequentially adjust clock phases of the input video source to the plurality of clock phases and sample the input video source based on a current clock phase of the plurality of clock phases, so as to obtain a plurality of sampling data sets; a reference data acquisition module 603, configured to acquire test reference data of a test reference source; the detection result obtaining module 604 is configured to detect the plurality of sampling data sets according to the test reference data to obtain a plurality of detection results corresponding to each other one by one; a clock phase determining module 605, configured to determine a target clock phase according to the plurality of detection results; a clock phase adjustment module 606 is configured to adjust a clock phase of the input video source to the target clock phase.
Further, the present embodiment provides a sampled data obtaining module 602, where the plurality of clock phases includes a first clock phase, the plurality of sampled data sets includes a first sampled data set, the first sampled data set includes first video data and a first synchronization signal, and the sampled data obtaining module 602 is specifically configured to: adjusting the current clock phase of the input video source to the first clock phase; and sampling the input video source according to the first clock phase to obtain the first video data and the first synchronous signal.
Further, the present embodiment provides a detection result obtaining module 604, where the plurality of detection results includes a first detection result, and the detection result obtaining module 604 is specifically configured to: comparing whether the test reference data is the same as the first video data or not to obtain a first video data detection result; judging whether the resolutions of the multi-frame continuous pictures of the first synchronous signals in the first sampling data set are the same and/or whether the frame rates are the same to obtain a first synchronous signal detection result; and determining the first detection result according to the first video data detection result and the first synchronous signal detection result.
Further, the present embodiment provides a clock phase determining module 605, specifically configured to: judging whether the detection results are correct or not and counting the continuous correct detection results to obtain a count value; and when the count value reaches a correct detection result quantity threshold value, taking the clock phase corresponding to a target detection result in the continuous correct detection results as the target clock phase. The target detection result is a detection result in a middle position in the continuous correct detection results.
Further, the clock period is generated by the resolution of the input video source and the output mode of the interface chip.
The method for adjusting the input video source implemented by the input video source adjusting apparatus 600 according to the present embodiment is as described in the foregoing first embodiment, and thus will not be described in detail herein. Optionally, each module in the second embodiment and the other operations or functions described above are respectively for implementing the method in the first embodiment of the present invention, and the beneficial effects of this embodiment may be referred to the description of the beneficial effects of the first embodiment, which is not repeated herein.
[ Third embodiment ]
As shown in fig. 7A, a third embodiment of the present invention provides a video input card 700, comprising: a first video input interface 701, a communication interface 703, and a programmable logic device 704.
The first video input interface 701 is used for accessing an input video source and accessing a test reference source; for the access of the input video source and the test reference source, for example, before performing clock phase adjustment and data sampling of the input video source, the test reference source is accessed first, test reference data is acquired in an initial clock phase, and is stored on a video input card, for example, a nonvolatile memory connected with the programmable logic device 704, or is directly stored in an internal RAM of the programmable logic device 704, for example, then the input video source is accessed again through the first video input interface 701, and data sampling of the input video source is started, and dynamic adjustment of clock phase is performed according to the test reference data of the test reference source obtained by sampling and sampling data of the input video source; of course, it may also be that an input video source is accessed through the first video input interface 701, clock phase division is started on the input video source and is adjusted to a current clock phase in a plurality of clock phases, data sampling is performed on the input video source based on the current clock phase and sampling data is recorded, then a test reference source is accessed through the first video input interface 701, test reference data is obtained under the initial clock phase and is stored on a video input card, for example, a nonvolatile memory connected with the programmable logic device 704, or is directly stored in the programmable logic device 704, for example, an internal RAM thereof, and finally dynamic adjustment of clock phase is performed according to the test reference data of the test reference source obtained by sampling and the sampling data of the input video source; even, the method may further access an input video source through the first video input interface 701, start to perform clock phase division on the input video source and adjust the input video source to a current clock phase in a plurality of clock phases, perform data sampling on the input video source based on the current clock phase and record sampling data, access a test reference source through another interface, such as a video input interface or a communication interface, obtain test reference data under the initial clock phase, and store the test reference data on a video input card, such as a nonvolatile memory connected with the programmable logic device 704, or directly store the test reference data in the programmable logic device 704, such as an internal RAM thereof, and perform dynamic adjustment of the clock phase according to the test reference data of the test reference source obtained by sampling and the sampling data of the input video source.
The communication interface 703 is configured to receive an input video source adjustment instruction; the programmable logic device 704 connects the first video input interface 701 and the communication interface 703.
Wherein the programmable logic device is configured to perform the input video source adjustment method as described in the first embodiment above.
The video input card 700 may further include a second video input interface, a third video input interface, and so on, and a plurality of video input interfaces may be provided on the video input card 700 according to actual needs, which is not limited herein.
Still further, as shown in fig. 7B, the programmable logic device 704 includes: the hybrid clock management module 7041, the data sampling module 7042, the data detection module 7043, and the hybrid clock management configuration module 7044.
Wherein the mixed clock management configuration module 7044 is configured to obtain the input video source adjustment instruction through the communication interface 703, obtain the clock period of the input video source, and determine the continuous multiple clock phases according to the clock period; the mixed clock management module 7041 is configured to sequentially adjust the clock phases of the input video source to the plurality of clock phases; the data sampling module 7042 is configured to sample the input video source based on the current clock phase of the plurality of clock phases, so as to obtain a plurality of sampling data sets, and acquire the test reference data of the test reference source through the first video input interface; the data detection module 7043 is configured to detect the plurality of sampling data sets according to the test reference data to obtain a plurality of detection results corresponding to each other one by one; the mixed clock management configuration module 7044 is further configured to determine the target clock phase according to the plurality of detection results; the hybrid clock management module 7041 is further configured to adjust a clock phase of the input video source to the target clock phase.
Further, as shown in fig. 7B, the data detecting module 7043 includes a video data detecting unit 70431 and a synchronization signal detecting unit 70432; the video data detecting unit 70431 is configured to compare whether video data in the plurality of sampling data sets are the same one by one according to the test reference data to obtain a plurality of video data detection results; the synchronization signal detection unit 70432 is configured to determine whether the resolutions of the multiple frames of continuous pictures of the synchronization signals in the multiple sampling data sets are the same and/or whether the frame rates are the same one by one to obtain multiple synchronization signal detection results.
[ Fourth embodiment ]
As shown in fig. 8, a video processing apparatus 800 according to a fourth embodiment of the present invention includes: a video input card 801; a main control card 802 connected to the communication interface 8011 of the video input card 801;
The video input card 801 is, for example, the video input card of the foregoing third embodiment.
[ Fifth embodiment ]
As shown in fig. 9, an input video source adjustment system 900 according to a fifth embodiment of the present invention includes: a processor 901 and a memory 903; wherein the memory 903 stores instructions executed by the processor 901, and the processor 901 executes the instructions to perform the input video source adjustment method described in the foregoing first embodiment.
[ Sixth embodiment ]
As shown in fig. 10, a sixth embodiment of the present invention provides a computer readable storage medium 1000, which is a nonvolatile memory and stores computer readable instructions, where the computer readable instructions are executed by one or more processors to perform the input video source adjustment method described in the foregoing first embodiment.
In addition, it should be understood that the foregoing embodiments are merely exemplary illustrations of the present invention, and the technical solutions of the embodiments may be arbitrarily combined and matched without conflict in technical features, contradiction in structure, and departure from the purpose of the present invention.
In the several embodiments provided herein, it should be understood that the disclosed systems, devices, and/or methods may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and the division of the units/modules is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or modules may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units/modules described as separate units may or may not be physically separate, and units/modules may or may not be physically units, may be located in one place, or may be distributed on multiple network units. Some or all of the units/modules may be selected according to actual needs to achieve the purpose of the embodiment.
In addition, each functional unit/module in the embodiments of the present invention may be integrated in one processing unit/module, or each unit/module may exist alone physically, or two or more units/modules may be integrated in one unit/module. The integrated units/modules may be implemented in hardware or in hardware plus software functional units/modules.
The integrated units/modules implemented in the form of software functional units/modules described above may be stored in a computer readable storage medium. The software functional units described above are stored in a storage medium and include instructions for causing one or more processors of a computer device (which may be a personal computer, a server, or a network device, etc.) to perform some steps of the methods described in the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory RAM), a magnetic disk, or an optical disk, etc., which can store program codes.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A method of input video source conditioning comprising:
acquiring a clock cycle of an input video source and determining a plurality of continuous clock phases according to the clock cycle;
Sequentially adjusting the clock phases of the input video source to be the clock phases and sampling the input video source based on the current clock phase in the clock phases to obtain a plurality of sampling data sets;
Acquiring test reference data of a test reference source; the test reference data are video data acquired by the test reference source through a first clock phase in the plurality of clock phases;
Detecting the plurality of sampling data sets according to the test reference data to obtain a plurality of detection results in one-to-one correspondence;
determining a target clock phase according to the detection results; and
Adjusting the clock phase of the input video source to the target clock phase;
wherein said adjusting the clock phase of the input video source to the target clock phase comprises:
and determining the current clock cycle as the last clock cycle of the plurality of clock phases, and shifting the position of the last clock cycle to the position of the target clock phase.
2. The method of claim 1, wherein the plurality of clock phases comprises a first clock phase, the plurality of sample data sets comprises a first sample data set comprising first video data and a first synchronization signal; the sequentially adjusting the clock phases of the input video source to the plurality of clock phases and sampling the input video source based on a current clock phase of the plurality of clock phases to obtain a plurality of sampled data sets includes:
adjusting the current clock phase of the input video source to the first clock phase;
and sampling the input video source according to the first clock phase to obtain the first video data and the first synchronous signal.
3. The method of claim 2, wherein the plurality of detection results includes a first detection result; the detecting the plurality of sampling data sets according to the test reference data to obtain a plurality of detection results corresponding to one respectively includes:
comparing whether the test reference data is the same as the first video data or not to obtain a first video data detection result;
Judging whether the resolutions of the multi-frame continuous pictures of the first synchronous signals in the first sampling data set are the same and/or whether the frame rates are the same to obtain a first synchronous signal detection result; and
And determining the first detection result according to the first video data detection result and the first synchronous signal detection result.
4. The method of claim 1, wherein determining a target clock phase based on the plurality of detection results comprises:
Judging whether the detection results are correct or not and counting the continuous correct detection results to obtain a count value;
And when the count value reaches the number threshold of the correct detection results, taking the clock phase corresponding to the target detection result in the continuous correct detection results as the target clock phase.
5. The method of claim 1, wherein the clock period is a clock period generated by a resolution of the input video source and an interface chip output mode.
6. An input video source adjustment device, for implementing the input video source adjustment method according to any one of claims 1 to 5, comprising:
the clock cycle acquisition module acquires a clock cycle of an input video source and determines a plurality of continuous clock phases according to the clock cycle;
the sampling data obtaining module is used for sequentially adjusting the clock phases of the input video source to be the multiple clock phases and sampling the input video source based on the current clock phase in the multiple clock phases so as to obtain multiple sampling data sets;
the reference data acquisition module is used for acquiring test reference data of the test reference source;
The detection result obtaining module is used for respectively detecting the plurality of sampling data sets according to the test reference data to obtain a plurality of detection results in one-to-one correspondence;
The clock phase determining module is used for determining a target clock phase according to the detection results; and
And the clock phase adjusting module is used for adjusting the clock phase of the input video source to the target clock phase.
7. A video input card, comprising:
the first video input interface is used for accessing an input video source and a test reference source;
the communication interface is used for receiving an input video source adjusting instruction;
A programmable logic device connecting the first video input interface and the communication interface;
wherein the programmable logic device is configured to perform the input video source conditioning method of any of the preceding claims 1 to 5.
8. The video input card of claim 7, wherein the programmable logic device comprises: the device comprises a mixed clock management module, a data sampling module, a data detection module and a mixed clock management configuration module;
the mixed clock management configuration module is used for acquiring the input video source adjusting instruction through the communication interface, acquiring the clock period of the input video source and determining a plurality of continuous clock phases according to the clock period;
The mixed clock management module is used for sequentially adjusting the clock phases of the input video source into a plurality of clock phases;
The data sampling module is used for sampling the input video source based on the current clock phase in the clock phases to obtain a plurality of sampling data sets, and acquiring the test reference data of the test reference source through the first video input interface;
the data detection module is used for respectively detecting the plurality of sampling data sets according to the test reference data to obtain a plurality of detection results corresponding to each other one by one;
the mixed clock management configuration module is further used for determining the target clock phase according to the detection results;
the hybrid clock management module is further configured to adjust a clock phase of the input video source to the target clock phase.
9. The video input card of claim 8, wherein the data detection module comprises a video data detection unit and a synchronization signal detection unit;
The video data detection unit is used for comparing whether the video data in the plurality of sampling data sets are identical one by one according to the test reference data to obtain a plurality of video data detection results;
the synchronous signal detection unit is used for judging whether the resolutions of the multi-frame continuous pictures of the synchronous signals in the plurality of sampling data sets are the same and/or whether the frame rates are the same one by one to obtain a plurality of synchronous signal detection results.
10. A video processing apparatus, comprising:
a video input card as claimed in any one of claims 7 to 9;
and the main control card is connected with the communication interface of the video input card.
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