CN114499497A - A kind of strong pull-down latch structure level conversion circuit - Google Patents

Abstract

The invention discloses a strong pull-down latch structure level switching circuit, which comprises a two-pole input phase inverter, a strong pull-down latch circuit and a DLS output phase inverter; the strong pull-down latch circuit comprises two part structures consisting of four PMOS transistors and two NMOS transistors, each part structure comprises an RVT pull-up PMOS transistor, an HVT middle pull-up PMOS transistor and an LVT pull-down NMOS transistor, and the grid electrode of each part RVT pull-up PMOS transistor is connected with the drain electrode of the other part LVT pull-down NMOS transistor to form the strong pull-down latch circuit; the two-pole input inverter comprises two inverters in cascade connection; the DLS output inverter serves as an output inverter circuit. The invention ensures the reliability of converting the ultralow core voltage into the I/O voltage under the advanced process, and has the advantages of wide level conversion range, high conversion speed and high reliability.

Description

A kind of strong pull-down latch structure level conversion circuit

technical field

The invention relates to the field of level conversion circuits for integrated chips, in particular to a level conversion circuit with a strong pull-down latch structure.

Background technique

In order to integrate more functions on the integrated chip, improve the reliability of the integrated circuit, reduce the power consumption of the integrated circuit, and improve the performance of the integrated circuit, MOSFET (Metal-Oxide-Semiconductor Field-EffectTransistor, metal-oxide semiconductor field effect The process size of transistors) continues to shrink; however, with the reduction of the MOSFET process size, the operating voltage of the integrated chip must be reduced accordingly to avoid the hot carrier effect and the breakdown of the gate oxide, so most integrated chips in advanced processes are operate at lower voltage levels. However, the operating voltage of the off-chip circuit system has not changed much, and the mainstream I/O output level is still 3.3V, which leads to the problem of incompatibility between the on-chip and on-chip voltages, which requires level conversion, and the I/O unit One of the main problems to be solved is level conversion, so the level conversion circuit becomes a bridge between the low voltage of the chip core and the external I/O voltage. Because the core voltage of the chip has mostly been reduced to below 1V under the advanced technology, the traditional level shift circuit (as shown in Figure 1) can no longer work normally. The I/O tube is still used, that is, the threshold voltage Vth of the 3.3V NMOS still maintains the original value, which causes the 3.3V NMOS to not work normally during the pull-down process. Therefore, it is necessary to develop a strong pull-down latch structure level. conversion circuit.

As shown in Figure 1, the traditional level shift circuit mainly includes three parts: input inverter, half-latch circuit and output inverter. Because of the strong competing currents between the pull-up and pull-down networks of the semi-latch circuit, translating the signal from the low-voltage domain to the higher-voltage domain requires an order of magnitude increase in the size of the pull-down transistor to overcome the strength of the pull-up network , which results in additional consumption of area, which is unrealistic and unacceptable. At the same time, Figure 1 uses traditional CMOS transistors as output inverters, and their leakage power consumption and short-circuit power consumption during signal inversion will also cause a lot of power waste, and only one-stage CMOS inverters are used as input. , it is difficult to ensure the input voltage level of the semi-latch circuit in the latter stage, and even affect the function of the circuit.

In view of this, the present invention is proposed.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a level conversion circuit with a strong pull-down latch structure to solve the above-mentioned technical problems existing in the prior art. The invention solves the problem that the core voltage cannot be pulled down normally, reduces the power consumption of the rear stage, ensures the reliability of converting the ultra-low core voltage into the I/O voltage under the advanced technology, and has the range of level conversion. It has the advantages of wide range, fast conversion speed and high reliability.

The purpose of this invention is to realize through the following technical solutions:

A level conversion circuit with a strong pull-down latch structure includes a two-pole input inverter, a strong pull-down latch circuit and a DLS output inverter; the input end of the two-pole input inverter is the strong pull-down latch structure circuit. The input terminal IN of the level conversion circuit; the output terminal of the DLS output inversion is the output terminal OUT of the level conversion circuit of the strong pull-down latch structure;

The strong pull-down latch circuit includes four PMOS transistors and two NMOS transistors, the four PMOS transistors are respectively defined as M5, M6, M8, and M9, and the two NMOS transistors are respectively defined as M7 and M10; the PMOS transistors M5 and PMOS transistor M8 is an RVT pull-up PMOS transistor, PMOS transistor M6 and PMOS transistor M9 are HVT middle pull-up PMOS transistors, NMOS transistor M7 and NMOS transistor M10 are LVT pull-down NMOS transistors; the source and substrate of PMOS transistor M5 are connected to high The power supply voltage VDDH of the voltage domain is electrically connected, the drain of the PMOS transistor M5 and the source of the PMOS transistor M6 are electrically connected to the input S of the DLS output inverter, the gate of the PMOS transistor M5 and the drain of the PMOS transistor M9 , the drain of the NMOS transistor M10 is electrically connected; the source and the substrate of the PMOS transistor M8 are electrically connected to the power supply voltage VDDH of the high voltage domain, the drain of the PMOS transistor M8 is electrically connected to the source of the PMOS transistor M9, and the PMOS transistor M8 The gate of the PMOS transistor M6 is electrically connected to the drain of the NMOS transistor M7; the gate of the PMOS transistor M6 and the gate of the NMOS transistor M7 are electrically connected to the second-stage output terminal B of the two-pole input inverter The gate of the PMOS transistor M9 and the gate of the NMOS transistor M10 are both electrically connected to the first-stage output terminal A of the two-stage input inverter; the source of the NMOS transistor M7 is electrically connected to the source of the NMOS transistor M10 at the low level VSS; the substrate of the PMOS transistor M6 is electrically connected to the substrate of the PMOS transistor M9 and is electrically connected to the positive level Vb1; the substrate of the NMOS transistor M7 is electrically connected to the substrate of the NMOS transistor M10 and It is electrically connected to the positive level Vb2.

Preferably, the structure of the two-pole input inverter includes a first-stage CMOS inverter circuit and a second-stage CMOS inverter circuit; the first-stage CMOS inverter circuit includes a PMOS transistor M1 and an NMOS transistor M2; The source of the PMOS transistor M1 is electrically connected to the power supply voltage VDDL in the low voltage domain, the gate of the PMOS transistor M1 is electrically connected to the gate of the NMOS transistor M2 as the input terminal of the two-pole input inverter, and the drain of the PMOS transistor M1 The pole is electrically connected to the drain of the NMOS transistor M2 as the first-stage output terminal A of the two-pole input inverter, and the source of the NMOS transistor M2 is electrically connected to the low-level VSS; the second-stage CMOS inverter The circuit includes a PMOS transistor M3 and an NMOS transistor M4; the source of the PMOS transistor M3 is electrically connected to the power supply voltage VDDL of the low voltage domain, and the gate of the PMOS transistor M3 is electrically connected to the gate of the NMOS transistor M4 and is inversely connected to the two-pole input. The first stage output terminal A of the inverter is electrically connected, the drain of the PMOS transistor M3 and the drain of the NMOS transistor M4 are electrically connected together as the second stage output terminal B of the two-pole input inverter, and the source of the NMOS transistor M4 Electrically connected to low level VSS.

Preferably, the structure of the DLS output inverter includes two NMOS transistors and two PMOS transistors, the two NMOS transistors are respectively defined as M11 and M13, and the two PMOS transistors are respectively defined as M12 and M14; the NMOS transistor M11 The drain of the NMOS transistor M11 is electrically connected to the power supply voltage VDDH of the high-voltage domain, the source of the NMOS transistor M11 is electrically connected to the source of the PMOS transistor M12, and the gate of the PMOS transistor M12 and the gate of the NMOS transistor M13 are electrically connected together as the DLS The input terminal S of the output inverter, the source of the NMOS transistor M13 is electrically connected to the source of the PMOS transistor M14, the drain of the PMOS transistor M14 is electrically connected to the low level VSS, the gate of the NMOS transistor M11, the gate of the PMOS transistor M12 The drain, the drain of the NMOS transistor M13, and the gate of the PMOS transistor M14 are electrically connected together as the output end of the DLS output inverter; the NMOS transistor M11, the NMOS transistor M13, the PMOS transistor M12, and the PMOS transistor M14 are all RVT transistors The substrates of NMOS transistor M11 and NMOS transistor M13 are both electrically connected to the power supply voltage VDDH in the high voltage domain, and the substrates of PMOS transistor M12 and PMOS transistor M14 are electrically connected to low level VSS.

Preferably, the input terminal IN of the strong pull-down latch structure level conversion circuit is electrically connected to the in-chip port; the output terminal OUT of the strong pull-down latch structure level conversion circuit is electrically connected to the external circuit of the chip.

Compared with the prior art, the present invention adopts a strong pull-down latch circuit with special structure to solve the problem that the core voltage cannot be pulled down normally, and adopts DLS (Dynamic Leakage Suppression, dynamic leakage suppression) output in the high voltage domain. The inverter is used as the output inverter, which reduces the power consumption of the subsequent stage, and at the same time, the two-pole input inverter composed of two inverters cascaded is used as the input inverter, thereby ensuring that the present invention can exceed the advanced technology. The reliability of converting the low core voltage into the I/O voltage enables the invention to have the advantages of wide level conversion range, fast conversion speed and high reliability.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without any creative effort.

1 is a schematic structural diagram of a conventional level conversion circuit in the prior art;

2 is a schematic structural diagram of a strong pull-down latch level conversion circuit provided in Embodiment 1 of the present invention;

In FIG. 2, HVT refers to high threshold voltage, RVT refers to common threshold voltage, and LVT refers to low threshold voltage.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention; obviously, the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments, which do not It does not constitute a limitation of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present invention.

First a description of terms that may be used in this article:

The terms "comprising", "comprising", "containing", "having", or other descriptions with similar meanings, should be construed as non-exclusive inclusions. For example: including certain technical characteristic elements (such as raw materials, components, ingredients, carriers, dosage forms, materials, dimensions, parts, components, mechanisms, devices, steps, processes, methods, reaction conditions, processing conditions, parameters, algorithms, signals, data, products or products, etc.), should be construed to include not only a certain technical feature element explicitly listed, but also other technical feature elements known in the art that are not explicitly listed.

The level conversion circuit of the strong pull-down latch structure provided by the present invention will be described in detail below. Contents that are not described in detail in the embodiments of the present invention belong to the prior art known to those skilled in the art. If the specific conditions are not indicated in the examples of the present invention, it is carried out according to the conventional conditions in the art or the conditions suggested by the manufacturer. The reagents or instruments used in the examples of the present invention without the manufacturer's indication are conventional products that can be purchased from the market.

Example 1

As shown in FIG. 2 , the present invention provides a level shift circuit with a strong pull-down latch structure, including a bipolar input inverter, a strong pull-down latch circuit and a DLS output inverter.

The input terminal of the two-pole input inverter is the input terminal IN of the level conversion circuit of the strong pull-down latch structure; the output terminal of the DLS output inversion is the output of the level conversion circuit of the strong pull-down latch structure terminal OUT; the input terminal IN of the strong pull-down latch structure level conversion circuit is electrically connected to the port in the chip; the output terminal OUT of the strong pull-down latch structure level conversion circuit is electrically connected to the external circuit of the chip.

The strong pull-down latch circuit includes four PMOS transistors and two NMOS transistors, the four PMOS transistors are respectively defined as M5, M6, M8, and M9, and the two NMOS transistors are respectively defined as M7 and M10. PMOS transistor M5 and PMOS transistor M8 are RVT pull-up PMOS transistors, PMOS transistor M6 and PMOS transistor M9 are HVT middle pull-up PMOS transistors, NMOS transistor M7 and NMOS transistor M10 are LVT pull-down NMOS transistors. The source and substrate of the PMOS transistor M5 are both electrically connected to the power supply voltage VDDH in the high-voltage domain, the drain of the PMOS transistor M5 and the source of the PMOS transistor M6 are electrically connected to the input terminal S of the DLS output inverter, and the PMOS transistor M5 is electrically connected to the input terminal S of the DLS output inverter. The gate of the transistor M5 is electrically connected to the drain of the PMOS transistor M9 and the drain of the NMOS transistor M10; the source and the substrate of the PMOS transistor M8 are both electrically connected to the power supply voltage VDDH of the high voltage domain, and the drain of the PMOS transistor M8 is electrically connected to the The source of the PMOS transistor M9 is electrically connected, the gate of the PMOS transistor M8 is electrically connected to the drain of the PMOS transistor M6 and the drain of the NMOS transistor M7; the gate of the PMOS transistor M6 and the gate of the NMOS transistor M7 are electrically connected to the The second-stage output terminal B of the two-stage input inverter; the gate of the PMOS transistor M9 and the gate of the NMOS transistor M10 are both electrically connected to the first-stage output terminal A of the two-stage input inverter; the NMOS transistor M7 The source and the source of the NMOS transistor M10 are both electrically connected to the low level VSS; the substrate of the PMOS transistor M6 is electrically connected to the substrate of the PMOS transistor M9 and is electrically connected to the positive level Vb1; the substrate of the NMOS transistor M7 It is electrically connected to the substrate of the NMOS transistor M10 and is electrically connected to the positive level Vb2.

Specifically, the level conversion circuit of the strong pull-down latch structure may include the following embodiments:

(1) The input terminal of the two-pole input inverter is the input terminal IN of the level conversion circuit of the strong pull-down latch structure; the input terminal IN of the level conversion circuit of the strong pull-down latch structure is electrically connected to the in-chip port. connect. The two-pole input inverter includes two inverter circuits composed of CMOS transistors, and the two inverters are in a cascade relationship. The specific structure of the two-pole input inverter includes a first-stage CMOS inverter circuit and a second-stage CMOS inverter circuit. The first-stage CMOS inverter circuit includes a PMOS transistor M1 and an NMOS transistor M2; the source of the PMOS transistor M1 is electrically connected to the power supply voltage VDDL of the low voltage domain, and the gate of the PMOS transistor M1 is electrically connected to the gate of the NMOS transistor M2. connected together as the input end of the first-stage CMOS inverter circuit (that is, the input end of the two-pole input inverter, and also the input end IN of the level conversion circuit of the strong pull-down latch structure described in Embodiment 1 of the present invention, The input terminal IN is electrically connected to the in-chip port), the drain of the PMOS transistor M1 and the drain of the NMOS transistor M2 are electrically connected together as the first-stage output terminal A of the two-pole input inverter, and the source of the NMOS transistor M2 Electrically connected to low level VSS. The second-stage CMOS inverter circuit includes a PMOS transistor M3 and an NMOS transistor M4; the source of the PMOS transistor M3 is electrically connected to the power supply voltage VDDL of the low voltage domain, and the gate of the PMOS transistor M3 is electrically connected to the gate of the NMOS transistor M4. connected together and electrically connected to the first-stage output terminal A of the two-pole input inverter (ie, the output of the first-stage CMOS inverter circuit is used as the input of the second-stage CMOS inverter circuit), the drain of the PMOS transistor M3 The pole of the NMOS transistor M4 is electrically connected to the drain of the NMOS transistor M4 as the second-stage output terminal B of the two-pole input inverter, and the source of the NMOS transistor M4 is electrically connected to the low level VSS.

(2) The specific structure of the strong pull-down latch circuit may include a two-part structure composed of four PMOS transistors and two NMOS transistors (that is, a part of the structure mainly composed of the PMOS transistor M5, the PMOS transistor M6, and the NMOS transistor M7 and the Another part of the structure based on PMOS transistor M8, PMOS transistor M9, and NMOS transistor M10); each part of the structure includes an RVT pull-up PMOS transistor (that is, PMOS transistor M5 and PMOS transistor M8 are RVT pull-up PMOS transistors), an HVT A middle pull-up PMOS transistor (ie, PMOS transistor M6 and PMOS transistor M9 are HVT middle pull-up PMOS transistors) and an LVT pull-down NMOS transistor (ie, NMOS transistor M7 and NMOS transistor M10 are LVT pull-down NMOS transistors), each part of the RVT pull-up PMOS transistor The gates of the transistors are all connected to the drains of another part of the LVT pull-down NMOS transistors (that is, the gate of the PMOS transistor M5 is electrically connected to the drain of the NMOS transistor M10, and the gate of the PMOS transistor M8 is electrically connected to the drain of the NMOS transistor M7). , the substrates of the HVT middle pull-up PMOS transistors in these two structures are all electrically connected to the positive level Vb1 (that is, the substrate of the PMOS transistor M6 is electrically connected to the substrate of the PMOS transistor M9 and electrically connected to the positive level Vb1 connection), the LVT pull-down NMOS transistors in these two structures are all electrically connected to the positive level Vb2 (that is, the substrate of the NMOS transistor M7 is electrically connected to the substrate of the NMOS transistor M10 and is electrically connected to the positive level Vb2), Thus constitutes a strong pull-down latch circuit. The gate-source voltage of the pull-up PMOS transistor in the middle of the HVT is less than the power supply voltage VDDH in the high-voltage domain, so the pull-up capability of the pull-up PMOS transistor in the middle of the HVT is obviously weaker than that of the RVT pull-up PMOS transistor. The tube is no longer an RVT pull-up PMOS transistor, but a middle HVT pull-up PMOS transistor, and the substrate of each part of the HVT middle pull-up PMOS transistor and the substrate of each part of the LVT pull-down NMOS transistor are respectively connected to a certain positive voltage. The substrate bias effect formed by the level (that is, the positive level Vb1 and the positive level Vb2) greatly enhances the pull-down capability of the strong pull-down latch circuit and ensures the reliability of the transition from low level to high level. sex.

(3) The DLS output inverter is used as an output inverter circuit, and the output terminal of the DLS output inversion is the output terminal OUT of the level conversion circuit of the strong pull-down latch structure, and the strong pull-down latch structure The output terminal OUT of the level conversion circuit is electrically connected to the external circuit of the chip. The specific structure of the DLS output inverter may include two NMOS transistors and two PMOS transistors, the two NMOS transistors are respectively defined as M11 and M13, and the two PMOS transistors are respectively defined as M12 and M14. The drain of the NMOS transistor M11 is electrically connected to the power supply voltage VDDH of the high voltage domain, the source of the NMOS transistor M11 is electrically connected to the source of the PMOS transistor M12, and the gate of the PMOS transistor M12 is electrically connected to the gate of the NMOS transistor M13. As the input terminal S of the DLS output inverter, the source of the NMOS transistor M13 is electrically connected to the source of the PMOS transistor M14, the drain of the PMOS transistor M14 is electrically connected to the low level VSS, the gate of the NMOS transistor M11, the PMOS transistor M11 The drain of the transistor M12, the drain of the NMOS transistor M13, and the gate of the PMOS transistor M14 are electrically connected together as the output terminal of the DLS output inverter (that is, the level of the strong pull-down latch structure described in Embodiment 1 of the present invention). The output terminal OUT of the conversion circuit, the output terminal OUT is electrically connected to the external circuit of the chip). The NMOS transistor M11, NMOS transistor M13, PMOS transistor M12, and PMOS transistor M14 are all RVT transistors. The substrate of the NMOS transistor M11 and the substrate of the NMOS transistor M13 are both electrically connected to the power supply voltage VDDH in the high voltage domain. Both the bottom and the substrate of the PMOS transistor M14 are electrically connected to the low level VSS.

Further, the principle of the level conversion circuit of the strong pull-down latch structure provided in Embodiment 1 of the present invention is as follows:

(1) The output voltage of the DLS output inverter is fed back to the bottom PMOS transistor M14 and the top NMOS transistor M11 so that all leakage transistors are in a super-off state. The so-called "super cut-off" means that the gate-source voltage of the NMOS transistor is negative, and the gate-source voltage of the PMOS transistor is positive. The leakage current of the DLS output inverter is much lower than that of the conventional inverter, and the power consumption is reduced several times compared with the conventional CMOS inverter. The CMOS inverter can greatly reduce power consumption.

(2) The two-pole input inverter includes a first-stage CMOS inverter circuit and a second-stage CMOS inverter circuit. The input of the first-stage CMOS inverter circuit is connected to the in-chip port, and the first-stage CMOS inverter circuit The output of the circuit is used as the input of the second-stage CMOS inverter circuit, and the output terminal A of the first-stage CMOS inverter circuit is connected to the source of the NMOS transistor M7 and the gate of the PMOS transistor M9 in the strong pull-down latch circuit. , the gate of the NMOS transistor M10 and the source of the NMOS transistor M10 are electrically connected, and the output terminal B of the second-stage CMOS inverter circuit is connected to the gate of the PMOS transistor M6 and the gate of the NMOS transistor M7 in the strong pull-down latch circuit. The two-pole input inverter is electrically connected, and the power supply voltage of the two-pole input inverter is connected to the power supply voltage VDDL in the low-voltage domain. Therefore, the use of the two-pole input inverter in the present invention can effectively ensure the output level of the core voltage and avoid the traditional core signal port. In the case of directly driving the NMOS, the level conversion circuit of the strong pull-down latch structure of the present invention is more stable and reliable.

(3) When the input terminal IN of the level conversion circuit of the strong pull-down latch structure is at a high level (that is, when the input signal IN is output at a high level), the first-stage CMOS input inverter will be passed through first. The output terminal A of the inverter circuit and the output terminal B of the second-stage CMOS inverter circuit have stable voltage outputs of VSS and VDDL respectively; when the output terminal B of the second-stage CMOS inverter circuit is a high level VDDL , the gate-source voltage of the pull-up PMOS transistor M6 in the middle of the HVT in the strong pull-down latch circuit is equal to the high-voltage domain power supply voltage equal to VDDH-VDDL, and the substrate of the pull-up PMOS transistor M6 in the middle of the HVT is connected to the positive level Vb1, so that the circuit The pull-up capability and pull-up speed are weakened. At the same time, the LVT pull-down NMOS transistor M7 is turned on, and because the LVT tube is used and the substrate of the LVT pull-down NMOS transistor M7 is connected to the positive level Vb2, Vth is extremely small, which makes the pull-down speed. It is greatly improved with the pull-down reliability. The combined effect of reducing the pull-up and improving the pull-down ensures that the strong pull-down latch circuit has high pull-down reliability and fast conversion speed, and is extremely suitable for I/ The O-cell realizes the transition from the low-voltage domain to the high-voltage domain.

Compared with the prior art, the level conversion circuit of the strong pull-down latch structure provided in Embodiment 1 of the present invention adopts a DLS output inverter as the output inverter, and adopts a two-pole input inverter composed of two inverters cascaded. The inverter is used as an input inverter, and a strong pull-down latch circuit with a special structure is used to ensure the reliability of ultra-low core voltage conversion to I/O voltage under advanced technology, and the level conversion circuit has a wide conversion range. , Fast speed and high reliability.

From the above, it can be seen that the embodiments of the present invention solve the problem that the core voltage cannot be pulled down normally, reduce the power consumption of the subsequent stage, and ensure the reliability of converting the ultra-low core voltage into the I/O voltage under the advanced technology. Moreover, it has the advantages of wide level conversion range, fast conversion speed and high reliability.

The above description is only a preferred embodiment of the present invention, but the protection scope of the present invention is not limited to this. Substitutions should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims. The information disclosed in this Background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.

Claims (4)

1. A strong pull-down latch structure level switching circuit is characterized by comprising a two-pole input inverter, a strong pull-down latch circuit and a DLS output inverter;

the input end of the two-pole input phase inverter is the input end IN of the strong pull-down latching structure level switching circuit; the output end of the DLS output inversion is the output end OUT of the strong pull-down latching structure level conversion circuit;

the strong pull-down latch circuit comprises four PMOS transistors and two NMOS transistors, wherein the four PMOS transistors are respectively defined as M5, M6, M8 and M9, and the two NMOS transistors are respectively defined as M7 and M10;

PMOS transistor M5 and PMOS transistor M8 are RVT pull-up PMOS transistors, PMOS transistor M6 and PMOS transistor M9 are HVT middle pull-up PMOS transistors, NMOS transistor M7 and NMOS transistor M10 are LVT pull-down NMOS transistors;

the source and the substrate of the PMOS transistor M5 are electrically connected to the supply voltage VDDH of the high voltage domain, the drain of the PMOS transistor M5 and the source of the PMOS transistor M6 are electrically connected to the input terminal S of the DLS output inverter, and the gate of the PMOS transistor M5 and the drain of the PMOS transistor M9 and the drain of the NMOS transistor M10 are electrically connected;

the source and the substrate of the PMOS transistor M8 are both electrically connected to the supply voltage VDDH of the high voltage domain, the drain of the PMOS transistor M8 is electrically connected to the source of the PMOS transistor M9, and the gate of the PMOS transistor M8 is electrically connected to the drain of the PMOS transistor M6 and the drain of the NMOS transistor M7;

the grid of the PMOS transistor M6 and the grid of the NMOS transistor M7 are electrically connected to the second-stage output end B of the two-stage input inverter; the grid of the PMOS transistor M9 and the grid of the NMOS transistor M10 are both electrically connected to the first-stage output end A of the two-stage input inverter; the source of the NMOS transistor M7 and the source of the NMOS transistor M10 are both electrically connected to the low level VSS;

the substrate of the PMOS transistor M6 is electrically connected together with the substrate of the PMOS transistor M9 and electrically connected to the positive level Vb 1; the substrate of the NMOS transistor M7 is electrically connected together with the substrate of the NMOS transistor M10 and electrically connected to the positive level Vb 2.

2. The strong pull-down latching architecture level shifting circuit of claim 1, wherein the structure of the two-pole input inverter comprises a first stage CMOS inverter circuit and a second stage CMOS inverter circuit;

the first stage CMOS inverter circuit includes a PMOS transistor M1 and an NMOS transistor M2; a source of the PMOS transistor M1 is electrically connected to a power supply voltage VDDL of a low voltage domain, a gate of the PMOS transistor M1 and a gate of the NMOS transistor M2 are electrically connected together as an input terminal of the bipolar input inverter, a drain of the PMOS transistor M1 and a drain of the NMOS transistor M2 are electrically connected together as a first-stage output terminal a of the bipolar input inverter, and a source of the NMOS transistor M2 is electrically connected to a low-level VSS;

the second stage CMOS inverter circuit includes a PMOS transistor M3 and an NMOS transistor M4; the source of the PMOS transistor M3 is electrically connected to the power supply voltage VDDL of the low voltage domain, the gate of the PMOS transistor M3 is electrically connected to the gate of the NMOS transistor M4 and to the first-stage output terminal a of the two-pole input inverter, the drain of the PMOS transistor M3 is electrically connected to the drain of the NMOS transistor M4 as the second-stage output terminal B of the two-pole input inverter, and the source of the NMOS transistor M4 is electrically connected to the low-level VSS.

3. The strong pull-down latch structure level shifter circuit as claimed in claim 1 or 2, wherein the structure of the DLS output inverter includes two NMOS transistors defined as M11, M13, respectively, and two PMOS transistors defined as M12, M14, respectively;

the drain of the NMOS transistor M11 is electrically connected to the supply voltage VDDH in the high voltage domain, the source of the NMOS transistor M11 is electrically connected to the source of the PMOS transistor M12, the gate of the PMOS transistor M12 is electrically connected to the gate of the NMOS transistor M13 as the input terminal S of the DLS output inverter, the source of the NMOS transistor M13 is electrically connected to the source of the PMOS transistor M14, the drain of the PMOS transistor M14 is electrically connected to the low level VSS, the gate of the NMOS transistor M11, the drain of the PMOS transistor M12, the drain of the NMOS transistor M13, and the gate of the PMOS transistor M14 are electrically connected together as the output terminal of the DLS output inverter;

the NMOS transistor M11, the NMOS transistor M13, the PMOS transistor M12, and the PMOS transistor M14 all employ RVT transistors, the substrate of the NMOS transistor M11 and the substrate of the NMOS transistor M13 are electrically connected to a power supply voltage VDDH in a high voltage domain, and the substrate of the PMOS transistor M12 and the substrate of the PMOS transistor M14 are electrically connected to a low-level VSS.

4. The strong pull-down latch structure level shifter circuit according to claim 1 or 2, wherein an input terminal IN of the strong pull-down latch structure level shifter circuit is electrically connected to an on-chip port; and the output end OUT of the strong pull-down latching structure level conversion circuit is electrically connected with a chip external circuit.

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