CN114499477B - A GaN driver with double protection - Google Patents

Abstract

The invention belongs to the technical field of electronic circuits, and in particular relates to a GaN half-bridge driver with double protection functions. The driver is based on the negative pressure generated by traditional capacitive coupling, and uses the high-K dielectric power device to switch to the corresponding working mode according to different control signals, making it suitable for driving with various voltage levels. The control signal controls the working mode of the high-K dielectric power device and the charging and discharging of the coupling capacitor, so that the first coupling capacitor can stably generate negative pressure, effectively preventing the GaN power tube from being turned on by mistake. It overcomes the problem that when negative pressure is generated by traditional capacitive coupling, the capacitive charge is easily disturbed and causes the negative pressure to disappear. Moreover, the present invention does not require external negative pressure or integration of internal step-down converters. On the one hand, it avoids the stability problems caused by large power consumption and switching interference caused by traditional external negative pressure. On the other hand, it reduces the structural complexity and saves layout area, reduce cost.

Description

A GaN driver with double protection

technical field

The invention belongs to the technical field of electronic circuits, and in particular relates to a GaN driver with double protection functions.

Background technique

Gallium Nitride (GaN) power transistors have a high mobility electron gas, which can achieve a current density and switching speed far exceeding that of traditional silicon-based devices, and has a wide range of applications. In applications involving GaN half-bridge switches such as motor drive, high-side drive, power conversion, and electric vehicle drive, the cooperation of pull-up and pull-down devices is required, but the development of pull-up P-channel GaN transistors is lagging behind. All-GaN integrated circuits have great difficulties, mainly reflected in the low threshold voltage of the GaN half-bridge switch (generally lower than 1.5V, the minimum value is as low as 0.7V), and the low threshold voltage of the GaN half-bridge switch itself in the actual circuit It will cause serious reliability problems for most applications, such as false opening and so on.

To overcome this problem, existing literatures have proposed corresponding driving schemes for different applications, which can be divided into two categories: non-negative voltage gate drive and negative voltage gate drive. Among them, the non-negative voltage gate drive is similar to the traditional CMOS power tube drive method, and the GaN switch is realized by driving the gate voltage above zero volts; the negative voltage gate drive uses negative voltage to drive the gate of the GaN power tube , by driving the circuit to generate a negative voltage, the gate voltage of the closed GaN power tube is lowered below the ground level, so as to avoid false opening of the gate of the GaN power tube.

The traditional negative voltage gate drive circuit achieves GaN power transistor driving by connecting an external negative voltage, or using an internal buck converter to generate negative voltage, or generating negative voltage based on capacitive coupling. Generating negative voltage through an external negative voltage or using an internal step-down converter will result in additional power consumption and cost; through capacitive coupling to generate negative voltage, when the GaN power tube is turned on, the capacitor is charged first, and when the GaN power tube needs When it is turned off, connect one end of the capacitor to the ground, so that the voltage difference on the capacitor directly acts on the gate of the GaN power tube to realize negative voltage driving. This driving method cannot provide a stable negative voltage for the gate of the GaN power tube. When there is a large disturbance, the charge of the coupling capacitor is easily disturbed and the negative pressure disappears, which makes the gate voltage of the GaN power tube rise, and the negative pressure generated by the capacitive coupling method will be destroyed, causing the GaN power tube to be turned on by mistake.

Contents of the invention

The purpose of the present invention is to provide a GaN driver with dual protection functions, so as to solve the problem that the traditional GaN power tube driving method based on capacitive coupling to generate negative pressure cannot provide a stable negative voltage for the GaN power tube gate.

To achieve the above object, the present invention adopts the following technical solutions:

A GaN driver with dual protection functions, including a first die and a load, one end of the load is connected to the output terminal G1 of the first die, and the other end is grounded;

The first die includes a first high-K dielectric power device S1, a first coupling capacitor C1, a first NMOS transistor M1, a power supply Vcc, and a second NMOS transistor M2;

The first high-K dielectric power device S1 has a main grid, a slave grid, an anode and a cathode, the main grid is connected to an externally input control signal 1, the slave grid is connected to an externally input control signal 2, and the anode is connected to the first NMOS transistor The source of M1 and the drain of the second NMOS transistor M2, the cathode grounded and the source of the second NMOS transistor M2;

One end of the first coupling capacitor C1 is connected to the slave gate of the first high-K dielectric power device S1, and the other end is connected to the source of the first NMOS transistor M1 and the drain of the second NMOS transistor M2;

The gate of the first NMOS transistor M1 is connected to the external input control signal 3, the drain is connected to the power supply Vcc, and the source is connected to the drain of the second NMOS transistor M2 to form the output terminal G1 of the first die;

The gate of the second NMOS transistor M2 is connected to an externally input control signal 4, and the source is grounded;

Control the on-off of the first NMOS transistor M1 and the second NMOS transistor M2 through the high and low levels of the externally input control signal 3 and control signal 4; through the high and low levels of the externally input control signal 1 and control signal 2 Controlling the working mode of the high-K dielectric power device S1 realizes controlling the charging and discharging of the first coupling capacitor C1 so that it can stably generate negative voltage.

Further, the process of stably generating negative pressure of the GaN driver with double protection function is:

When the external input low-level control signal 3 and low-level control signal 4 turn off the first NMOS transistor M1 and the second NMOS transistor M2; the external input high-level control signal 2 turns off the slave gate of the high-K dielectric power device S1 Set to high level, when the external input level control signal sets the main gate to low level, the high-K dielectric power device S1 is in the off mode, and the first coupling capacitor C1 is connected to one end of the gate to charge positive charges. The other end is charged with a negative charge, and when negative voltage needs to be generated, an external high-level control signal 4 is input to turn on the second NMOS transistor M2, and G1 can be pulled down to ground potential to prepare for negative pressure generation;

When the external input low-level control signal four turns off the second NMOS transistor M2, the external input low-level control signal two changes the gate input of the high-K dielectric power device from high level to low level, and the external input high As soon as the level control signal changes the main gate input from low level to high level, the high-K dielectric power device S1 is turned on and works in a state of strong current pull-down capability. Since the first coupling capacitor C1 is connected to one end of the slave gate as the ground level, the other end of the first coupling capacitor C1 will generate a negative voltage.

Further, the load is a GaN power transistor M3, the gate of which is connected to the output terminal G1 of the first die, the drain is connected to the positive power supply HV, and the source is grounded.

A GaN driver with dual protection functions, including a high-side GaN transistor M5, a low-side GaN transistor M6, a first die, and a second die;

The gate of the high-side GaN tube M5 is connected to the output G1 of the first die, the drain is connected to the positive power supply HV, and the source is connected to the floating potential SW; the gate of the low-side GaN tube M6 is connected to the output G2 of the die 2, and the drain is connected to Floating potential SW, source connected to ground;

The first die is composed of the first power supply Vcc1, the first NMOS transistor M1, the second NMOS transistor M2, the first coupling capacitor C1, and the first high-K dielectric power device S1; the first power supply Vcc1 is connected to the drain of the first NMOS transistor M1 The gate of the first NMOS transistor M1 is connected to the external input control signal 7, and the source is connected to the drain of the second NMOS transistor M2 to form the output terminal G1 of the first die; the gate of the second NMOS transistor M2 is connected to the external Input control signal eight, the source is connected to the cathode of the first high-K dielectric power device S1 and the floating potential SW; one end of the first coupling capacitor C1 is connected to the output terminal G1 and the anode of the first high-K dielectric power device S1, and the other end is connected to the first high-K dielectric power device S1. The slave gate of a high-K dielectric power device S1; the main gate of the first high-K dielectric power device S1 is connected to the external input control signal 6, and the slave gate is connected to the external input control signal 5;

The second die is composed of a second power supply Vcc2, a third NMOS transistor M3, a fourth NMOS transistor M4, a second coupling capacitor C2, and a second high-K dielectric power device S2; the second power supply Vcc2 is connected to the drain of the third NMOS transistor M3 The gate of the third NMOS transistor M3 is connected to the external input control signal 9, and the source is connected to the drain of the fourth NMOS transistor M4 to form the output terminal G2 of the second die; the gate of the fourth NMOS transistor M4 is connected to the external Input the control signal ten, the source is connected to the cathode of the second high-K dielectric power device S2, the source of the low-side GaN transistor M6 and the ground; one end of the second coupling capacitor C2 is connected to the output terminal G2 and the second high-K dielectric power device S2 The anode of the second high-K dielectric power device S2 is connected with the other end; the main gate of the second high-K dielectric power device S2 is connected to the external input control signal twelve, and the slave gate is connected to the external input control signal eleven.

The high-K dielectric power device is a power device developed on the basis of the technology accumulation of high-K devices. The device has three operating modes: standard LIGBT, enhanced twin conduction and PMOS. By switching the three operating modes, it can It is applied to different voltage levels, for details, please refer to the content disclosed in patent number ZL201510998522.X.

A GaN driver with dual protection functions provided by the present invention provides the first heavy negative pressure protection on the basis of negative pressure generated by traditional capacitive coupling, and uses high-K dielectric power devices to switch to corresponding working modes according to different control signals. To make it suitable for the drive of various voltage levels, control the high-K dielectric power device to work in the state of strong pull-down capability through the external input control signal, so that the gate voltage of the GaN power tube is lower than 0.7V, providing the second layer Protection, through the joint action of capacitive coupling and high-K dielectric power devices, effectively prevents GaN power tubes from being turned on by mistake. In the present invention, one end of the coupling capacitor is connected to the slave gate of the high-K dielectric power device, and the other end is connected to the output end of the tube core and the anode of the high-K dielectric power device. When a voltage is applied to the coupling capacitor, it is connected to the slave gate One end of the pole accumulates positive charge under the action of electric field force, and the other end accumulates negative charge. That is, under the coupling effect of the coupling capacitor, the negative charge accumulated by the coupling capacitor is different from the negative voltage in the traditional sense. It is essentially a positive voltage, but the voltage value is lower than the voltage value generated by the positive charge connected to one end of the gate. When the external high-level control signal 4 is input to turn on the second NMOS transistor M2, the output terminal G1 can be pulled down to the ground potential. There is a transition stage in the entire negative pressure generation process, which effectively reduces the power consumption of the driver. When a large current disturbance occurs, the high-K power device is controlled to enter the enhanced twin conduction mode. At this time, the high-K power device has a strong current pull-down capability, and the high-K power device’s strong current pull-down capability is used to timely discharge the large current of the output terminal G1. , the gate potential is clamped at 0.7V to prevent the GaN tube from being turned on by mistake.

Compared with the prior art, the present invention has the following advantages:

1. The present invention does not require external negative pressure or internal step-down converter integration. On the one hand, it avoids the large power consumption caused by the traditional external negative pressure and the stability problem caused by switching interference. On the other hand, it reduces the structural complexity. Save layout area and reduce cost.

2. The working mode of the high-K dielectric power device and the charging and discharging of the coupling capacitor are controlled by an externally input control signal, which overcomes the problem that when the traditional capacitive coupling generates negative pressure, the capacitor charge is easily disturbed and the negative pressure disappears.

Description of drawings

Fig. 1 is a structural representation of the present invention;

Fig. 2 is the structural representation of embodiment 1;

Fig. 3 is embodiment 1 sequence diagram;

Fig. 4 is the structural representation of embodiment 2:

FIG. 5 is a timing diagram of Embodiment 2.

Detailed ways

The GaN half-bridge driver with dual protection functions of the present invention will be described in detail below with reference to the drawings and embodiments.

Example 1

FIG. 4 provides a first embodiment of the present invention. As shown in FIG. 4, a GaN driver with dual protection functions includes a first die and a load;

The first die includes a first high-K dielectric power device S1, a power supply Vcc, a first coupling capacitor C1, a first NMOS transistor M1, and a second NMOS transistor M2. The first high-K dielectric power device S1 has a main grid 4, a slave grid 3, an anode 7, and a cathode 8; the main grid 4 of the high-K dielectric power device S1 is connected to an external input control signal-5, and the slave grid 3 is connected to an external Input control signal 2 6, the anode 7 is connected to the source of the first NMOS transistor M1 and the drain of the second NMOS transistor M2, the first coupling capacitor C1 is connected between the gate and the anode, the cathode is grounded and the second NMOS transistor M2 Source: the gate of the first NMOS transistor M1 is connected to the external input control signal 31, the drain is connected to the power supply Vcc, and the source is connected to the drain of the second NMOS transistor M2 to form the output terminal G1 of the first die; the second The gate of the NMOS transistor M2 is connected to the external input control signal 42, and the source is grounded.

The load is a GaN power transistor M3, the gate of the GaN power transistor M3 is connected to the output terminal G1 of the first die, the drain is connected to the positive power supply HV, and the source is grounded.

As shown in Figure 5, at time t0-t1, the external input control signal 31 is set to high level to turn on the first NMOS transistor M1, and the external input control signal 42 is set to low level to turn off the second NMOS transistor M2 ; The external input control signal 26 is set to high level, and the external input control signal 15 is set to low level, so that the first high-K dielectric power device S1 is completely turned off; at this time, the first coupling capacitor C1 is connected to the slave gate One end of pole 3 is charged with positive charge, and the other end is negatively charged. Through the pull-up effect of the first NMOS transistor M1, the voltage at point G1 is pulled up, and the GaN power transistor M3 is turned on.

When the GaN power transistor M3 needs to be turned off at time t1, set the external input signal 31 to low level to turn off the first NMOS transistor M1, and set the external input signal 42 to low level to turn off the second NMOS transistor M2; t2 At any time, the external input signal 15 provides a high level to the main gate 4. At this time, the first high-K dielectric power device S1 works in the typical twin conduction mode of the standard traditional LIGBT, and at the same time, the external input signal 42 provides a high level to turn the second The second NMOS tube M2 is turned on, and the point G1 drops to the ground potential. At time t3, the external input signal 42 is set to low level to turn off the second NMOS tube, and the external input signal 26 is set to low level, because at this time the slave gate 3 of the first high-K dielectric power device S1 is low level, the right side of the first coupling capacitor C1 will realize a negative pressure, and completely turn off the GaN power transistor M3. Even if the circuit is disturbed and the potential of G1 rises, since the high-K dielectric power device S1 is working in the state of strong current pull-down capability, it can quickly absorb the current at point G1, so that the potential of this point will drop, and because of the high K at this time There is a voltage difference of 0.7V between the anode 7 and the cathode 8 of the dielectric power device S1, which can ensure that the gate voltage of the GaN power transistor M3 does not exceed 0.7V under worst conditions, providing double protection for negative voltage.

Example 2

Figure 2 provides a second embodiment of the present invention, as shown in Figure 2, a GaN driver with dual protection functions provided by this embodiment includes: a first die, a second die, a high-side GaN transistor M5 and low-side GaN tube M6, positive power supply HV. The gate G1 of the high-side GaN transistor M5 is connected to the output of the die 1, the drain of the M5 is connected to the positive power supply HV, and the source of the M5 is connected to the floating potential SW. The gate G2 of the low-side GaN transistor M6 is connected to the output of the die 2, the drain of M6 is connected to the floating potential SW, and the source of M6 is connected to the ground.

Die 1 includes: high-K dielectric power device S1, first NMOS transistor M1, second NMOS transistor M2, first coupling capacitor C1, external input control signal five 11, external input control signal six 12, external input control signal seven 7 , external input control signal eight 8, positive power supply Vcc1. The gate of the first NMOS transistor (M1) is connected to the external input control signal 77, the gate of the second NMOS transistor M2 is connected to the external input control signal 88, and the main gate 10 of the high-K dielectric power device S1 is connected to the external input control signal 612 , the gate 9 is connected to the external input control signal 5 11, the left side of the first coupling capacitor C1 is connected to the external input control signal 5 11, and the right side is connected to G1. The drain of the first NMOS transistor M1 is connected to the power supply Vcc1, and the source is connected to G1. The drain of the second NMOS transistor is connected to G1, and the source is connected to the floating potential SW.

Die 2 includes: high-K dielectric power device S2, third NMOS transistor M3, fourth NMOS transistor M4, second coupling capacitor C2, external input control signal nine 15, external input control signal ten 16, external input control signal eleven 17. External input control signal 12. 18. Positive power supply Vcc2. The gate of the third NMOS transistor M3 is connected to the external input control signal 15, the gate of the fourth NMOS transistor M4 is connected to the external input control signal 16, and the gate 19 of the high-K dielectric power device S2 is connected to the external input control signal 10 17, the main gate 20 is connected to the external input control signal 12 18, the left side of the second coupling capacitor C2 is connected to the external input control signal 11 17, and the right side is connected to G2. The drain of the third NMOS transistor M3 is connected to the power supply Vcc2, and the source is connected to G2. The drain of the fourth NMOS transistor is connected to G2, and the source is connected to the ground.

As shown in the standard working timing diagram in Figure 3, when the high-side GaN transistor M5 needs to be turned off, at time t1, the gate level of the first NMOS is pulled down, and M1 is turned off; then at time t2, the internal The gate level of the second NMOS transistor is set to a high level, M2 is turned on, and at the same time, the external input control signal 6 12 sets the main gate 10 of the high-K dielectric power device S1 to a high level, while the external input control signal 5 11 maintains The high level of the gate 9 remains unchanged. At this moment, the second NMOS transistor M2 pulls down G1 to the level of the floating potential SW point, and the gate-source voltage of the high-side GaN transistor M5 is zero, and will be in a cut-off state.

During the switching dead time between t2 and t3, since the main gate 10 and the slave gate 9 of the high-K dielectric power device S1 are at high level at the same time, the high-K dielectric power device S1 will be in the standard LIGBT working mode at this time, Since the second NMOS transistor M2 pulls the voltage at point G1 to the floating potential SW voltage, the voltage between the anode 13 and the cathode 14 of the high-K dielectric power device S1 is lower than 0.7V, so that no current flows through the high-K dielectric power device S1, However, due to the strong current pull-down capability of LIGBT, if there is a large disturbance at this time, the voltage at point G1 will increase rapidly, and the strong current pull-down capability of high-K dielectric power device S1 will quickly absorb the disturbance current, ensuring that the voltage at point G1 will not change. If it exceeds 0.7V, the wrong turn-on of the high-side GaN transistor M5 is avoided. At this time, since the secondary gate 9 of the high-K dielectric power device S1 is high and G1 is low, the first coupling capacitor C1 will charge positive charges on the left plate and negative charges on the right plate.

When the dead time from t2 to t3 ends, the low-side GaN transistor M6 needs to be turned on. Before t3, the high-K dielectric power device S2 works in a state of strong current pull-down capability, and G2 is a negative voltage. At time t3, the external input control signal 11 17 sets the secondary gate 19 of the high-K dielectric power device S2 to a high level, and the external input control signal 12 18 sets the main gate 20 to a low level to completely turn off the high-K dielectric power device S2. Dielectric power device S2. Due to the leakage of the second coupling capacitor C2 during the turn-off period of the low-side GaN transistor M6, the voltage difference on C2 is reduced, so when the high-K dielectric power device S2 rises from the voltage on the gate 19 to the high-level voltage, G2 A positive pressure will be generated, turning on the low side GaN transistor M6. Since the high-K dielectric power device S2 rapidly rises from the gate 19 when the voltage is coupled to G2 through the second coupling capacitor C2, the delay is small, and the low-side GaN transistor M6 will be turned on very quickly. At the same time, the external input control signal 88 becomes low level, and M2 in the die 1 is turned off. When the external input control signal 511 sets the slave gate 9 of the high-K dielectric power device S1 from high to low, there is a left-to-right voltage on the first coupling capacitor C1, and G1 on the right side of the first coupling capacitor C1 will realize negative The high-side GaN tube M5 is completely closed.

Since the high-K dielectric power device S2 has been turned off at time t3. At time t4, the external input control signal 915 becomes high level, and the third NMOS transistor M3 is turned on without generating short-circuit current. When M3 is turned on, it will provide a stable active positive voltage for G2, thereby maintaining the low-side GaN transistor The opening of M6. When it is necessary to turn off the low-side GaN transistor M6 and turn on the high-side GaN transistor M5, at time t5, the external input control signal 915 first sets the gate of the third NMOS transistor in die 2 to a low level to turn off M3 to avoid short circuit . Then at time t6, the external input control signal twelve 18 sets the main gate 20 of the high-K dielectric power device S2 in the die 2 to a high level, and the external input control signal ten 16 sets the gate of the fourth NMOS transistor M4 At the same time, M4 pulls the G2 point to the ground level, similar to the high-K dielectric power device S1 in die 1 at time t2. At this time, the high-K dielectric power device S2 will enter the standard LIGBT working mode and can discharge Large current disturbance at point G2. At the same time, the slave gate 19 of the high-K dielectric power device S2 is high and the point G2 is low, and the second coupling capacitor C2 will be positively charged on the left plate and negatively charged on the right plate. At the time t7, the main gate 10 and the slave gate 9 of the high-K dielectric power device S1 are set to low level and high level respectively to completely close the new high-K dielectric multifunctional device S1, and use the rise of the slave gate 9 The voltage, through the capacitive coupling of the first coupling capacitor C1, quickly turns on the high-side GaN transistor M5. At the same time, the external input control signal +16 becomes low level, turning off the fourth NMOS transistor M4 in the die 2 . The external input control signal eleven 17 sets the slave gate 19 of the high-K dielectric power device S2 from high to low. Since there is a left-to-right voltage on the second coupling capacitor C2, when the slave gate 19 is at the ground level, the point G2 will realize a negative voltage.

At time t8, the external input control signal 77 sets the gate of the first NMOS transistor in die 1 to a high level, turns on the first NMOS transistor M1, keeps the voltage at point G1 high, and makes the high-side GaN transistor M5 last turned on, enabling high-side switching operation.

It can be seen that the present invention can realize negative voltage driving without external negative pressure and integration of internal buck converter. Compared with the traditional way of driving GaN power transistors by generating negative pressure through capacitive coupling, this embodiment provides a new idea. This embodiment controls the high-K dielectric power device and the coupling capacitor to generate negative pressure to realize the driving of the GaN power tube, which overcomes the capacitive charge in the traditional capacitive coupling negative voltage drive and is easily disturbed to cause the negative pressure to disappear, or the circuit. When the disturbance is too large, it may cause a positive voltage on the GaN gate, making the GaN gate that should be off continue to be turned on. In this embodiment, the working mode of the high-K dielectric power device is switched, and the coupling capacitor is controlled to generate negative pressure, so that the high-K dielectric power device is in a state of strong current pull-down capability, which can fully absorb the peak current caused by the large disturbance, ensuring In the worst case, the GaN gate voltage does not exceed 0.7V, thus providing highly reliable double protection for GaN.

Claims (4)

1. A GaN driver with dual protection functions, comprising a first die and a load, one end of the load is connected to the output terminal G1 of the first die, and the other end is grounded, characterized in that: The first die includes a first high-K dielectric power device S1, a first coupling capacitor C1, a first NMOS transistor M1, a power supply Vcc, and a second NMOS transistor M2; The first high-K dielectric power device S1 has a main grid, a slave grid, an anode and a cathode, the main grid is connected to an externally input control signal 1, the slave grid is connected to an externally input control signal 2, and the anode is connected to the first NMOS transistor The source of M1 and the drain of the second NMOS transistor M2, the cathode grounded and the source of the second NMOS transistor M2; One end of the first coupling capacitor C1 is connected to the slave gate of the first high-K dielectric power device S1, and the other end is connected to the source of the first NMOS transistor M1 and the drain of the second NMOS transistor M2; The gate of the first NMOS transistor M1 is connected to the external input control signal 3, the drain is connected to the power supply Vcc, and the source is connected to the drain of the second NMOS transistor M2 to form the output terminal G1 of the first die; The gate of the second NMOS transistor M2 is connected to an externally input control signal 4, and the source is grounded; Control the on-off of the first NMOS transistor M1 and the second NMOS transistor M2 through the high and low levels of the externally input control signal 3 and control signal 4; through the high and low levels of the externally input control signal 1 and control signal 2 Controlling the working mode of the high-K dielectric power device S1 realizes controlling the charging and discharging of the first coupling capacitor C1 so that it can stably generate negative voltage. 2. A GaN driver with dual protection functions according to claim 1, characterized in that: the stable negative pressure generation process of the GaN driver with dual protection functions is: When the external input low-level control signal 3 and low-level control signal 4 turn off the first NMOS transistor M1 and the second NMOS transistor M2; the external input high-level control signal 2 turns off the slave gate of the high-K dielectric power device S1 Set to high level, when the external input level control signal sets the main gate to low level, the high-K dielectric power device S1 is in the off mode, and the first coupling capacitor C1 is connected to one end of the gate to charge positive charges. The other end is charged with a negative charge, and when negative voltage needs to be generated, an external high-level control signal 4 is input to turn on the second NMOS transistor M2, and G1 can be pulled down to ground potential to prepare for negative pressure generation; When the external input low-level control signal four turns off the second NMOS transistor M2, the external input low-level control signal two changes the gate input of the high-K dielectric power device from high level to low level, and the external input high As soon as the level control signal changes the main gate input from low level to high level, the high-K dielectric power device S1 is turned on and works in a state of strong current pull-down capability. Since the first coupling capacitor C1 is connected to one end of the slave gate as the ground level, the other end of the first coupling capacitor C1 will generate a negative voltage. 3. A GaN driver with dual protection functions according to claim 1 or 2, characterized in that: the load is a GaN power transistor M3, the gate of which is connected to the output terminal G1 of the first die, and the drain is connected to Positive power supply HV, source grounded. 4. A GaN driver with dual protection functions, comprising a high-side GaN tube M5, a low-side GaN tube M6, a first die and a second die, characterized in that: The gate of the high-side GaN tube M5 is connected to the output G1 of the first die, the drain is connected to the positive power supply HV, and the source is connected to the floating potential SW; the gate of the low-side GaN tube M6 is connected to the output G2 of the die 2, and the drain The pole is connected to the floating potential SW, and the source is connected to the ground; The first die is composed of a first power supply Vcc1, a first NMOS transistor M1, a second NMOS transistor M2, a first coupling capacitor C1, and a first high-K dielectric power device S1; the first power supply Vcc1 is connected to the first NMOS transistor M1 The drain of the first NMOS transistor M1 is connected to the external input control signal 7, and the source is connected to the drain of the second NMOS transistor M2 to form the output terminal G1 of the first die; the gate of the second NMOS transistor M2 Connect to the external input control signal 8, the source is connected to the cathode of the first high-K dielectric power device S1 and the floating potential SW; one end of the first coupling capacitor C1 is connected to the output terminal G1 and the anode of the first high-K dielectric power device S1, and the other end Connect the slave gate of the first high-K dielectric power device S1; the main gate of the first high-K dielectric power device S1 is connected to the external input control signal 6, and the slave gate is connected to the external input control signal 5; The second die is composed of a second power supply Vcc2, a third NMOS transistor M3, a fourth NMOS transistor M4, a second coupling capacitor C2, and a second high-K dielectric power device S2; the second power supply Vcc2 is connected to the third NMOS transistor M3 The drain of the third NMOS transistor M3 is connected to the external input control signal 9, and the source is connected to the drain of the fourth NMOS transistor M4 to form the output terminal G2 of the second die; the gate of the fourth NMOS transistor M4 Connect to the external input control signal 10, the source is connected to the cathode of the second high-K dielectric power device S2, the source of the low-side GaN transistor M6 and the ground; one end of the second coupling capacitor C2 is connected to the output terminal G2 and the second high-K dielectric power The anode of the device S2 is connected to the slave gate of the second high-K dielectric power device S2 at the other end; the main gate of the second high-K dielectric power device S2 is connected to the external input control signal 12, and the slave gate is connected to the external input control signal 10 one.

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