CN114497190B - Semiconductor device with non-uniformly distributed space life and manufacturing method - Google Patents

Abstract

The invention provides a semiconductor device with non-uniform distribution of space lifetime, the minority carrier lifetime under the cathode is lower than the minority carrier lifetime under the gate. The semiconductor device with non-uniform distribution of space life and the manufacturing method of the present invention improve the off-current capability of a single cell by optimizing the steady-state carrier distribution density and the electric field distribution in the turn-off transient state, thereby improving the safe operation of the device district.

Description

A semiconductor device with non-uniform distribution of space lifetime and its manufacturing method

technical field

The invention belongs to the technical field of semiconductor devices, in particular to a semiconductor device with non-uniform distribution of space lifetime and a manufacturing method.

Background technique

With the rapid development of distributed renewable energy and the urgent need for the reliability of power transmission and distribution systems, intelligent control and power electronics of power equipment have become a recognized development trend. Power electronic devices are widely used in AC-DC converters, DC transformers, DC circuit breakers, wind turbine converters, photovoltaic inverters, etc. Integrated Gate-Commutated Thyristors (IGCT, Integrated Gate-Commutated Thyristor) also rely on their low cost , low conduction loss, and high reliability have become new concerns in low-frequency, high-capacity applications.

In order to further tap the potential of IGCT in high-capacity applications, it has always been the research focus of researchers in the industry to discuss device optimization from the perspective of meeting the overall performance requirements of multiple key parameters at the same time. Among them, the maximum shutdown current capability is a very important parameter, which directly affects the cost and loss of the application.

The macroscopic performance parameters of IGCT devices are determined by microscopic characteristic parameters such as carrier concentration, lifetime, impact ionization coefficient, and surface recombination rate. Therefore, it is a more effective and more targeted means to start from the regulation of microscopic characteristics to modulate macroscopic performance. . Among them, the lifetime of minority carriers (that is, minority carriers) is one of the optional control objects. Since the minority carrier lifetime directly affects the movement state and law of the minority carrier, the regulation of the minority carrier lifetime has a wider range and higher sensitivity for the modulation of device characteristic parameters.

At present, there are two basic methods for controlling the minority carrier lifetime of power semiconductor devices: one is to introduce deep-level impurity thermal diffusion into the silicon forbidden band, and the other is to bombard high-energy particles that cause lattice damage in the crystal. The thermal diffusion of impurities represented by gold and platinum and the irradiation of high-energy electrons all form uniform defects in the wafer, which can only control the minority carrier lifetime as a whole, which makes it relatively simple to regulate power semiconductor devices. Light ion irradiation is currently the only technology that can achieve local control of minority carrier lifetimes, mainly including protons and helium ions; protons are lighter in mass and proton accelerator technology is relatively mature in China. Therefore, proton irradiation is the most effective means with the highest degree of freedom to achieve local control of device minority carrier lifetimes and custom modulation of performance parameters of power semiconductor devices. At the same time, combined with electron irradiation, multi-dimensional adjustment of the spatial lifetime of semiconductor devices can be realized.

Patent application JP2004288680A proposes a press-contact type semiconductor device, which can particularly improve the reverse blocking breakdown voltage characteristic or reverse recovery characteristic of a thyristor. Five embodiments are proposed, two of which are related to lifespan control.

Among them, the third embodiment describes three local lifetime control regions, which are also typical control regions for proton irradiation. By introducing multi-level proton irradiation defects in the N-based region near the cathode side, in the middle, and near the anode side, Thereby improving the reverse recovery characteristic of the device. As shown in FIG. 1 , inside the N-type layer of the semiconductor substrate 10 , a plurality of lifetime control regions are formed approximately parallel to the substrate surface. In the lifetime control region, crystal defects are intentionally introduced by irradiating protons, etc., to form deep energy levels in the semiconductor forbidden band, so that the residual carriers can be quickly eliminated when turned off. Here, three lifetime control regions are formed, and the first lifetime control region 31 closest to the second diffusion layer 12 and the third diffusion layer 13 is the second diffusion layer, preferably a region with a shorter lifetime. The second lifetime control region 32 is second closer than the second lifetime control region 12 and the third diffusion layer 13 . In addition, it is preferable that the lifetime of the first lifetime control region 31 is the shortest among the lifetime control regions. The fourth embodiment controls the lifetime of the edge BV structure, which can reduce the current density of the edge, concentrate the current in the central active area, and improve the working temperature, as shown in FIG. 2 .

Patent CN103065950B (a method for improving the safe working area of GCT chips) proposes a method for improving the safe working area of GCT chips. The non-uniformity of the traditional composite alloy baffle irradiates the GCT chip twice, by reducing the minority carrier lifetime of the principle gate comb, reducing the redistribution effect of the current during the GCT shutdown process, and improving the overall safe working area of the GCT chip, etc. advantage. The patent uses electron irradiation to optimize the overall uniformity of the chip, thereby improving the off-current capability.

At present, the improvement of semiconductor devices through irradiation technology is mainly to optimize the turn-off loss and reverse recovery loss, and the lateral non-uniform electron irradiation at the chip level (for example, irradiating the outer ring of the chip) can improve the safe working area, but It will significantly increase the voltage drop, thereby increasing the conduction loss of the device in the application. Therefore, how to significantly improve the turn-off capability of semiconductor devices and avoid significant impact on other characteristic parameters is an urgent technical problem to be solved.

Contents of the invention

In view of the above problems, the present invention proposes a semiconductor device and a manufacturing method with a non-uniform distribution of space lifetime, which can reduce the minority carrier lifetime under the cathode, weaken the two-dimensional storage effect, increase the carrier concentration under the gate, and optimize the switching efficiency. The distribution of the electric field during the off process accelerates the recombination of electron-hole pairs generated by the avalanche and improves the turn-off capability. This structure can minimize the impact of irradiation on other characteristics such as pressure drop and other parameters. This structure can be used for but not limited to asymmetric IGCT and reverse resistance IGCT, and is also suitable for other symmetrical and asymmetrical power devices, such as thyristors, IGBTs (Insulated Gate Bipolar Transistor, insulated gate bipolar transistors), etc.

A semiconductor device with non-uniform spatial lifetime distribution, wherein the minority carrier lifetime under the cathode is lower than the minority carrier lifetime under the gate.

Further, the longitudinal distribution of the minority carrier lifetime under the cathode is uniform.

Further, the minority carrier lifetime below the cathode is longitudinally distributed non-uniformly;

The maximum minority carrier lifetime under the cathode is not greater than the minority carrier lifetime under the gate.

Further, an A1 area and an A2 area are longitudinally distributed under the cathode, wherein the A1 area is arranged between the A2 area and the cathode;

The minority carrier lifetime of the A1 region is not greater than the minority carrier lifetime below the gate;

The minority carrier lifetime of the A2 region is smaller than the minority carrier lifetime of the A1 region.

Further, an A2 area and a plurality of A1 areas are longitudinally distributed under the cathode, wherein the direction from the cathode to the anode is the A1 area, the A2 area and the A1 area;

The minority carrier lifetime of the A1 region is not greater than the minority carrier lifetime below the gate;

The minority carrier lifetime of the A2 region is smaller than the minority carrier lifetime of the A1 region.

Further, there is a first region with uniform distribution of minority carrier lifetimes under the cathode, and the width of the first region is less than 400um.

Further, the width of the A2 region is less than 400um, the height is less than 200um, and the distance to the cathode side is less than 600um.

Further, the width of the A2 region is the same as the width of the cathode; and/or

The height of the A2 area is 20-40um; and/or

The distance from the A2 area to the cathode side is 200-300um.

Further, the semiconductor device is an IGCT, a thyristor or an IGBT.

The present invention also provides a method for manufacturing a semiconductor device with a non-uniform distribution of space lifetime, wherein the above-mentioned semiconductor device is formed by electron irradiation and/or proton irradiation.

The semiconductor device with non-uniform distribution of space life and the manufacturing method of the present invention improve the off-current capability of a single cell by optimizing the steady-state carrier distribution density and the electric field distribution in the turn-off transient state, thereby improving the safe operation of the device district. Furthermore, by distributing the defects within a certain depth range under the cathode through proton irradiation, the safe working area can be optimized and at the same time, the conduction voltage drop of the device has almost no influence.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure pointed out in the written description, claims hereof as well as the appended drawings.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 shows a longitudinal sectional view of a third embodiment of a crimp-type semiconductor device according to the prior art;

Fig. 2 shows a longitudinal sectional view of a crimping type semiconductor device according to the prior art;

Fig. 3 shows a schematic diagram of a GCT single cell structure according to an embodiment of the present invention;

FIG. 4 shows a schematic diagram of a cell structure of a semiconductor device with uniform distribution of space life according to an embodiment of the present invention;

Fig. 5 shows a schematic diagram of partial electron irradiation according to an embodiment of the present invention;

FIG. 6 shows a schematic diagram of a cell structure of a semiconductor device with non-uniform lifetime distribution according to an embodiment of the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

A semiconductor device with non-uniform distribution of space lifetime and a manufacturing method thereof. Wherein, the semiconductor device may be an asymmetric IGCT, a reverse resistance IGCT, and other symmetric and asymmetric power devices, such as thyristors and IGBTs, are also applicable. In the following, GCT (Gate Commutated Thyristor, Gate Commutated Thyristor) is taken as an example for illustration.

A GCT chip is composed of thousands of cells, and the structure of a single cell is shown in Figure 3. According to the doping concentration, it is divided in order from the cathode to the anode: n+ emitter, p base, n- The base area, the n buffer area, and the p+ emitter have three PN junctions J1, J2, and J3 (that is, the boundary line between the p-type doped area and the n-type doped area in the semiconductor). In the on-state, the current flows from the anode to the cathode, and the current path passes through the PNPN four-layer structure. In the on-state mode, it is very similar to a thyristor; in the turn-off process, the gate cathode applies back pressure, and the cathode current begins to commutate to the gate, and the commutation ends Finally, the current flows from the anode to the gate, through the PNP three-layer structure, ready for the shutdown process in transistor mode.

相关，如式 （1）所示。其中载流子密度包括形成电流的空间电荷

和基底掺杂电荷

。耗尽层 扩展的过程中不断扫除N基区内的存储电荷，又由于阴极下方存储电荷密度较大，扫除N基 区载流子的过程中阴极下方电流密度较大，电流带来的空间电荷使得阴极下方电场强度较 大。 Since the GCT chip adopts a structure in which the cathode and gate heights are staggered, and the heights of the cathode and gate electrodes are not equal, it is inaccurate to use a one-dimensional model to describe the conduction state. The current density under the cathode is greater than that under the gate. That is, there is a two-dimensional memory effect. According to Poisson's equation, the electric field strength E and the space carrier density during the turn-off process

Correlation, as shown in formula (1). where the carrier density includes the space charge that forms the current

and substrate doping charge

. During the expansion of the depletion layer, the stored charge in the N-base region is continuously swept away, and because the density of stored charges under the cathode is relatively high, the current density under the cathode is relatively large during the process of sweeping away the carriers in the N-base region, and the space charge brought by the current Make the electric field intensity under the cathode larger.

（1）

(1)

（2）

(2)

是硅的介电常数，q是单位电荷量。 in,

is the dielectric constant of silicon, and q is the unit charge.

Therefore, the uneven distribution of the current density in the steady state directly leads to the uneven distribution of the electric field intensity during the turn-off process. If the electric field intensity under the cathode is greater, the hole-electron pairs generated by the dynamic avalanche will further increase when they flow from the cathode to the gate. The lateral pressure drop in the body is reduced, which is likely to cause shutdown failure.

In the traditional structure, the lifetime of minority carriers in the chip is consistent. The embodiment of the present invention proposes a semiconductor device with non-uniform distribution of space lifetime, each cell structure of which can be divided into two parts, A and B, wherein the A region is the low lifetime region (the first region), and the B region is the high lifetime region (Second area), as shown in Figure 4, the first area is the area below the cathode, distributed longitudinally from the cathode to the anode, and the second area is the area below the gate, distributed longitudinally from the gate to the anode. Areas A and B have the following characteristics:

1. The minority carrier lifetime in the A region can be uniformly distributed, and its minority carrier lifetime is lower than that of the B region; it can also be non-uniformly distributed, and the maximum minority carrier lifetime is not greater than that of the B region;

2. The width of the A area is 0-400um (excluding 0um), and the typical width is the same as the cathode width, about 200um;

3. The minority carrier lifetime in the B region can be the original lifetime, that is, no additional irradiation defects are introduced, or uniform irradiation defects can be introduced, but the minority carrier lifetime is still higher than that in the A region;

In a semiconductor device with a non-uniform distribution of spatial lifetime, due to the lower lifetime of the A region and the smaller carrier diffusion length, the carrier concentration in this region is reduced in the on-state, even lower than that of the B region. Then, during the establishment of the electric field, the electric field strength under the gate is greater than that under the cathode, so that the electron-hole pairs generated by the dynamic avalanche flow directly to the gate without additionally increasing the lateral voltage drop in the chip body, thereby increasing the turn-off current capability.

The present invention also provides a manufacturing method of a semiconductor device with a non-uniform distribution of space life. In order to form a region A with a uniform distribution of minority carrier lifetimes, additional baffles can be introduced into the A region through electron irradiation (non-uniform electron irradiation) defects, so that the minority carrier lifetime in the A region is lower than that in the B region. As shown in Figure 5, after adding a baffle above the gate, the cell is irradiated with electrons, so that the minority carrier lifetime under the cathode is reduced.

In another embodiment, the minority carrier lifetimes of the region A are non-uniformly distributed. Exemplarily, the region A is longitudinally divided into a plurality of A1 regions and A2 regions that are distributed alternately. Among them, "A1", "A2" and "A" are only used to identify regions with different parameter characteristics (such as average minority carrier lifetime). The A2 area introduces additional defects through proton irradiation. As shown in Figure 6, the direction from the cathode to the anode is the A1 area, the A2 area and the A1 area, and has the following characteristics:

1. The height H of the A2 area is 0-200um (excluding 0um), more preferably 20-40um;

2. The width W of the A2 area is 0-400um (excluding 0um), and the typical width is the same as the width of the cathode, about 200um;

3. The distance L from the A2 area to the cathode side is 0-600um (excluding 0um), more preferably 200-300um;

4. The lifetime of each A1 region can be the original minority carrier lifetime, or additional defects can be introduced through the above-mentioned electron irradiation;

5. The lifetime of area B can be the original minority carrier lifetime, or additional defects can be introduced by uniform (without baffle) electron irradiation;

6. The service life of the three areas should be B>=A1>A2.

In another embodiment, the direction from the cathode to the anode may also be set to be the A1 area and the A2 area in sequence.

Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: they can still modify the technical solutions described in the aforementioned embodiments, or perform equivalent replacements for some of the technical features; and these The modification or replacement does not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims (6)

1. A semiconductor device with non-uniform spatial lifetime distribution, wherein the minority carrier lifetime below the cathode is lower than the minority carrier lifetime below the gate;

the minority carrier lifetime longitudinal distribution under the cathode is non-uniform;

the maximum value of the minority carrier lifetime below the cathode is not more than the minority carrier lifetime below the gate electrode;

an A1 area and an A2 area are longitudinally distributed below the cathode, wherein the A1 area is arranged between the A2 area and the cathode;

the minority carrier lifetime of the A1 region is not more than the minority carrier lifetime below the gate electrode;

the minority carrier lifetime of the A2 region is less than that of the A1 region;

wherein the A2 region introduces additional defects by proton irradiation;

the A1 region introduces additional defects by electron irradiation.

2. The semiconductor device according to claim 1, wherein an A2 region and a plurality of A1 regions are longitudinally distributed below the cathode, wherein the A1 region, the A2 region and the A1 region are sequentially arranged from the cathode to the anode;

the minority carrier lifetime of the A1 region is not more than the minority carrier lifetime below the gate electrode;

the minority carrier lifetime of the A2 region is less than the minority carrier lifetime of the A1 region.

3. The semiconductor device according to claim 2,

the width of A2 region is less than 400um, and the height is less than 200um, and the side distance to the cathode is less than 600um.

4. The semiconductor device according to claim 3,

the width of the A2 area is the same as that of the cathode; and/or

The height of the A2 area is 20-40um; and/or

The A2 area is 200-300um away from the cathode side.

5. The semiconductor device according to any one of claims 1 to 4,

the semiconductor device is an IGCT, a thyristor or an IGBT.

6. A method of manufacturing a semiconductor device with a non-uniform distribution of spatial lifetimes, characterized in that the semiconductor device as claimed in any of claims 1 to 5 is formed by electron irradiation and proton irradiation.

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