CN114496921A - Manufacturing method of semiconductor device and semiconductor device - Google Patents

Abstract

The present application provides a method for fabricating a semiconductor device and a semiconductor device. The method for fabricating a semiconductor device includes: providing a substrate, where the substrate includes a high-voltage device region and a low-voltage device region; forming a first gate on the high-voltage device region; A second gate is formed on the low-voltage device region; a dielectric layer is formed on at least the exposed surface of the first gate and the exposed surface of the second gate, and the thickness of the dielectric layer on the sidewall of the first gate is the first The thickness of the dielectric layer on the sidewall of the second gate is the second thickness, and the first thickness is greater than the second thickness. The manufacturing method of the semiconductor device of the present application solves the technical problem that the high-voltage device region has a large hot carrier injection effect, which degrades or damages the performance of the semiconductor device.

Description

Manufacturing method of semiconductor device and semiconductor device

technical field

The present application relates to the field of semiconductors, and in particular, to a method for fabricating a semiconductor device and a semiconductor device.

Background technique

In the prior art, the gate spacers of the high voltage (High Voltage, HV) device region and the low voltage (Low Voltage, LV) device region in the semiconductor device are both oxide layer-nitride layer structures. As the critical dimension of the semiconductor device shrinks, The gate spacers are also smaller, which can enhance the Hot Carrier Injection Effect (HCI) in the high-voltage device region, so that the performance of the semiconductor device is degraded or damaged.

The above information disclosed in this Background section is only for enhancement of understanding of the background of the technology described in this article and therefore it may contain certain information that does not form part of the already known in this country to a person of ordinary skill in the art known prior art.

SUMMARY OF THE INVENTION

The main purpose of the present application is to provide a method for fabricating a semiconductor device and a semiconductor device, so as to solve the problem that the HCI in the high-voltage device region affects the performance of the semiconductor device in the prior art.

In order to achieve the above object, according to an aspect of the present application, a method for fabricating a semiconductor device is provided, including: providing a substrate, the substrate including a high-voltage device region and a low-voltage device region; forming a first semiconductor device on the high-voltage device region a gate, and a second gate is formed on the low-voltage device region; a dielectric layer is formed on at least the exposed surface of the first gate and the exposed surface of the second gate, located on the first gate The thickness of the dielectric layer on the sidewall of the gate is a first thickness, the thickness of the dielectric layer on the sidewall of the second gate is a second thickness, and the first thickness is greater than the second thickness thickness.

Optionally, forming a dielectric layer on at least the exposed surface of the first gate and the exposed surface of the second gate includes: forming the substrate, the first gate and the second gate A first dielectric sublayer, a second dielectric sublayer and a third dielectric sublayer are sequentially stacked on the exposed surface of the gate; a part of the third dielectric sublayer is removed and remains on the sidewall of the first gate the third dielectric sublayer; remove part of the second dielectric sublayer, leaving the second dielectric on the sidewall of the first gate and the sidewall of the second gate Sublayers, the first dielectric sublayer, the reserved second dielectric sublayer, and the reserved third dielectric sublayer constitute the dielectric layer.

Optionally, removing part of the third dielectric sublayer includes: implanting a predetermined element into the third dielectric sublayer on the surface of the second gate, and the third dielectric after implanting the predetermined element A sublayer forms a dielectric bulk layer; removing the dielectric bulk layer, the third dielectric sublayer on a surface of the substrate, and the dielectric bulk on a surface of the first gate away from the substrate The third dielectric sublayer.

Optionally, implanting a predetermined element into the third dielectric sublayer on the second gate surface includes: forming on the exposed surface of the third dielectric sublayer on the first gate surface A sacrificial layer; injecting the predetermined element into the third dielectric sub-layer not shielded by the sacrificial layer to obtain the dielectric loose layer; removing the sacrificial layer.

Optionally, the first dielectric sublayer includes silicon oxide, the second dielectric sublayer includes silicon nitride, and the third dielectric sublayer includes silicon oxide.

Optionally, the predetermined element is an inert element.

According to another aspect of the present application, a semiconductor device is also provided, comprising: a substrate including a high-voltage device region and a low-voltage device region; a first gate electrode and a second gate electrode, the first gate electrode being located at the high-voltage device region On the device region, the second gate is located on the low-voltage device region; a dielectric layer, covering at least the first gate and the second gate, is located on all the sidewalls of the first gate The thickness of the dielectric layer is a first thickness, the thickness of the dielectric layer on the sidewall of the second gate is a second thickness, and the first thickness is greater than the second thickness.

Optionally, the dielectric layer includes: a first dielectric sublayer located on the sidewall of the first gate and the sidewall of the second gate; a second dielectric sublayer located on the first gate on the surface of the dielectric sublayer away from the sidewall of the first gate, and on the surface of the first dielectric sublayer away from the sidewall of the second gate; a third dielectric sublayer, located on the on the surface of the second dielectric sublayer away from the sidewall of the first gate.

Optionally, the material of the first dielectric sublayer includes silicon oxide, the material of the second dielectric sublayer includes silicon nitride, and the material of the third dielectric sublayer includes silicon oxide.

Optionally, the semiconductor device further includes: a gate oxide layer including a high voltage gate oxide layer and a low voltage gate oxide layer, the high voltage gate oxide layer is located between the high voltage device region and the first gate, the A low voltage gate oxide layer is located between the low voltage device region and the second gate electrode.

Optionally, the thickness of the high voltage gate oxide layer is greater than the thickness of the low voltage gate oxide layer.

Applying the technical solution of the present application, in the manufacturing method of the semiconductor device, a substrate including a high-voltage device region and a low-voltage device region is first provided, and then a first gate and a second gate are respectively formed on the high-voltage device region and the low-voltage device region. gate, and finally, a dielectric layer is formed on at least the exposed surfaces of the first gate and the second gate, and the thickness of the dielectric layer on the sidewall of the first gate is greater than that of the second gate The thickness of the dielectric layer on the sidewall, that is, the thickness of the sidewall of the first gate electrode on the high-voltage device region is greater than that of the low-voltage device region. In the manufacturing method of the present application, by increasing the thickness of the sidewall of the gate on the high-voltage device region, the hot carrier injection effect of the high-voltage device region is ensured to be small, and the impact of the hot carrier injection effect on the semiconductor device is alleviated. It solves the problem of the performance degradation or damage of the semiconductor device caused by the large hot carrier injection effect in the high-voltage device region in the prior art. At the same time, since the high-voltage device region and the low-voltage device region have different sensitivities to HCI, the sidewall thickness of the gate on the low-voltage device region is smaller than that on the high-voltage device region, thus ensuring the high-voltage device. While the HCI in the low-voltage device region is relatively small, the performance of the device in the low-voltage device region is basically not affected.

Description of drawings

The accompanying drawings that form a part of the present application are used to provide further understanding of the present application, and the schematic embodiments and descriptions of the present application are used to explain the present application and do not constitute improper limitations on the present application. In the attached image:

FIG. 1 shows a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of the present application;

FIG. 2 to FIG. 5 are schematic diagrams of structures formed after different process steps in the method for fabricating a semiconductor device according to the present application.

Wherein, the above-mentioned drawings include the following reference signs:

100, shallow trench isolation structure; 101, substrate; 102, low voltage gate oxide layer; 103, first dielectric sublayer; 104, second dielectric sublayer; 105, third dielectric sublayer; 106, high voltage gate oxide layer; 201, a first gate; 202, a second gate; 301, a high voltage device region; 302, a low voltage device region; 401, a sacrificial layer.

Detailed ways

It should be noted that the following detailed description is exemplary and intended to provide further explanation of the application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

It should be noted that the terminology used herein is for the purpose of describing specific embodiments only, and is not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly dictates otherwise, the singular is intended to include the plural as well, furthermore, it is to be understood that when the terms "comprising" and/or "including" are used in this specification, it indicates that There are features, steps, operations, devices, components and/or combinations thereof.

It should be noted that the embodiments in the present application and the features of the embodiments may be combined with each other in the case of no conflict. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

In order to make those skilled in the art better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only The embodiments are part of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the scope of protection of the present application.

It should be noted that the terms "first", "second", etc. in the description and claims of the present application and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific sequence or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances for the embodiments of the application described herein. Furthermore, the terms "comprising" and "having" and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those expressly listed Rather, those steps or units may include other steps or units not expressly listed or inherent to these processes, methods, products or devices.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element can be "directly connected" to the other element or "connected" to the other element through a third element.

As described in the background art, the main purpose of the present application is to provide a method for fabricating a semiconductor device and a semiconductor device, so as to solve the problem that the HCI in the high-voltage device region affects the performance of the semiconductor device in the prior art.

According to an embodiment of the present application, a method for fabricating a semiconductor device is provided. 1 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present application. As shown in FIGS. 1 to 5 , the method for fabricating a semiconductor device includes the following steps:

In step S101, a substrate 101 is provided, and the substrate includes a high-voltage device region 301 and a low-voltage device region 302;

Step S102, forming a first gate 201 on the high-voltage device region 301, and forming a second gate 202 on the low-voltage device region 302;

In step S103, a dielectric layer is formed on at least the exposed surface of the first gate 201 and the exposed surface of the second gate 202, and the thickness of the dielectric layer on the sidewall of the first gate 201 is the first Thickness, the thickness of the dielectric layer located on the sidewall of the second gate 202 is the second thickness, the first thickness is greater than the second thickness, and the structure shown in FIG. 5 is obtained.

In the above-mentioned manufacturing method of a semiconductor device, a substrate including a high-voltage device region and a low-voltage device region is first provided, then a first gate and a second gate are formed on the high-voltage device region and the low-voltage device region, respectively, and finally, at least the above A dielectric layer is formed on the exposed surfaces of the first gate and the second gate, and the thickness of the dielectric layer on the sidewall of the first gate is greater than the thickness of the dielectric layer on the sidewall of the second gate, that is, a high-voltage device The thickness of the sidewall of the first gate on the region is greater than the thickness of the sidewall of the low voltage device region. The above-mentioned manufacturing method of the present application ensures that the hot carrier injection effect in the high-voltage device region is small by thickening the sidewall thickness of the gate on the high-voltage device region, and alleviates the damage to the semiconductor device caused by the hot-carrier injection effect. , which solves the problem in the prior art that the hot carrier injection effect in the high-voltage device region is large, which causes the performance of the semiconductor device to degrade or damage. At the same time, since the high-voltage device region and the low-voltage device region have different sensitivities to HCI, the sidewall thickness of the gate on the low-voltage device region is smaller than that on the high-voltage device region, thus ensuring the high-voltage device. While the HCI in the low-voltage device region is relatively small, the performance of the device in the low-voltage device region is basically not affected.

Specifically, the above-mentioned second thickness of the present application is the same as the thickness of the sidewall of the gate on the low-voltage device region in the prior art, and the above-mentioned first thickness is greater than the above-mentioned second thickness, that is, the present application ensures the thickness of the gate on the low-voltage device region. Under the condition that the thickness of the sidewall remains unchanged, the thickness of the sidewall of the gate on the high-voltage device region is increased, so that the damage to the semiconductor device caused by the HCI in the high-voltage device region is alleviated under the condition that the device performance in the low-voltage region is not degraded.

It should be noted that, each step in the above-mentioned embodiment of forming the substrate can be implemented in a feasible manner in the prior art. The substrates in the above-mentioned bases can be selected according to the actual needs of the device, and can include silicon substrates, germanium substrates, silicon germanium substrates, SOI (silicon on insulator, Silicon On Insulator) substrates or GOI (germanium on insulator, Germaniun On Insulator) substrates. Insulator) substrate. In other embodiments, the above-mentioned substrate may also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP or SiC, etc., may also be a stacked structure, such as Si/SiGe, etc., and may also be other epitaxial structures , such as SGOI (silicon germanium on insulator) and so on. Of course, it can also be other substrates available in the prior art.

In an actual application process, the above-mentioned high-voltage device region is used to form a high-voltage device, and the above-mentioned low-voltage device region is used to form a low-voltage device.

In a specific embodiment, as shown in FIGS. 2 to 5 , a shallow trench isolation structure 100 is provided between the low-voltage device region 302 and the high-voltage device region 301 . The above-mentioned shallow trench isolation structure is used to define an active region or to isolate devices, so that the devices will not be connected to cause a short circuit problem.

According to another specific embodiment of the present application, forming a dielectric layer on at least the exposed surface of the first gate and the exposed surface of the second gate includes: as shown in FIG. 2 , on the substrate 101 , The first dielectric sub-layer 103, the second dielectric sub-layer 104 and the third dielectric sub-layer 105 are sequentially stacked on the exposed surfaces of the first gate 201 and the second gate 202; remove part of the third dielectric sub-layer Layer 105, retaining the above-mentioned third dielectric sub-layer 105 located on the sidewall of the above-mentioned first gate 201 to obtain the structure shown in FIG. 4; removing part of the above-mentioned second dielectric sub-layer 104, leaving the above-mentioned first gate. The second dielectric sublayer 104 on the sidewall of the electrode 201 and on the sidewall of the second gate 202, the first dielectric sublayer 103, the remaining second dielectric sublayer 104, and the remaining third dielectric sublayer 104 The dielectric sublayer 105 constitutes the above-mentioned dielectric layer, and the structure shown in FIG. 5 is obtained. Compared with the prior art, two dielectric layers are arranged on the sidewall of the low-voltage device region and the sidewall of the high-voltage device region. The dielectric sublayer on the sidewall of the device area is increased from two layers to three layers, which improves the hot carrier injection effect of the above-mentioned high-voltage device area, thereby further ensuring that the damage of the hot carrier injection effect to the semiconductor device is alleviated. The above-mentioned low-voltage device region maintains the original performance, further ensuring that the saturated drain current of the low-voltage device region is small, and the response speed of the low-voltage device region is fast.

In an actual application process, the above-mentioned first, second, and third dielectric sublayers can all use feasible materials in the prior art. In a specific embodiment, the first dielectric sublayer includes silicon oxide, the second dielectric sublayer includes silicon nitride, and the third dielectric sublayer includes silicon oxide. In a more specific embodiment, the first dielectric sub-layer is silicon oxide, the second dielectric sub-layer is silicon nitride, and the third dielectric sub-layer is silicon oxide.

According to another specific embodiment of the present application, removing part of the third dielectric sublayer includes: implanting a predetermined element into the third dielectric sublayer on the surface of the second gate electrode, and after implanting the predetermined element, the The third dielectric sublayer forms a dielectric bulk layer; the dielectric bulk layer, the third dielectric sublayer located on the surface of the substrate, and the third dielectric located on the surface of the first gate away from the substrate are removed sublayer. By injecting predetermined elements into the third dielectric sublayer on the surface of the second gate electrode, the oxidation etching selectivity of the third dielectric sublayer on the surface of the second gate electrode is changed, so that only the first gate electrode is removed in the above-mentioned removing step. The above-mentioned third dielectric sublayer and the above-mentioned dielectric loose layer on the surface far away from the above-mentioned substrate, the third dielectric sub-layer on the side wall of the first gate is reserved, which further ensures that the thickness of the side wall of the high-voltage device region is relatively high. Thickness, which further ensures that the hot carrier injection effect of the fabricated semiconductor device is small, and at the same time, compared with the prior art, it further ensures that the thickness of the sidewall of the low-voltage device region remains unchanged, thereby further ensuring the saturation of the low-voltage device region. The drain current is smaller and the response speed of the low voltage device region is faster.

It should be noted that the technical means for removing the third dielectric sub-layer on the first predetermined surface is not limited to the above-mentioned process, and those skilled in the art can also use other feasible methods in the prior art.

In a specific embodiment, the above-mentioned predetermined elements are inert elements, such as nitrogen elements, argon elements, and the like.

In order to obtain the above-mentioned intermediate structure more easily, according to another specific embodiment of the present application, as shown in FIG. 2 and FIG. 3 , a predetermined elements, including: forming a sacrificial layer 401 on the exposed surface of the third dielectric sub-layer 105 located on the surface of the first gate 201; injecting the predetermined element into the third dielectric sub-layer 105 not covered by the sacrificial layer , to obtain the above-mentioned dielectric loose layer; and remove the above-mentioned sacrificial layer 401 . By shielding the third dielectric layer on the surface of the first gate by the sacrificial layer, the lattice structure of the third dielectric layer there can be prevented from being damaged, thereby facilitating the subsequent easy removal of the dielectric loose layer.

In a specific embodiment, the sacrificial layer is a photoresist layer. There are also many methods for forming the above-mentioned photoresist layer of the present application, and those skilled in the art can select an appropriate method to form the above-mentioned photoresist layer of the present application according to the actual situation.

In a specific embodiment, after the substrate is provided, the first gate is formed on the high-voltage device region, and before the second gate is formed on the low-voltage device region, the method further includes: forming on the substrate. The gate oxide layer, as shown in FIG. 2 to FIG. 5 , the gate oxide layer includes a high-voltage gate oxide layer 106 and a low-voltage gate oxide layer 102 , the high-voltage gate oxide layer 106 is located on the surface of the high-voltage device region 301 , and the low-voltage gate oxide layer Layer 102 is located on the surface of low voltage device region 302 described above. The thickness of the high-voltage gate oxide layer is greater than that of the low-voltage gate oxide layer, and the thickness of the high-voltage gate oxide layer is larger, and the larger thickness enables the high-voltage device region to have a stronger pressure bearing capacity.

Both the material of the high voltage gate oxide layer and the material of the low voltage gate oxide layer include silicon oxide. In a more specific embodiment, the material of the high voltage gate oxide layer and the material of the low voltage gate oxide layer are both silicon oxide.

The above-mentioned structural layers can be formed by one of molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), metal organic vapor phase epitaxy (MOVPE), hydride vapor phase epitaxy (HVPE) and/or other well-known crystal growth processes. one or more forms.

It should be noted that, in the above-mentioned embodiments of the present application, the reasons why the device performance of the low-voltage device region can be maintained without degradation include the following: the lattice structure of the third dielectric sublayer at the sidewall of the second gate is destroyed by ion implantation. , so that it becomes loose. Under the same etching conditions, the loose structure is etched faster, so that in the subsequent etching process, the third dielectric sublayer at the sidewall of the first gate still has large When partially remaining, the loose third dielectric sublayer has been removed. Therefore, the thickness of the dielectric layer at the sidewall of the second gate will not be increased, so that when the source and drain terminals are formed by subsequent ion implantation, the range of the ion implantation area blocked by the dielectric layer is small, and the formed source and drain terminals have a smaller range. The spacing between them will not become larger, so that the response speed of the device will not become slower. The reasons for improving the hot carrier injection effect in the high-voltage device region include the following: the thickness of the dielectric layer at the sidewall of the first gate on the high-voltage device region is relatively thick, so that during subsequent high-concentration ion implantation, the above-mentioned high-voltage device The sidewall of the region can generate a section of LDD region between the high-concentration source-drain and the gate, which can define the source-drain distance of the MOS transistor more accurately, which avoids excessive source and drain ion implantation. close to the channel region, which causes the channel to be too short or even the source and drain are connected. In addition, the sidewall structure can also play a role in protecting the first gate, so that the first gate can be etched or ion implanted later. without damage.

According to another typical embodiment of the present application, a semiconductor device is provided, and the above-mentioned semiconductor device is manufactured by any one of the above-mentioned manufacturing methods of a semiconductor device.

The above-mentioned semiconductor device is obtained by adopting any of the above-mentioned manufacturing methods of the semiconductor device. This method ensures that the hot carrier injection effect of the above-mentioned high-voltage device region is small by thickening the sidewall thickness of the gate on the high-voltage device region. , the damage to the semiconductor device caused by the hot carrier injection effect is alleviated, and the problem that the hot carrier injection effect in the high-voltage device region in the prior art is large and the performance of the semiconductor device is degraded or damaged is solved. At the same time, since the high-voltage device region and the low-voltage device region have different sensitivities to HCI, the sidewall thickness of the gate on the low-voltage device region is smaller than that on the high-voltage device region, thus ensuring the high-voltage device. While the HCI in the low-voltage device region is relatively small, the performance of the device in the low-voltage device region is basically not affected.

According to another typical embodiment of the present application, a semiconductor device is provided, including: a substrate, a first gate, a second gate, and a dielectric layer, wherein the substrate includes a high-voltage device region and a low-voltage device region The above-mentioned first gate is located on the above-mentioned high-voltage device region, and the above-mentioned second gate is located on the above-mentioned low-voltage device region; the above-mentioned dielectric layer covers at least the above-mentioned first gate and the above-mentioned second gate, and is located on the side of the above-mentioned first gate The thickness of the dielectric layer on the wall is a first thickness, the thickness of the dielectric layer on the sidewall of the second gate is a second thickness, and the first thickness is greater than the second thickness.

The above-mentioned semiconductor device includes a substrate having a high-voltage device region and a low-voltage device region, a first gate located on the high-voltage device region and a second gate located on the low-voltage device region, and also includes the first gate and the above-mentioned The dielectric layer on the surface of the second gate, and the thickness of the dielectric layer on the sidewall of the first gate is greater than the thickness of the dielectric layer on the sidewall of the second gate, that is, the thickness of the first gate on the high-voltage device region The sidewall thickness is greater than the sidewall thickness of the low voltage device region. The above-mentioned manufacturing method of the present application ensures that the hot carrier injection effect in the high-voltage device region is small by thickening the sidewall thickness of the gate on the high-voltage device region, and alleviates the damage to the semiconductor device caused by the hot-carrier injection effect. , which solves the problem in the prior art that the hot carrier injection effect in the high-voltage device region is large, which causes the performance of the semiconductor device to degrade or damage. At the same time, since the high-voltage device region and the low-voltage device region have different sensitivities to HCI, the sidewall thickness of the gate on the low-voltage device region is smaller than that on the high-voltage device region, thus ensuring the high-voltage device. While the HCI in the low-voltage device region is relatively small, the performance of the device in the low-voltage device region is basically not affected.

According to another specific embodiment of the present application, the dielectric layer includes a first dielectric sublayer, which is located on the sidewall of the first gate and the sidewall of the second gate; the second dielectric sublayer is located on the sidewall of the first gate and the sidewall of the second gate. on the surface of the first dielectric sublayer away from the sidewall of the first gate, and on the surface of the first dielectric sublayer away from the sidewall of the second gate; the third dielectric sublayer is located on the first dielectric sublayer. On the surfaces of the two dielectric sublayers that are far away from the sidewalls of the first gate electrode. Compared with the prior art, two dielectric layers are arranged on the sidewall of the low-voltage device region and the sidewall of the high-voltage device region. The above-mentioned dielectric layers ensure the original two-layer dielectric sub-layers on the sidewall of the low-voltage device region. The dielectric sub-layers on the sidewall of the high-voltage device region are increased from two layers to three layers, which improves the hot carrier injection effect in the high-voltage device region, thereby further ensuring that the damage caused by the hot carrier injection effect to the semiconductor device is alleviated. In addition, the original performance of the low-voltage device region is maintained, which further ensures that the saturated drain current of the low-voltage device region is small and the response speed of the low-voltage device region is fast.

In an actual application process, the above-mentioned first, second, and third dielectric sublayers can all use feasible materials in the prior art. In a specific embodiment, the material of the first dielectric sub-layer includes silicon oxide, the material of the second dielectric sub-layer includes silicon nitride, and the material of the third dielectric sub-layer includes silicon oxide. In a more specific embodiment, the first dielectric sub-layer is silicon oxide, the second dielectric sub-layer is silicon nitride, and the third dielectric sub-layer is silicon oxide.

According to another specific embodiment of the present application, the semiconductor device further includes a gate oxide layer, the gate oxide layer includes a high-voltage gate oxide layer and a low-voltage gate oxide layer, and the high-voltage gate oxide layer is located between the high-voltage device region and the first gate oxide layer. Between the gates, the low-voltage gate oxide layer is located between the low-voltage device region and the second gate. The thickness of the high voltage gate oxide layer is greater than the thickness of the low voltage gate oxide layer. The thickness of the high-voltage gate oxide layer is larger, and the larger thickness enables the high-voltage device region to have a stronger pressure bearing capacity.

In the above-mentioned embodiments of the present invention, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

From the above description, it can be seen that the above-mentioned embodiments of the present application achieve the following technical effects:

1) In the manufacturing method of the above-mentioned semiconductor device of the present application, a substrate comprising a high-voltage device region and a low-voltage device region is first provided, then a first gate and a second gate are formed on the high-voltage device region and the low-voltage device region respectively, and finally forming a dielectric layer at least on the exposed surfaces of the first gate and the second gate, and the thickness of the dielectric layer on the sidewall of the first gate is greater than the thickness of the dielectric layer on the sidewall of the second gate , that is, the thickness of the sidewall of the first gate on the high-voltage device region is greater than that of the low-voltage device region. The above-mentioned manufacturing method of the present application ensures that the hot carrier injection effect in the high-voltage device region is small by thickening the sidewall thickness of the gate on the high-voltage device region, and alleviates the damage to the semiconductor device caused by the hot-carrier injection effect. , which solves the problem in the prior art that the hot carrier injection effect in the high-voltage device region is large, which causes the performance of the semiconductor device to degrade or damage. At the same time, since the high-voltage device region and the low-voltage device region have different sensitivities to HCI, the sidewall thickness of the gate on the low-voltage device region is smaller than that on the high-voltage device region, thus ensuring the high-voltage device. While the HCI in the low-voltage device region is relatively small, the performance of the device in the low-voltage device region is basically not affected.

2) The above-mentioned semiconductor device of the present application is obtained by adopting any one of the above-mentioned manufacturing methods of the semiconductor device, and the method ensures the hot carrier of the above-mentioned high-voltage device region by thickening the sidewall thickness of the gate on the high-voltage device region. The injection effect is small, the damage to the semiconductor device caused by the hot carrier injection effect is alleviated, and the problem that the hot carrier injection effect in the high-voltage device region in the prior art is large and the performance of the semiconductor device is degraded or damaged is solved. At the same time, since the high-voltage device region and the low-voltage device region have different sensitivities to HCI, the sidewall thickness of the gate on the low-voltage device region is smaller than that on the high-voltage device region, thus ensuring the high-voltage device. While the HCI in the low-voltage device region is relatively small, the performance of the device in the low-voltage device region is basically not affected.

3) The above-mentioned semiconductor device of the present application includes a substrate having a high-voltage device region and a low-voltage device region, a first gate located on the high-voltage device region, and a second gate located on the low-voltage device region, and also includes a first gate located on the above-mentioned first gate. The gate and the dielectric layer on the surface of the second gate, and the thickness of the dielectric layer on the sidewall of the first gate is greater than the thickness of the dielectric layer on the sidewall of the second gate, that is, the first gate on the high-voltage device region. The sidewall thickness of a gate is greater than the sidewall thickness of the low voltage device region. In the above-mentioned manufacturing method of the present application, by thickening the sidewall thickness of the gate on the high-voltage device region, the hot-carrier injection effect in the high-voltage device region is ensured to be small, and the damage to the semiconductor device caused by the hot-carrier injection effect is alleviated , which solves the problem in the prior art that the hot carrier injection effect in the high-voltage device region is large, which causes the performance of the semiconductor device to degrade or damage. At the same time, since the high-voltage device region and the low-voltage device region have different sensitivities to HCI, the sidewall thickness of the gate on the low-voltage device region is smaller than that on the high-voltage device region, thus ensuring the high-voltage device. While the HCI in the low-voltage device region is relatively small, the performance of the device in the low-voltage device region is basically not affected.

The above descriptions are only preferred embodiments of the present application, and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application shall be included within the protection scope of this application.

Claims (10)

1. A method for manufacturing a semiconductor device, comprising:

providing a substrate, wherein the substrate comprises a high-voltage device area and a low-voltage device area;

forming a first grid electrode on the high-voltage device area, and forming a second grid electrode on the low-voltage device area;

and forming dielectric layers at least on the exposed surface of the first grid electrode and the exposed surface of the second grid electrode, wherein the thickness of the dielectric layer on the side wall of the first grid electrode is a first thickness, the thickness of the dielectric layer on the side wall of the second grid electrode is a second thickness, and the first thickness is greater than the second thickness.

2. The method of claim 1, wherein forming a dielectric layer on at least an exposed surface of the first gate and an exposed surface of the second gate comprises:

sequentially superposing a first dielectric sublayer, a second dielectric sublayer and a third dielectric sublayer on the exposed surfaces of the substrate, the first grid and the second grid;

removing part of the third dielectric sublayer, and reserving part of the third dielectric sublayer positioned on the side wall of the first grid electrode;

and removing part of the second dielectric sublayer, and reserving part of the second dielectric sublayer on the side wall of the first gate and on the side wall of the second gate, wherein the first dielectric sublayer, the reserved part of the second dielectric sublayer and the reserved part of the third dielectric sublayer form the dielectric layer.

3. The method of claim 2, wherein removing a portion of the third dielectric sublayer comprises:

injecting a predetermined element into the third dielectric sublayer on the surface of the second gate, wherein the third dielectric sublayer after the predetermined element is injected forms a dielectric loose layer;

and removing the dielectric loose layer, the third dielectric sub-layer on the surface of the substrate and the third dielectric sub-layer on the surface of the first grid far away from the substrate.

4. The method of claim 3, wherein implanting a predetermined element into the third dielectric sublayer on the second gate surface comprises:

forming a sacrificial layer on an exposed surface of the third dielectric sublayer located on the first gate surface;

injecting the predetermined element into the third medium sub-layer which is not shielded by the sacrificial layer to obtain the medium loose layer;

and removing the sacrificial layer.

5. A method for manufacturing a semiconductor device according to claim 3 or 4, wherein the predetermined element is an inert element.

6. A semiconductor device, comprising:

a substrate including a high voltage device region and a low voltage device region;

the first grid electrode is positioned on the high-voltage device area, and the second grid electrode is positioned on the low-voltage device area;

and the dielectric layer at least covers the first grid electrode and the second grid electrode, the thickness of the dielectric layer on the side wall of the first grid electrode is a first thickness, the thickness of the dielectric layer on the side wall of the second grid electrode is a second thickness, and the first thickness is larger than the second thickness.

7. The semiconductor device of claim 6, wherein the dielectric layer comprises:

the first dielectric sublayer is positioned on the side wall of the first grid electrode and the side wall of the second grid electrode;

the second dielectric sublayer is positioned on the surface of the side wall of the first dielectric sublayer, which is far away from the first grid electrode, and the surface of the side wall of the first dielectric sublayer, which is far away from the second grid electrode;

and the third dielectric sublayer is positioned on the surface of the side wall of the second dielectric sublayer, which is far away from the first grid electrode.

8. The semiconductor device of claim 7, wherein the material of the first dielectric sublayer comprises silicon oxide, the material of the second dielectric sublayer comprises silicon nitride, and the material of the third dielectric sublayer comprises silicon oxide.

9. The semiconductor device according to any one of claims 6 to 8, further comprising:

and the gate oxide layer comprises a high-voltage gate oxide layer and a low-voltage gate oxide layer, the high-voltage gate oxide layer is positioned between the high-voltage device area and the first grid electrode, and the low-voltage gate oxide layer is positioned between the low-voltage device area and the second grid electrode.

10. The semiconductor device of claim 9, wherein a thickness of the high voltage gate oxide layer is greater than a thickness of the low voltage gate oxide layer.

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