CN114496905A - Preparation method of semiconductor structure and semiconductor structure - Google Patents

Abstract

The invention provides a preparation method of a semiconductor structure and a semiconductor structure. The method includes: providing a semiconductor substrate, on which a contact hole is formed; forming a SiGe layer at the bottom of the contact hole; depositing an ohmic metal layer on the SiGe layer; A cover metal layer is deposited above the layer; after heat treatment of the ohmic metal layer, the cover metal layer is removed; a diffusion barrier layer and a main metal layer are deposited on the ohmic metal layer after removing the cover metal layer; a SiGe layer is pre-formed inside the contact hole, Germanium silicide can be formed inside the contact hole; since Ge has a faster electron movement rate than Si, it can achieve lower resistivity and ensure the performance of the semiconductor structure; and it does not need to consume a lot of silicon substrate when forming the metal structure, improving The formation position of germanium silicide ensures a shallow junction between the ohmic contact metal structure and the silicon substrate; because the consumption of the silicon substrate is reduced, the non-uniformity of germanium silicide is improved.

Description

A kind of preparation method of semiconductor structure and semiconductor structure

technical field

The invention belongs to the technical field of semiconductors, and in particular relates to a preparation method of a semiconductor structure and a semiconductor structure.

Background technique

For a semiconductor device formed on a silicon substrate, in order to have stable ohmic contact between the metal and the silicon substrate, it is generally necessary to form various silicide substances between the metal and the silicon according to the type and application of the storage device.

In the prior art, the metal structure of ohmic contact is formed by using metal silicides such as TiSi2 and CoSi. Although it is relatively refractory and has high thermal stability, it consumes a large amount of silicon substrate during the formation process. Therefore, when the size of the ohmic contact becomes smaller and smaller, for example, for memory devices below 20 nm, there will be a phenomenon of uneven agglomeration and a phenomenon of high resistivity.

Other traditional technologies also use NiSi or noble metal silicide, which consumes relatively little silicon substrate, to achieve ohmic contact metal structures. Although the resistivity of NiSi and precious metal compounds is lower than that of TiSi2 and CoSi2, the subsequent preparation processes need to be maintained below 600 °C. However, in a storage device such as a dynamic random access memory (DRAM), there are many processes in which the subsequent preparation process is above 600° C., so this preparation method is difficult to apply.

SUMMARY OF THE INVENTION

In view of the problems existing in the prior art, the embodiments of the present invention provide a method for preparing a semiconductor structure and a semiconductor structure, which are used to solve the problems of high resistivity and high electrical resistance when the ohmic contact metal structure is produced in the prior art when the semiconductor structure is prepared. The agglomeration phenomenon, or the inability to meet the requirements of the subsequent process, makes it impossible to prepare a stable ohmic contact metal structure, thereby affecting the performance of the semiconductor structure.

The present invention provides a method for preparing a semiconductor structure, the method comprising:

providing a semiconductor substrate on which contact holes are formed;

forming a SiGe layer at the bottom of the contact hole;

depositing an ohmic metal layer over the SiGe layer;

depositing a capping metal layer over the ohmic metal layer;

Heat treatment is performed on the ohmic metal layer by a heat treatment process, so that the ohmic metal enters the SiGe layer to form germanium silicide;

removing the cover metal layer;

A diffusion barrier layer and a bulk metal layer are deposited over the ohmic metal layer after removal of the cap metal layer.

Optionally, the semiconductor substrate includes an active region, and the contact hole exposes the active region of the semiconductor substrate; or the semiconductor substrate includes a gate conductor layer, and the contact hole exposes the gate of the semiconductor substrate a conductor layer; or the semiconductor substrate includes a metal layer, and the contact hole exposes the metal layer on the semiconductor substrate.

Optionally, the germanium silicide specifically includes: at least one of TiSiGe, CoSiGe and NiSiGe.

Optionally, forming the SiGe layer at the bottom of the contact hole includes:

Using PVD process, CVD process, ALD process or Epitaxy process to deposit on the bottom of the contact hole to form the SiGe layer, the thickness of the SiGe layer is

Optionally, a PVD process, a CVD process, an ALD process or an Epitaxy process is used to deposit on the bottom of the contact hole, and when the SiGe layer is formed, the deposition temperature is 25-400°C.

Optionally, when the ohmic metal layer is heat treated by a heat treatment process, the heat treatment temperature is 400 to 1100° C., and the heat treatment time is 30 s to 30 min.

The present invention also provides a semiconductor structure, the semiconductor structure includes:

a semiconductor substrate, comprising contact holes on the semiconductor substrate;

SiGe layer, located at the bottom of the contact hole;

an ohmic metal layer located above the SiGe layer;

a diffusion barrier layer, located above the ohmic metal layer after removing the cover metal layer;

The main metal layer is located above the diffusion barrier layer; wherein, the silicide inside the contact hole is germanium silicide.

Optionally, the SiGe layer is in contact with an active region of the semiconductor substrate, in contact with a gate conductor layer on the semiconductor substrate, or in contact with a metal layer on the semiconductor substrate.

Optionally, the germanium silicide specifically includes: at least one of TiSiGe, CoSiGe and NiSiGe.

Optionally, the thickness of the SiGe layer is

The present invention provides a method for preparing a semiconductor structure and a semiconductor structure, the method comprising: providing a semiconductor substrate on which a contact hole is formed; forming a SiGe layer at the bottom of the contact hole; depositing ohmic metal on the SiGe layer layer; depositing a cover metal layer over the ohmic metal layer; thermally treating the ohmic metal layer with a heat treatment process, so that the ohmic metal enters the SiGe layer to form germanium silicide; removing the cover metal layer; A diffusion barrier layer and a main metal layer are deposited on the ohmic metal layer behind the metal layer; wherein, the silicide inside the contact hole is GermanoSilicide; in this way, when preparing the semiconductor structure, it is formed at the bottom of the contact hole in advance For the SiGe layer, after the preparation process is completed, GermanoSilicide, a germanosilicide, can be formed inside the contact hole; since the electron movement rate of Ge element is faster than that of Si element, the ohmic contact metal structure formed in this way can achieve lower resistivity and ensure thermal stability. It can ensure the overall performance of the semiconductor structure; and it does not need to consume a large amount of silicon substrate when forming the metal structure, which improves the formation position of GermanoSilicide, so it can ensure that the ohmic contact metal structure and the silicon substrate keep shallow junction; at the same time Because the consumption of the silicon substrate can be suppressed, the non-uniformity of germanium silicide can be improved; the preparation method of the metal structure provided by the present application does not need to limit the temperature conditions of the subsequent preparation process, thus improving the applicability of the metal structure, thereby improving the Suitability of semiconductor structures.

Description of drawings

FIG. 1 is a schematic diagram when contact holes are respectively located above an active region of a silicon substrate, above a gate conductor layer, and above a metal layer according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a semiconductor structure prepared when a contact hole is located above an active region of a silicon substrate according to an embodiment of the invention;

3 is a schematic diagram of a semiconductor structure prepared by a contact hole located above a gate conductor layer provided in an embodiment of the present invention;

FIG. 4 is a schematic diagram of a semiconductor structure prepared when a contact hole is located above a metal layer according to an embodiment of the present invention.

Detailed ways

In order to solve the problem that when the semiconductor structure is prepared in the prior art, the ohmic contact metal structure will have high resistivity and agglomeration, or it is not suitable for the requirements of the subsequent process, resulting in the inability to prepare a stable ohmic contact metal structure, which affects the semiconductor structure. The technical problem of overall performance, the present invention provides a preparation method of a semiconductor structure and a semiconductor structure.

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not to scale, some details have been exaggerated for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships are only exemplary, and in practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art should Regions/layers with different shapes, sizes, relative positions can be additionally designed as desired.

In the context of this disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. element. In addition, if a layer/element is "on" another layer/element in one orientation, then when the orientation is reversed, the layer/element can be "under" the other layer/element.

In the above description, technical details such as patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as those described above. Additionally, although the various embodiments have been described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

The technical solutions of the present invention will be further described in detail below through specific embodiments.

This embodiment provides a method for fabricating a semiconductor structure, which can be applied to the fabrication of a semiconductor structure contact plug or gold plug. For example, a device layer has been formed on a semiconductor substrate, and the device layer may be a MOSFET, including an active region, a gate region, and the like, and a metal layer may be formed on the semiconductor substrate. The active area, gate area and metal layer all need to be connected to the back-end circuit through contact plugs or metal plugs. As shown in the following figure, it is an applicable area of several embodiments of the present invention in the CMOS manufacturing process, but the application of the present invention is not limited to this. The application of the embodiments of the present invention will be described in detail below with reference to FIGS. 1 to 4 .

Referring to FIG. 1, a semiconductor substrate 101 is provided on which contact holes 102 are formed. The semiconductor substrate 101 may be a silicon substrate or a silicon germanium substrate, which is not limited herein. The semiconductor substrate 101 includes an active region 103, and the contact hole 102 can expose the active region 103 of the semiconductor substrate 101; or the semiconductor substrate 101 includes a gate conductor layer 104, and the contact hole 102 can expose the gate conductor layer 104 of the semiconductor substrate; or the semiconductor substrate 101 includes a gate conductor layer 104. The substrate 101 includes a metal layer 105 , and the contact hole 102 can expose the metal layer 105 on the semiconductor substrate 101 .

Specifically, referring to FIG. 2 , the contact hole 102 may be located above the active region 103 ; referring to FIG. 3 , the contact hole 102 may be located above the gate conductor layer 104 ; referring to FIG. 4 , the contact hole 102 may be located above the metal layer 105 . Here, no matter whether the position of the contact hole 102 is above the active region 103 , above the gate conductor layer 104 or above the metal layer 105 , the fabrication method of the semiconductor structure is the same. Here, the method for fabricating the semiconductor structure is illustrated by taking the position of the contact hole 102 above the active region 103 as an example.

Continuing to refer to FIG. 2 , after the contact hole 102 is formed, a SiGe layer needs to be formed at the bottom of the contact hole 102 , that is, after the SiGe layer is formed, the SiGe layer is in contact with the active region 103 of the semiconductor substrate 101 and is in contact with the gate conductor on the semiconductor substrate 101 Layer 104 contacts or is in contact with metal layer 105 on semiconductor substrate 101 . In this way, when the silicide silicide is subsequently formed, the silicide may be germanium silicide, for example, at least one of TiSiGe, CoSiGe and NiSiGe.

(5埃～100埃)，优选厚度可以为

Specifically, when the SiGe layer is formed at the bottom of the contact hole 102, a physical vapor deposition (PVD, Physical Vapor Deposition) process, a chemical vapor deposition (CVD, Chemical Vapor Deposition) process, and an atomic layer deposition (ALD, Atomic Layer Deposition) process can be used Or the epitaxy process is deposited at the bottom of the contact hole 102 to form a SiGe layer, and the thickness of the SiGe layer is

(5 angstroms to 100 angstroms), the preferred thickness can be

Here, when depositing on the bottom of the contact hole 102 by using the PVD process, the CVD process, the ALD process or the Epitaxy process to form the SiGe layer, the deposition temperature is 25-400°C.

It is worth noting that the deposition temperature corresponding to different processes may be different.

After the SiGe layer is formed, an ohmic metal layer 201 is deposited over the SiGe layer. Likewise, the ohmic metal layer 201 may be deposited over the SiGe layer using a PVD process, a CVD process, an ALD process, or a plasma enhanced chemical vapor deposition process (PECVD, Plasma Enhanced Chemical Vapor Deposition).

In order to prevent the ohmic metal layer 201 from being contaminated or corroded by subsequent processes, after the ohmic metal layer 201 is formed, a cover metal layer needs to be deposited over the ohmic metal layer 201 .

Likewise, a capping metal layer can be deposited over the ohmic metal layer 201 using a PVD process, a CVD process, an ALD process or a PECVD process.

After depositing the cover metal layer, heat treatment is performed on the deposited ohmic metal layer 201 by a heat treatment process, so that the ohmic metal can enter the SiGe layer to form germanium silicide. The heat treatment process may include: any one of an annealing furnace furnace, a rapid processing process RTP, and a laser annealing process.

As an optional embodiment, when the ohmic metal layer 201 is heat treated by a heat treatment process, the heat treatment temperature is 400˜1100° C., and the heat treatment time is 30 s˜30 min. The heat treatment temperature and heat treatment time may be different for different heat treatment processes.

After the heat treatment is completed, the cover metal layer is removed by stripping the wet etching process.

Then, a diffusion barrier layer diffusion barrier 202 and a main metal layer main metal 203 are deposited on the ohmic metal layer 201 after removing the cover metal layer. Wherein, the deposition of the diffusion barrier layer 202 is mainly to block the diffusion of some atoms and ensure the metal properties of the ohmic metal layer 201 .

After the diffusion barrier layer 202 and the main metal layer 203 are deposited, GermanoSilicide can be formed inside the contact hole 102 . The germanoSilicide specifically includes: at least one of TiSiGe, CoSiGe and NiSiGe. Wherein, the diffusion barrier layer may include: TiN, TaN, TiW or WN. The host metal layer may be at least one of W, Al, Cu, Co, and Ru.

Here, the ohmic metal layer 201, the capping metal layer and the diffusion barrier layer 202 may be sequentially performed in separate deposition chambers.

In this way, since the electron movement rate of Ge element is faster than that of Si element, the formed ohmic contact metal structure can achieve lower resistivity, ensure thermal stability, and thus ensure the performance of semiconductor structure; and no consumption is required when forming the metal structure A large number of silicon substrates improve the formation position of GermanoSilicide, so it can ensure the shallow junction between the semiconductor structure and the silicon substrate; at the same time, because the consumption of the silicon substrate is reduced, the non-uniformity of GermanoSilicide can be improved. The performance of the metal structure; the preparation method of the semiconductor structure provided by the present application also does not need to limit the temperature conditions of the subsequent preparation process, and the temperature of the subsequent process does not need to be limited below 600 degrees, thus improving the applicability of the metal structure.

This embodiment also provides a semiconductor structure, as shown in FIG. 2 to FIG. 4 , the semiconductor structure includes: a semiconductor substrate 101 , a SiGe layer, an ohmic metal layer 201 , a diffusion barrier layer 202 , and a body metal layer 203 ;

a semiconductor substrate 101, the semiconductor substrate 101 includes a contact hole 102;

SiGe layer, located at the bottom of the contact hole 102;

The ohmic metal layer 201 is located above the SiGe layer;

The diffusion barrier layer 202 is located above the ohmic metal layer 201 after removing the covering metal layer;

The main metal layer 203 is located above the diffusion barrier layer 202;

The silicide at the bottom of the contact hole 102 is GermanoSilicide, which specifically includes: at least one of TiSiGe, CoSiGe and NiSiGe; the thickness of the SiGe layer is

Here, the preparation method of the semiconductor structure has been described in detail above, so it will not be repeated here.

The embodiments of the present invention can also be applied to contact manufacturing in other fields such as DRAM, NAND, and MEMS, and the application method can refer to the description of the above embodiments.

The method for preparing a semiconductor structure and the beneficial effects brought by the semiconductor structure provided by the embodiments of the present invention are at least as follows:

The invention provides a preparation method of a semiconductor structure and a semiconductor structure, the method comprising: providing a semiconductor substrate, on which a contact hole is formed; forming a SiGe layer at the bottom of the contact hole; depositing an ohmic metal layer on the SiGe layer; depositing a cover metal layer over the ohmic metal layer; thermally treating the ohmic metal layer with a heat treatment process so that the ohmic metal enters the SiGe layer to form germanium silicide; removing the cover metal layer; A diffusion barrier layer and a main metal layer are deposited above the ohmic metal layer; wherein, the silicide at the bottom of the contact hole is GermanoSilicide; thus, when preparing the semiconductor structure, a SiGe layer is formed at the bottom of the contact hole in advance, and the silicide at the bottom of the contact hole is GermanoSilicide. After the preparation process is completed, GermanoSilicide can be formed inside the contact hole; since the electron movement rate of the Ge element is faster than that of the Si element, the semiconductor structure formed in this way can achieve a lower resistivity, ensure thermal stability, and then ensure the semiconductor structure. The overall performance of the structure; and it does not need to consume a large amount of silicon substrate when forming the metal structure, which improves the formation position of GermanoSilicide, so it can ensure that the ohmic contact metal structure and the silicon substrate keep a shallow junction; at the same time, because the silicon substrate can be inhibited Therefore, the non-uniformity of germanium silicide can be improved; the preparation method provided by the present application also does not need to limit the temperature conditions of the subsequent preparation process, thus improving the applicability of metal structures and thus improving the applicability of semiconductor structures.

The above are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention shall be included in the within the protection scope of the present invention.

Claims (10)

1. A method of fabricating a semiconductor structure, the method comprising:

providing a semiconductor substrate, wherein a contact hole is formed on the semiconductor substrate;

forming a SiGe layer at the bottom of the contact hole;

depositing an ohmic metal layer over the SiGe layer;

depositing a cover metal layer over the ohmic metal layer;

carrying out heat treatment on the ohmic metal layer by using a heat treatment process so as to enable the ohmic metal to enter the SiGe layer to form germanosilicide;

removing the covering metal layer;

and depositing a diffusion barrier layer and a main metal layer above the ohmic metal layer after the cover metal layer is removed.

2. The method of claim 1, wherein the semiconductor substrate includes an active region thereon, and the contact hole exposes the active region of the semiconductor substrate; or the semiconductor substrate comprises a gate conductor layer, and the contact hole exposes the gate conductor layer of the semiconductor substrate; or the semiconductor substrate comprises a metal layer, and the contact hole exposes the metal layer on the semiconductor substrate.

3. The method of claim 1, wherein the germanosilicide specifically comprises: at least one of TiSiGe, CoSiGe and NiSiGe.

4. The method of claim 1, wherein forming a SiGe layer at the bottom of the contact hole comprises:

depositing on the bottom of the contact hole by using a PVD (physical vapor deposition) process, a CVD (chemical vapor deposition) process, an ALD (atomic layer deposition) process or an Epitaxy process to form the SiGe layer; the thickness of the SiGe layer is

5. The method of claim 4, wherein the SiGe layer is formed at a deposition temperature of 25-400 ℃ by performing a deposition on the bottom of the contact hole using a PVD process, a CVD process, an ALD process, or an Epitaxy process.

6. The method according to claim 1, wherein the ohmic metal layer is heat-treated by a heat treatment process at a temperature of 400 to 1100 ℃ for a time of 30s to 30 min.

7. A semiconductor structure, comprising:

the semiconductor substrate comprises a contact hole;

the SiGe layer is positioned at the bottom of the contact hole;

the ohmic metal layer is positioned above the SiGe layer;

the diffusion barrier layer is positioned above the ohmic metal layer after the covering metal layer is removed;

a body metal layer located over the diffusion barrier layer; the silicide in the contact hole is germanosilicide.

8. The semiconductor structure of claim 7, wherein the SiGe layer is in contact with an active region of the semiconductor substrate, in contact with a gate conductor layer on a semiconductor substrate, or in contact with a metal layer on a semiconductor substrate.

9. The semiconductor structure of claim 7, wherein the germanosilicide comprises in particular: at least one of TiSiGe, CoSiGe and NiSiGe.

10. The semiconductor structure of claim 7, wherein the SiGe layer has a thickness of

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