CN114496788A - P-type channel gallium nitride transistor and preparation method thereof - Google Patents

Abstract

The invention relates to a P-type channel gallium nitride transistor and a preparation method thereof, wherein the preparation method comprises the following steps: step 1: obtaining a wafer with a P-type channel gallium nitride structure; step 2: epitaxially growing heavy growth layers on two sides of the surface of the wafer, wherein the heavy growth layers are heavily doped group III nitride, and a gap is formed between the two heavy growth layers; and step 3: depositing ohmic metal on the surface of the regrowth layer to form a source ohmic contact and a drain ohmic contact; and 4, step 4: depositing a gate dielectric layer on the surface of the wafer which is not covered by the regrown layer and the surface of part of the regrown layer; and 5: and depositing gate metal on the surface of the gate dielectric layer to form a gate electrode. According to the preparation method, the heavily doped P-type channel layer is directly extended on the lightly doped P-type channel layer, so that the high interface state density caused by etching the P-type channel layer under the gate is avoided, the mobility and transconductance of the transistor are improved, the leakage current is reduced, and the problems of unstable threshold voltage, low reliability and the like of the transistor are solved.

Description

A kind of P-channel gallium nitride transistor and preparation method thereof

technical field

The invention belongs to the technical field of semiconductor devices, and in particular relates to a P-channel gallium nitride transistor and a preparation method thereof.

Background technique

Gallium nitride materials have excellent properties such as wide band gap, high critical breakdown field strength, relatively high mobility, high electron saturation velocity, and relatively large spontaneous polarization coefficient. Power electronic diodes and transistors based on gallium nitride materials It has the advantages of small on-resistance, high efficiency, short reverse recovery time, high temperature resistance, and radiation resistance. very big potential.

At present, the power electronic transistors of gallium nitride mostly adopt the heterojunction lateral structure with high electron mobility. In order to realize the enhancement mode operation, a P-type GaN cap layer will be added on the upper surface of the conventional barrier layer/channel layer structure to realize the depletion of the two-dimensional electron gas of the channel. The gate voltage bias is When zero or floating, the device channel is off. The p-type gallium nitride cap layer can be used to prepare a p-channel gallium nitride transistor, so that it can be combined with a high electron mobility heterojunction structure with an n-type two-dimensional electron gas to achieve high electron mobility with gallium nitride. Mobility Power Electronics Compatible Gallium Nitride Complementary Field Effect Transistor Inverter.

The conventional P-channel GaN transistor is fabricated by a method based on gate groove etching, that is, firstly, a gallium nitride high electron having a p-type gallium nitride cap layer of about 80 nm is prepared Mobility power electronic transistor wafer, etched in the gate area, partially removed the P-type GaN cap layer, leaving a P-type GaN channel layer of about 15nm, other than the original P-type GaN cap layer area to prepare ohmic contact electrodes.

However, the above preparation method will cause etching damage to the upper surface of the P-type GaN channel in the gate region, thereby introducing additional interface states, reducing the mobility of the P-type GaN channel, thereby reducing the P-type GaN channel. The current of the GaN channel transistor affects the stability and reliability of the current of the P-type GaN channel transistor. In addition, the uniformity and batch repeatability of the etching process on large wafers are also difficult to control.

SUMMARY OF THE INVENTION

In order to solve the above problems existing in the prior art, the present invention provides a P-channel gallium nitride transistor and a preparation method thereof. The technical problem to be solved by the present invention is realized by the following technical solutions:

The invention provides a preparation method of a P-channel gallium nitride transistor, comprising:

Step 1: Obtain a wafer with a P-channel GaN structure;

Step 2: epitaxially growing regrowth layers on both sides of the wafer surface, the regrowth layers are heavily doped Group III nitrides, and there is a gap between the two regrowth layers;

Step 3: depositing ohmic metal on the surface of the regrown layer to form source ohmic contact and drain ohmic contact;

Step 4: depositing a gate dielectric layer on the surface of the wafer not covered by the re-growth layer and on the surface of part of the re-growth layer;

Step 5: depositing gate metal on the surface of the gate dielectric layer to form a gate electrode.

In one embodiment of the present invention, the wafer includes a substrate, a nucleation layer, a buffer layer, an n-type channel layer, a barrier layer, and a P-type channel layer that are sequentially stacked from bottom to top.

In an embodiment of the present invention, the step 2 includes:

Step 2.1: depositing a protective dielectric layer on the surface of the wafer;

Step 2.2: using a photolithography process to etch both sides of the protective medium layer to remove the protective medium layer on both sides of the wafer surface;

Step 2.3: epitaxially growing a regrowth layer on the part of the wafer surface that is not covered by the protective medium layer;

Step 2.4: Use BOE to peel off the protective medium layer.

In an embodiment of the present invention, the material of the regrown layer is gallium nitride or indium gallium nitride, the doping impurity is Mg or Zn, and the doping concentration is 1.0×10 ¹⁸ -1.0×10 ²⁰ cm ^-3 , Its thickness is 5-200 nm.

In an embodiment of the present invention, the material of the gate dielectric layer is aluminum oxide, silicon oxide, silicon nitride, aluminum nitride, hafnium oxide or zirconium oxide, and the thickness thereof is 5-100 nm.

In an embodiment of the present invention, the material of the n-type channel layer is unintentionally doped gallium nitride, and its thickness is 50-500 nm;

The material of the barrier layer is aluminum gallium nitride, indium aluminum nitride or aluminum nitride, and its thickness is 5-20 nm;

The material of the P-type channel layer is gallium nitride or indium gallium nitride, the doping impurity is Mg or Zn, the doping concentration is 1.0×10 ¹⁸ -1.0×10 ²⁰ cm ^-3 , and the thickness is 5-30 nm.

In an embodiment of the present invention, the material of the protective medium layer is silicon oxide or silicon nitride, and the thickness thereof is 100-1000 nm.

The present invention provides a P-channel gallium nitride transistor, which is prepared by using any one of the methods described in the foregoing embodiments. The P-channel gallium nitride transistor includes:

The substrate, the nucleation layer, the buffer layer, the n-type channel layer, the barrier layer and the P-type channel layer are stacked sequentially from bottom to top;

a regrown layer, located on both sides of the surface of the P-type channel layer, the regrown layer is heavily doped Group III nitride, and there is a gap between the two regrown layers;

a source electrode and a drain electrode, disposed on the regrowth layer;

a gate dielectric layer, disposed on the surface of the P-type channel layer and part of the surface of the regrowth layer that is not covered by the regrowth layer;

A gate electrode is disposed on the gate dielectric layer.

Compared with the prior art, the beneficial effects of the present invention are:

1. The preparation method of the P-channel gallium nitride transistor of the present invention directly epitaxy a layer of the heavily-doped P-channel layer on the lightly-doped P-channel layer, avoiding the etching of the P-channel under the gate. The high interface state density brought by the layer improves transistor mobility and transconductance, reduces leakage current, and solves problems such as threshold voltage instability and low reliability;

2. The preparation method of the p-channel gallium nitride transistor of the present invention is compatible with the conventional process of the existing p-type cap layer gallium nitride high electron mobility power electronic transistor, and has a simple manufacturing process and low cost.

The above description is only an overview of the technical solution of the present invention, in order to be able to understand the technical means of the present invention more clearly, it can be implemented according to the content of the description, and in order to make the above and other objects, features and advantages of the present invention more obvious and easy to understand , the following specific preferred embodiments, and in conjunction with the accompanying drawings, are described in detail as follows.

Description of drawings

1 is a schematic diagram of a method for preparing a P-channel gallium nitride transistor according to an embodiment of the present invention;

2a-2g are a flow chart of a preparation process of a P-channel gallium nitride transistor provided by an embodiment of the present invention;

3 is a schematic structural diagram of a P-channel gallium nitride transistor provided by an embodiment of the present invention;

Detailed ways

In order to further illustrate the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, a P-channel gallium nitride transistor and its preparation method according to the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. .

The foregoing and other technical contents, features and effects of the present invention can be clearly presented in the following detailed description of the specific implementation with the accompanying drawings. Through the description of the specific embodiments, the technical means and effects adopted by the present invention to achieve the predetermined purpose can be more deeply and specifically understood. However, the accompanying drawings are only for reference and description, not for the technical analysis of the present invention. program is restricted.

Example 1

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a preparation method of a P-channel gallium nitride transistor provided by an embodiment of the present invention. As shown in the figure, the preparation method of the P-channel gallium nitride transistor of this embodiment, include:

Step 1: Obtain a wafer with a P-channel GaN structure;

In this embodiment, the wafer includes a substrate, a nucleation layer, a buffer layer, an n-type channel layer, a barrier layer, and a P-type channel layer sequentially stacked from bottom to top.

Optionally, the material of the substrate is silicon, sapphire, silicon carbide or aluminum nitride.

Optionally, the material of the nucleation layer is aluminum nitride, and its thickness is 50-200 nm.

Optionally, the material of the buffer layer is highly insulating gallium nitride, and its thickness is 0.5-20 μm.

Optionally, the material of the n-type channel layer is unintentionally doped gallium nitride, and its thickness is 50-500 nm.

Optionally, the material of the barrier layer is aluminum gallium nitride, indium aluminum nitride or aluminum nitride, and its thickness is 5-20 nm.

Optionally, the material of the P-type channel layer is gallium nitride or indium gallium nitride, the doping impurity is Mg or Zn, the doping concentration is 1.0×10 ¹⁸ -1.0×10 ²⁰ cm ^-3 , and its thickness is 5- 30nm.

Step 2: epitaxially growing regrowth layers on both sides of the wafer surface, the regrowth layers are heavily doped Group III nitrides, and there is a gap between the two regrowth layers;

Specifically, step 2 includes:

Step 2.1: deposit a protective dielectric layer on the wafer surface;

In this embodiment, the material of the protective medium layer is silicon oxide or silicon nitride, and the thickness thereof is 100-1000 nm.

Optionally, a PECVD, LPCVD, ICPCVD or APCVD process is used to deposit a protective dielectric layer on the surface of the P-type channel layer.

Step 2.2: using a photolithography process, etching both sides of the protective medium layer to remove the protective medium layer on both sides of the wafer surface;

Specifically, spin-coating photoresist on the surface of the protective medium layer, use a photolithography machine to expose and develop the etched area, then etch the medium layer, remove the protective medium layer on both sides of the surface of the P-type channel layer, and then Remove photoresist.

Step 2.3: epitaxially grow the regrowth layer on the part of the wafer surface that is not covered by the protective dielectric layer;

In this embodiment, the material of the regrown layer is gallium nitride or indium gallium nitride, the doping impurity is Mg or Zn, the doping concentration is 1.0×10 ¹⁸ -1.0×10 ²⁰ cm ^-3 , and its thickness is 5- 200nm.

It should be noted that the material of the regrowth layer and the material of the P-type channel layer may be different, and the doping impurities thereof must be kept the same. The heavy growth layer is heavily doped to form an ohmic contact, and the channel layer is lightly doped to form a 2DHG channel. Preferably, the material of the regrowth layer is the same as the material of the P-type channel layer. In this embodiment, the material of the regrowth layer and the material of the P-type channel layer are both P-type gallium nitride, and the doping impurity is Mg.

Step 2.4: Use BOE to peel off the protective medium layer.

Step 3: depositing ohmic metal on the surface of the regrown layer to form source ohmic contact and drain ohmic contact;

In this embodiment, the metal material of the source ohmic contact and the drain ohmic contact is Ni/Au laminated metal, wherein the thickness of Ni is 5-30 nm, and the thickness of Au is 5-30 nm.

Specifically, step 3 includes:

Spin-coat photoresist on the surface of the regrown layer and P-channel layer, use a photolithography machine to expose and develop the ohmic contact area, use electron beam evaporation to deposit Ni/Au stacked metal on the surface of the regrown layer, and then remove the photoresist The resist is finally annealed to form a source ohmic contact and a drain ohmic contact on the surface of the regrown layer.

Step 4: depositing a gate dielectric layer on the surface of the wafer not covered by the regrowth layer and on the surface of part of the regrowth layer;

In this embodiment, the material of the gate dielectric layer is aluminum oxide, silicon oxide, silicon nitride, aluminum nitride, hafnium oxide or zirconium oxide, and the thickness thereof is 5-100 nm.

Optionally, an aluminum oxide gate dielectric is deposited on the surface of the P-type channel layer and part of the regrown layer by atomic layer deposition (ALD).

Step 5: depositing gate metal on the surface of the gate dielectric layer to form a gate electrode.

In this embodiment, the gate metal material is Ti/Au stacked metal, and the thickness is 20-500 nm.

Specifically, step 5 includes:

Spin-coat photoresist on the surface of the device, use a photolithography machine to expose and develop the deposited gate metal area, and deposit Ti/Au stacked metal on the surface of the gate dielectric layer to form a gate electrode.

In the preparation method of the P-channel gallium nitride transistor in this embodiment, a layer of heavily doped P-type channel layer is directly epitaxial on the lightly-doped P-type channel layer, so as to avoid etching the P-type channel layer under the gate The resulting high interface state density improves transistor mobility and transconductance, reduces leakage current, and solves problems such as threshold voltage instability and low reliability.

Embodiment 2

In this embodiment, the preparation method of the P-channel gallium nitride transistor of the first embodiment is specifically described by taking gallium nitride doped with impurity Mg as an example as the regrown layer. Referring to FIGS. 2a-2g, FIGS. 2a-2g are flowcharts of a fabrication process of a P-channel gallium nitride transistor provided by an embodiment of the present invention. As shown in the figure, the specific preparation steps include:

Step 1: epitaxially grow an AlN nucleation layer 201, a GaN buffer layer 202, a GaN channel layer 203, an Al _0.15 Ga _0.85 N barrier layer 204 and a P-type GaN channel layer 205 sequentially on the Si substrate 200, as shown in FIG. 2a shown.

In this embodiment, the thickness of the AlN nucleation layer 201 is 0.8 nm, the thickness of the GaN buffer layer 202 is 4 μm, the thickness of the GaN channel layer 203 is 300 nm, and the thickness of the Al _0.15 Ga _0.85 N barrier layer 204 is 15 nm. , the thickness of the P-type GaN channel layer 205 is 15 nm, the doping impurity is Mg, and the doping concentration is 1.0×10 ¹⁹ cm ⁻³ .

Step 2: Using PECVD to epitaxially grow a SiO ₂ dielectric layer 1a on the surface of the P-type GaN channel layer 205 with a thickness of 100 nm, as shown in FIG. 2b.

Step 3: Spin-coat photoresist on the surface of the SiO ₂ dielectric layer 1a, use a photolithography machine to expose and develop the etched area, and etch the SiO ₂ dielectric layer 1a to remove two surfaces on the surface of the P-type GaN channel layer 205. side of the _SiO2 dielectric layer 1a, and then remove the photoresist as shown in Figure 2c.

Step 4: A P-type gallium nitride regrowth layer 206 is epitaxially grown on the part of the P-type GaN channel layer 205 that is not covered by the SiO ₂ dielectric layer 1a, as shown in FIG. 2d.

In this embodiment, the doping impurity of the regenerated layer is Mg, the doping concentration is 3.0×10 ¹⁹ cm ^-3 , and the thickness is 40 nm.

Step 5: The _SiO2 dielectric layer 1a is peeled off with BOE, as shown in Figure 2e.

Step 6: Spin-coat photoresist on the surface of the P-type gallium nitride regrowth layer 206 and the P-type GaN channel layer 205, use a photolithography machine to expose and develop the ohmic contact area, and use electron beam evaporation on the P-type nitride layer. Ni/Au laminated metal is deposited on the surface of the gallium regrowth layer 206 .

In this embodiment, the thickness of Ni/Au is 15/20 nm;

Step 7: After removing the photoresist, the device is annealed to form a source ohmic contact 207 and a drain ohmic contact 208 on the surface of the P-type gallium nitride regrown layer 206, as shown in FIG. 2f.

In this embodiment, the annealing temperature is 550° C., the annealing time is 5 mins, and the annealing atmosphere is an oxygen atmosphere to form an ohmic contact.

Step 8: Atomic layer deposition (ALD) is used to deposit an aluminum oxide gate dielectric layer 209 on the surface of the P-type GaN channel layer 205 and part of the surface of the P-type gallium nitride regrown layer 206 .

In this embodiment, the thickness of the aluminum oxide gate dielectric layer 209 is 30 nm.

Step 9: Spin-coat photoresist on the surface of the device, use a photolithography machine to expose and develop the deposited gate metal area, and deposit Ti/Au stacked metal on the surface of the gate dielectric layer 209 to form a gate electrode 210, as shown in Figure 2g shown.

In this embodiment, the thickness of Ti/Au is 20/150 nm.

The preparation method of the P-channel gallium nitride transistor of this embodiment is compatible with the conventional process of the existing P-type cap layer gallium nitride high electron mobility power electronic transistor, and the manufacturing process is simple and the cost is low.

Embodiment 3

This embodiment provides a P-channel gallium nitride transistor, which is prepared by the method described in the embodiment. Please refer to FIG. 3 . FIG. 3 is a P-channel nitride transistor provided by the embodiment of the present invention. A schematic diagram of the structure of a gallium transistor, as shown in the figure, the p-channel gallium nitride transistor includes: a substrate 300, a nucleation layer 301, a buffer layer 302, an n-channel layer 303, a potential layer 300 stacked in sequence from bottom to top Barrier layer 304 and P-type channel layer 305; re-growth layers 306 are provided on both sides of the surface of P-type channel layer 305, and the re-growth layers 306 are heavily doped group III nitrides, and there is a gap between the two re-growth layers 306 spacer; the source electrode 307 and the drain electrode 308 are arranged on the regrown layer 306; a gate dielectric layer 309 is arranged on the surface of the P-type channel layer 305 and part of the regrown layer 306 not covered by the regrown layer 306; the gate dielectric A gate electrode 310 is provided on layer 309 .

For the P-channel GaN transistor of this embodiment, during the preparation process, a layer of heavily doped P-channel layer is directly epitaxial on the lightly-doped P-type channel layer, so as to avoid etching the P-type channel under the gate. The high interface state density brought by the channel layer improves transistor mobility and transconductance, reduces leakage current, and solves the problems of unstable threshold voltage and low reliability of P-channel GaN transistors.

It should be noted that, herein, the terms "comprising", "comprising" or any other variation are intended to encompass a non-exclusive inclusion such that an article or device comprising a list of elements includes not only those elements, but also a non-exclusive inclusion other elements listed. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in the article or device that includes the element. The orientation or positional relationship indicated by "up", "bottom", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying The device or element referred to must have a particular orientation, be constructed and operate in a particular orientation, and therefore should not be construed as limiting the invention.

The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be considered that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deductions or substitutions can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (8)

1. a preparation method of a P-type channel gallium nitride transistor, is characterized in that, comprises: Step 1: Obtain a wafer with a P-channel GaN structure; Step 2: epitaxially growing regrowth layers on both sides of the wafer surface, the regrowth layers are heavily doped Group III nitrides, and there is a gap between the two regrowth layers; Step 3: depositing ohmic metal on the surface of the regrown layer to form source ohmic contact and drain ohmic contact; Step 4: depositing a gate dielectric layer on the surface of the wafer not covered by the re-growth layer and on the surface of part of the re-growth layer; Step 5: depositing gate metal on the surface of the gate dielectric layer to form a gate electrode. 2 . The method for preparing a p-channel gallium nitride transistor according to claim 1 , wherein the wafer comprises a substrate, a nucleation layer, a buffer layer and an n-type channel stacked in sequence from bottom to top. 3 . channel layer, barrier layer and P-type channel layer. 3. The method for preparing a P-channel gallium nitride transistor according to claim 1, wherein the step 2 comprises: Step 2.1: depositing a protective dielectric layer on the surface of the wafer; Step 2.2: using a photolithography process to etch both sides of the protective medium layer to remove the protective medium layer on both sides of the wafer surface; Step 2.3: epitaxially growing a regrowth layer on the part of the wafer surface that is not covered by the protective medium layer; Step 2.4: Use BOE to peel off the protective medium layer. 4 . The method for preparing a P-channel gallium nitride transistor according to claim 1 , wherein the material of the regrown layer is gallium nitride or indium gallium nitride, the doping impurity is Mg or Zn, and the doping impurity is Mg or Zn. The impurity concentration is 1.0×10 ¹⁸ -1.0×10 ²⁰ cm ^-3 , and its thickness is 5-200 nm. 5 . The method for preparing a P-channel gallium nitride transistor according to claim 1 , wherein the gate dielectric layer is made of aluminum oxide, silicon oxide, silicon nitride, aluminum nitride, hafnium oxide or Zirconia with a thickness of 5-100nm. 6. The method for preparing a p-channel gallium nitride transistor according to claim 2, wherein the material of the n-type channel layer is unintentionally doped gallium nitride, and its thickness is 50-500 nm; The material of the barrier layer is aluminum gallium nitride, indium aluminum nitride or aluminum nitride, and its thickness is 5-20 nm; The material of the P-type channel layer is gallium nitride or indium gallium nitride, the doping impurity is Mg or Zn, the doping concentration is 1.0×10 ¹⁸ -1.0×10 ²⁰ cm ^-3 , and the thickness is 5-30 nm. 7 . The method for preparing a P-channel gallium nitride transistor according to claim 3 , wherein the material of the protective medium layer is silicon oxide or silicon nitride, and the thickness thereof is 100-1000 nm. 8 . 8. A P-channel gallium nitride transistor, characterized in that, prepared by the method according to any one of claims 1-7, and the P-channel gallium nitride transistor comprises: The substrate, the nucleation layer, the buffer layer, the n-type channel layer, the barrier layer and the P-type channel layer are stacked sequentially from bottom to top; a regrown layer, located on both sides of the surface of the P-type channel layer, the regrown layer is heavily doped Group III nitride, and there is a gap between the two regrown layers; a source electrode and a drain electrode, disposed on the regrowth layer; a gate dielectric layer, disposed on the surface of the P-type channel layer and part of the surface of the regrowth layer that is not covered by the regrowth layer; A gate electrode is disposed on the gate dielectric layer.

Images