CN114490208A - Test apparatus, method, computer equipment, storage medium and program product - Google Patents

Abstract

The present application relates to a test apparatus, a method, a computer device, a storage medium and a program product. The testing device comprises a testing main board and a short circuit board. The test mainboard is connected with the adapter card to be tested, and the adapter card to be tested is connected with the short circuit board. The test mainboard outputs a test signal to the adapter card to be tested so that the test signal reaches the short circuit board through the adapter card to be tested; the short circuit board outputs a backflow signal according to an output signal of the adapter card to be tested so that the backflow signal reaches the test main board after passing through the adapter card to be tested; and the test mainboard performs signal analysis according to the backflow signal output by the short circuit board to obtain a performance test result of the adapter card to be tested. In this scheme, form signal loop through the short circuit board among the testing arrangement, whether the test mainboard among the testing arrangement can be based on the route of backward flow signal location switching card that awaits measuring and have a problem, can realize the synchronous test of a plurality of switching cards that await measuring through the short circuit board, reduce the loss to server mainboard slot groove, the life-span of extension server mainboard.

Description

Test apparatus, method, computer equipment, storage medium and program product

technical field

The present application relates to the field of computer technology, and in particular, to a testing apparatus, method, computer equipment, storage medium and program product.

Background technique

With the gradual improvement of server application and performance, it is often necessary to introduce a function expansion card or adapter card (PCI-E riser card) inserted on the PCI-E interface to expand or transfer the PCI-E interface of the motherboard. When the path of the PCI-E riser card in the server is disconnected, the performance of the server during actual operation may be affected, and it may even cause serious damage to the system hardware of the server. Therefore, the path connectivity detection of the PCIe riser standard card is very important.

The current detection method for the PCI-E riser card includes installing the PCIe riser card on the server for on-board debugging, that is, installing the PCI-E riser card into the matching server motherboard, and inserting the corresponding Standard card, verify the performance of the standard card inserted on the PCI-E riser card through functional verification and script testing under the server operating system, so as to judge the performance of the PCI-E riser card.

The above method for judging the performance of the PCI-E riser card, in the scenario of testing the performance of multiple PCI-E riser cards, will cause a large consumption of the slot slot of the server motherboard and affect the life of the slot slot of the server motherboard.

SUMMARY OF THE INVENTION

Based on this, it is necessary to provide a test device, method, computer equipment, storage medium and program product that can improve the accuracy of the detection result of the performance of the PCI-E riser card in view of the above technical problems.

In a first aspect, the present application provides a test device, the test device includes: a test main board and a short circuit board; the test main board is connected to an adapter card to be tested, and the adapter card to be tested is connected to the short circuit board;

The test motherboard is used to output the test signal to the adapter card to be tested, so that the test signal can reach the short circuit board through the adapter card to be tested;

The short-circuit board is used to output the return signal according to the output signal of the riser card to be tested, so that the return signal reaches the test motherboard after passing through the riser card to be tested;

The mainboard is tested, and is also used for signal analysis according to the backflow signal output by the short-circuit board to obtain the performance test result of the adapter card to be tested.

In this solution, a signal loop is formed by the short circuit board in the test device, and the test motherboard in the test device can locate whether there is a problem with the passage of the adapter card to be tested according to the return signal, and does not depend on the server and is used for indirect testing The test standard card of the test adapter card can be tested directly through the short circuit board and the test motherboard, and the synchronous performance test of multiple adapter cards to be tested can also be realized through the short circuit board, without the need to perform multiple tests on the server motherboard. Plug to test the performance of the riser card to be tested, which reduces the mechanical complexity of the tooling, reduces the loss of the slot slot of the server motherboard, prolongs the life of the server motherboard, and reduces cost consumption.

In one optional embodiment, the test motherboard includes a first processor;

a first processor for outputting a first test signal, so that the first test signal reaches the short-circuit board through the adapter card to be tested;

a short circuit board, used for outputting the first return signal according to the first output signal of the riser card to be tested, so that the first return flow signal reaches the test motherboard through the riser card to be tested;

The first processor is further configured to perform signal analysis according to the first return signal to obtain a performance test result of the channel between the transmitting end and the receiving end of the adapter card to be tested.

In this embodiment, a short-circuit loop between the transmitting end and the receiving end of the adapter card to be tested is formed by the short circuit board, which can effectively avoid adding test tools such as cables, and can realize the simultaneous detection of multiple adapter cards to be tested. Improve the performance testing efficiency of multiple riser cards to be tested.

In one of the optional embodiments, the output end of the first processor is connected to the transmitting end of the adapter card to be tested, and the receiving end of the adapter card to be tested is connected to the input end of the first processor;

The transmitting end of the short circuit board is connected with the transmitting end of the adapter card to be tested, and the receiving end of the short circuit board is connected with the receiving end of the adapter card to be tested.

In this embodiment, a short-circuit loop between the transmitting end and the receiving end of the adapter card to be tested is formed by the short circuit board, which can effectively avoid adding test tools such as cables, and can realize the simultaneous detection of multiple adapter cards to be tested. Improve the performance testing efficiency of multiple riser cards to be tested.

In one optional embodiment, the test motherboard further includes a second processor;

The second processor is used for outputting the second test signal, so that the second test signal reaches the short-circuit board through the adapter card to be tested;

a short circuit board, used for outputting a second return flow signal according to the second output signal of the riser card to be tested, so that the second return flow signal reaches the first processor through the riser card to be measured;

The first processor is further configured to perform signal analysis on the second return flow signal to obtain a performance test result of the IIC path of the riser card to be tested.

In this embodiment, the short circuit of the IIC path in the adapter card to be tested is formed by the short circuit board, which can effectively avoid adding testing tools such as cables, and accurately and conveniently realize the location detection of the IIC path of the adapter card to be tested.

In one optional embodiment, the output end of the second processor is connected to the IIC pin of the riser card to be tested; the 100M signal pin of the riser card to be tested is connected to the input end of the first processor, The IIC pin and 100M signal pin of the adapter card to be tested are connected to the short circuit board; the IIC pin of the short circuit board is connected to the IIC pin of the adapter card to be tested, and the 100M signal pin of the short circuit board is connected to the The 100M signal pin connection of the riser card.

In this embodiment, the short circuit of the IIC path in the adapter card to be tested is formed by the short circuit board, which can effectively avoid adding testing tools such as cables, and accurately and conveniently realize the location detection of the IIC path of the adapter card to be tested.

In one optional embodiment, the test motherboard further includes an IIC expansion component; the input end of the IIC expansion component is connected to the output end of the second processor, and the output end of the IIC expansion component is connected to the IIC pin of the riser card to be tested connect;

The second processor is used for outputting the second test signal, so that the second test signal reaches the short-circuit board through the IIC expansion component and the IIC pin of the riser card to be tested.

In this embodiment, by adding an IIC extension component, the IIC address conflict is avoided as much as possible in a scenario where multiple PCI-E riser cards are detected at the same time.

In one optional embodiment, the test motherboard further includes a power supply;

The power supply is used to output the third test signal, so that the third test signal can reach the short-circuit board through the voltage pin of the adapter card to be tested;

a short circuit board, used for outputting a third return flow signal according to the third output signal of the voltage pin of the riser card to be tested, so that the third return flow signal reaches the second processor through the wake-up pin of the riser card to be measured;

The second processor is further configured to output the third return flow signal to the first processor;

The first processor is further configured to perform signal analysis on the third return flow signal to obtain a performance test result of the power supply path of the adapter card to be tested.

In this embodiment, the voltage pin and the wake-up pin of the PCI-E riser card are shorted together to form a loop, and the third test signal sent by the power supply of the test mainboard will all be returned to the CPLD of the test mainboard. It can effectively avoid adding test tools such as cables, and can locate whether the power supply path of the PCI-E riser card is abnormal.

In one optional embodiment, the short-circuit board includes a voltage pin and a wake-up pin; the short-circuited voltage pin is connected to the voltage pin of the riser card to be tested; the wake-up pin of the short-circuit board is connected to the riser card to be tested the wake-up pin connection.

In this embodiment, the voltage pin and the wake-up pin of the PCI-E riser card are shorted together to form a loop, and the third test signal sent by the power supply of the test mainboard will all be returned to the CPLD of the test mainboard. It can effectively avoid adding test tools such as cables, and can locate whether the power supply path of the PCI-E riser card is abnormal.

In one optional embodiment, the test motherboard further includes at least one of a buzzer, a digital tube, and an LED connected to the first processor;

The first processor is further configured to output abnormal performance information through at least one of a buzzer, a digital tube, and an LED when it is determined that the performance of the riser card to be tested is abnormal.

In this embodiment, the abnormal path information of the PCI-E riser card can be output through devices such as a buzzer, a digital tube, and an LED, which can effectively locate the abnormal path and improve the detection efficiency of the PCI-E riser card.

In a second aspect, a test method is provided, applied in the test device provided in any one of the first aspects, the method comprising:

Output the test signal to the adapter card to be tested through the test motherboard of the test device, so that the test signal reaches the short circuit board of the test device through the adapter card to be tested;

Output the return signal through the short-circuit board according to the output signal of the riser card to be tested, so that the return signal reaches the test motherboard after passing through the riser card to be tested;

The performance test result of the adapter card to be tested is obtained by analyzing the signal according to the backflow signal output by the short circuit board by the test motherboard.

In this embodiment, a signal loop is formed by the short circuit board in the test device, and the test motherboard in the test device can locate whether there is a problem with the passage of the riser card to be tested according to the return signal, and does not depend on the server and is used for indirect testing. The test standard card of the riser card to be tested can be directly tested through the short circuit board and the test motherboard. The direct test method improves the accuracy of the path test results of the riser card to be tested, and at the same time reduces the mechanical complexity of the tooling It also reduces the loss of the server motherboard and reduces the cost consumption.

In a third aspect, the present application also provides a computer device. The computer device includes a memory and a processor, the memory stores a computer program, and the processor implements the method provided in the second aspect when the processor executes the computer program.

In a fourth aspect, the present application also provides a computer-readable storage medium. The computer-readable storage medium has a computer program stored thereon, and when the computer program is executed by a processor, implements the method provided in the second aspect.

In a fifth aspect, the present application also provides a computer program product. The computer program product includes a computer program, which implements the method provided in the second aspect when the computer program is executed by a processor.

The above-mentioned test apparatus, method, computer equipment, storage medium and program product, the test apparatus includes a test motherboard and a short circuit. Wherein, the test mainboard is connected with the riser card to be tested, and the riser card to be tested is connected with the short circuit board. The test motherboard outputs the test signal to the adapter card to be tested, so that the test signal reaches the short circuit board through the adapter card to be tested; the short circuit board outputs the return signal according to the output signal of the adapter card to be tested, so that the return signal passes through the adapter to be tested. After the card reaches the test motherboard; the test motherboard performs signal analysis according to the return signal output by the short-circuit board, and obtains the performance test result of the adapter card to be tested. In this solution, a signal loop is formed by the short circuit board in the test device, and the test motherboard in the test device can locate whether there is a problem with the passage of the adapter card to be tested according to the backflow signal, and the short circuit board can also realize multiple The synchronization performance test of the riser card does not require multiple insertions of the server motherboard to test the performance of the riser card to be tested, which reduces the mechanical complexity of the tooling, reduces the loss of the slot slot of the server motherboard, and prolongs the server The lifespan of the motherboard reduces the cost consumption.

Description of drawings

1 is a schematic diagram of an environment for testing a riser card in the prior art in one embodiment;

2 is a schematic structural diagram of a testing device in one embodiment;

3 is a schematic structural diagram of a testing device including a first processor in another embodiment;

4 is a schematic structural diagram of a testing device including a first processor in another embodiment;

5 is a schematic structural diagram of a test device including a clock buffer in another embodiment;

6 is a schematic structural diagram of a test device including a door module in another embodiment;

7 is a schematic structural diagram of a test apparatus including a second processor in another embodiment;

8 is a schematic structural diagram of a test apparatus including a second processor in another embodiment;

9 is a schematic structural diagram of a test device including an IIC extension component in another embodiment;

10 is a schematic structural diagram of a test device including a sensor in another embodiment;

11 is a schematic structural diagram of a test device including a power supply in another embodiment;

12 is a schematic structural diagram of a test device including a power supply in another embodiment;

13 is a schematic structural diagram of a test device including LEDs in a power supply in another embodiment;

14 is a schematic structural diagram of a test device including a buzzer, an LED, and a digital tube in another embodiment;

15 is a schematic flowchart of a testing method in one embodiment;

Figure 16 is a diagram of the internal structure of a computer device in one embodiment.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present application more clearly understood, the present application will be described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application.

With the gradual improvement of server applications and performance, it is often necessary to introduce PCI-E riser cards to expand or transfer the PCI-E interface of the motherboard. Usually, each server has multiple PCI-E riser cards to achieve Functional expansion or performance improvement.

At present, these PCI-E riser cards lack corresponding detection methods, and it is difficult to determine the channel connectivity of the PCI-ERiser cards before the actual installation. When part of the path of the PCI-E riser card used in the server installation is disconnected, the performance of the server during actual operation may be degraded, or even serious damage to the system hardware may be caused.

The current hardware path detection solution for PCI-E riser cards is to perform board debugging by installing the PCI-E riser card on the server device, that is, install the PCI-E riser card on the matching server motherboard, and install the PCI-E riser card on the PCI-E riser card. Insert the corresponding test standard card on the PCI-E Riser card, and verify the performance of the test standard card inserted on the PCI-ERiser card through the function verification and script test under the system, so as to indirectly judge the function of the PCI-E Riser card, such as As shown in FIG. 1, FIG. 1 includes the connection relationship between the PCI-E riser card, the test standard card and the server motherboard.

However, the operation of the above solution is cumbersome, and it requires supporting test equipment and cables for testing, or building a complete server for testing; and, during verification, it is necessary to check the test standard card equipment inserted on the PCI-E riser card under the system; or Verify the performance of the test standard card through test scripts and other methods, so as to indirectly judge whether the path of the PCI-E riser card is normal, which not only wastes time, but also may lead to the missed detection of some IO functions; During the verification test, the PCI-E golden finger of the server will be repeatedly inserted and removed, which will reduce the service life of the corresponding server PCI-E slot and affect the quality of the server.

The present application provides a test device, as shown in FIG. 2 , the test device includes: a test main board and a short circuit board; wherein, the test main board is connected to an adapter card to be tested, and the adapter card to be tested is connected to the short circuit board.

The test motherboard is used to output the test signal to the adapter card to be tested, so that the test signal can reach the short circuit board through the adapter card to be tested;

The short-circuit board is used to output the return signal according to the output signal of the riser card to be tested, so that the return signal reaches the test motherboard after passing through the riser card to be tested;

The mainboard is tested, and is also used for signal analysis according to the backflow signal output by the short-circuit board to obtain the performance test result of the adapter card to be tested.

Optionally, the test mainboard can be a substrate including a processor and a power supply. Exemplarily, the processor can be a field programmable gate array (Field Programmable Gate Array, FPGA), a programmable logic device (Programmable Logic Device, PLD) , a complex programmable logic device (Complex Programmable Logic Device, CPLD), a Microcontroller Unit (Microcontroller Unit, MCU) and one or more processors are combined.

Optionally, the riser card may be a riser card of a PCI-E interface in a server, for example, a PCI-E riser standard card; or a riser card of other signal interfaces in the server.

Optionally, the short circuit board is used to connect with the adapter card to be tested and the test motherboard to form a short circuit signal path. Based on the characteristics of the short circuit board, the settings of the short circuit board can be consistent with the settings of the adapter card to be tested.

In this embodiment, the short-circuit board is connected to the adapter card to be tested, the adapter card to be tested is inserted into the slot of the card slot of the test motherboard, the test motherboard is controlled to be powered on, and after a period of time, the transfer to be tested starts. Card test. The period of time here can be 10 seconds, 20 seconds, etc.

Exemplarily, the test motherboard in the test device outputs a test signal to the riser card to be tested, where the test signal can be determined according to the path tested by the riser card to be tested. Exemplarily, if the power supply path of the riser card to be tested is detected , the test signal output by the test motherboard can be understood as a voltage value; if the IIC path of the adapter card to be tested is detected, the test signal output by the test motherboard can be the IIC address information; if other paths of the adapter card to be tested are detected, then The test board can output pulse modulated signals. In this embodiment, the signal output by the test motherboard is determined based on the path included in the riser card to be tested.

The test signal is output from the test motherboard, and is output to the short circuit board through the adapter card to be tested. The short circuit board outputs the return signal according to the signal output by the adapter card to be tested. It should be noted that when the circuit of the adapter card to be tested is normal , the output signal of the adapter card to be tested is the test signal; if the circuit of the adapter card to be tested fails, the output signal of the adapter card to be tested may be other signals. The short-circuit board outputs a return signal to the riser card to be tested according to the output signal of the riser card to be tested. The return signal passes through the riser card to be tested, and the test motherboard obtains the return signal for signal analysis. Similarly, the return signal passes through the switch to be tested. Card, when the circuit of the adapter card to be tested is normal, the return signal received by the test motherboard and passed through the adapter card to be tested is the return signal; The return signal of the test adapter card may be other signals.

Optionally, the test mainboard performs signal analysis according to the received backflow signal. Optionally, the test mainboard can analyze the waveform of the backflow signal, the signal parameters of the backflow signal, or other parameters indicated by the backflow signal, such as the voltage value, etc., to determine. Check whether the path corresponding to the return signal is faulty, and obtain the performance test result of the adapter card to be tested. Optionally, in the scenario where the riser card to be tested includes multiple channels, that is, in the scenario where the test mainboard receives the backflow signals corresponding to the multiple channels, the test mainboard performs signal analysis on the backflow signals corresponding to all channels, and if there are any If the backflow signal corresponding to at least one channel is abnormal, that is, at least one channel is faulty, locate the channel and output the prompt information of the channel failure to determine that the performance of the adapter card to be tested is abnormal; if the backflow signal corresponding to all channels does not appear If it is abnormal, that is, all channels are normal, it is determined that the performance of the riser card to be tested is normal.

The above-mentioned test device includes a test mainboard and a short circuit. Wherein, the test mainboard is connected with the riser card to be tested, and the riser card to be tested is connected with the short circuit board. The test motherboard outputs the test signal to the adapter card to be tested, so that the test signal reaches the short circuit board through the adapter card to be tested; the short circuit board outputs the return signal according to the output signal of the adapter card to be tested, so that the return signal passes through the adapter to be tested. After the card reaches the test motherboard; the test motherboard performs signal analysis according to the return signal output by the short-circuit board, and obtains the performance test result of the adapter card to be tested. In this solution, a signal loop is formed by the short circuit board in the test device, and the test motherboard in the test device can locate whether there is a problem with the passage of the adapter card to be tested according to the backflow signal, and the short circuit board can also realize multiple The synchronization performance test of the riser card does not require multiple insertions of the server motherboard to test the performance of the riser card to be tested, which reduces the mechanical complexity of the tooling, reduces the loss of the slot slot of the server motherboard, and prolongs the server The lifespan of the motherboard reduces the cost consumption.

In one optional embodiment, as shown in FIG. 3 , the test motherboard includes a first processor.

a first processor for outputting a first test signal, so that the first test signal reaches the short-circuit board through the adapter card to be tested;

a short circuit board, used for outputting the first return signal according to the first output signal of the riser card to be tested, so that the first return flow signal reaches the test motherboard through the riser card to be tested;

The first processor is further configured to perform signal analysis according to the first return signal to obtain a performance test result of the channel between the transmitting end and the receiving end of the adapter card to be tested.

Optionally, the first processor may be any one of FPGA, PLD, CPLD, and MCU. Optionally, the first test signal output by the first processor may be pulse width modulation (Pulse Width Modulation, PWM).

The first processor is a CPLD and the adapter card to be tested is a PCI-E riser card for illustration, as shown in FIG. 3 . The CPLD outputs the first test signal, which is used to test the connectivity of the path between the transmitter and the receiver of the PCI-E riser. Exemplarily, the first test signal may be a PWM signal, the PWM signal reaches the short-circuit board through the PCI-E riser card, and the short-circuit board forms a return signal of the PWM signal according to the signal output by the PCI-E riser card, and reaches the short-circuit board through the PCI-E riser card. In the CPLD, the CPLD performs signal analysis according to the return signal of the PWM signal to determine the connectivity of the path between the transmitter and the receiver in the PCI-E riser card. Exemplarily, if the CPLD determines that the signal state of the return signal of the PWM signal is abnormal, it is determined that the path between the transmitter and the receiver in the PCI-E riser card is faulty.

Optionally, as shown in FIG. 4 , the output end of the first processor is connected to the transmitting end of the adapter card to be tested, and the receiving end of the adapter card to be tested is connected to the input end of the first processor; The terminal is connected to the transmitting terminal of the adapter card to be tested, and the receiving terminal of the short circuit board is connected to the receiving terminal of the adapter card to be tested.

The adapter card to be tested includes a transmitter port and a receiver port. Correspondingly, the short circuit board forms a short circuit with the transmitter end and the receiver end, and the transmitter end and the receiver end are also arranged in the short circuit board. The test mainboard can detect the connectivity of the path between the transmitting end and the receiving end by outputting the first test signal.

Exemplarily, the first processor is a CPLD, and the riser card to be tested is a PCI-E riser card as an example for illustration, and reference may be made to FIG. 4 . The PCI-E riser card includes transmit ports TXDP and TXDN, and receive ports RXDP and RXDN. The transmitting ports TXDP and TXDN of the PCI-ERiser card are respectively connected with the transmitting ports TXDP and TXDN of the short circuit board, and the receiving ports RXDP and RXDN of the short circuit board are respectively connected with the receiving ports RXDP and RXDN of the PCI-E riser card. The transmitting ports TXDP and TXDN of the PCI-E riser card are both connected to the output end of the CPLD; the receiving ports RXDP and RXDN of the PCI-E riser card are both connected to the input end of the CPLD.

Exemplarily, the first test signal can be a PWM signal, and the PWM signal output by the CPLD reaches the transmit ports TXDP and TXDN of the short-circuit board through the transmit ports TXDP and TXDN of the PCI-E riser card. The signal forms the return signal of the PWM signal, which is output to the receiving ports RXDP and RXDN of the PCI-E riser card through the receiving ports RXDP and RXDN of the short-circuit board, and the return signal is output to the receiving ports RXDP and RXDN of the PCI-E riser card. in CPLD. The CPLD performs signal analysis according to the return signal of the PWM signal, and determines the connectivity of the path between the transmitter TXDP and TXDN and the receiver RXDP and RXDN in the PCI-E riser card. Exemplarily, if the CPLD determines that the signal state of the return signal of the PWM signal is abnormal, it is determined that the path between the transmitting ends TXDP and TXDN and the receiving ends RXDP and RXDN in the PCI-E riser card is faulty.

Optionally, in order to realize the expansion of the first test signal, a clock buffer Buffer can also be added to the test motherboard. Exemplarily, take the first processor as a CPLD and the adapter card to be tested as a PCI-E riser card as an example. To illustrate, as shown in Figure 5, the input end of the clock buffer Buffer is connected to the output end of the CPLD, and the output end of the clock buffer Buffer is respectively connected to the transmit ports TXDP and TXDN of the PCI-E riser card to realize the output of the CPLD. Extension of the first test signal.

Optionally, in order to improve the utilization rate of the pins of the CPLD, a gate circuit can also be set in the test motherboard. Exemplarily, take the first processor as a CPLD and the adapter card to be tested as a PCI-E riser card as an example. Description, as shown in Figure 6, the input end of the gate circuit is connected to the receiving ends RXDP and RXDN of the PCI-E riser card, and the output end of the gate circuit is connected to the input end of the CPLD, so as to realize that the receiving end of the PCI-E riser card has many Integrated collection of road signals. Exemplarily, if the state of the return signal output by at least one port of the receiving end of the PCI-E riser card is abnormal, then the state of the return signal output by the gate circuit is abnormal, then it is determined that the transmitting end TXDP and TXDN in the PCI-E riser card are the same as the receiving end. There is a fault in the path between RXDP and RXDN; if the status of the return signal output by all ports on the receiving end of the PCI-ERiser card is normal, then the status of the return signal output by the gate circuit is normal, then determine the TXDP and TXDN at the transmitting end of the PCI-E riser card. The channel with the receiver RXDP and RXDN is normal.

In this embodiment, the short circuit of the path between the transmitting end and the receiving end in the adapter card to be tested is formed by the short circuit board, which can effectively avoid adding test tools such as cables. In addition, the clock buffer and the gate circuit realize the branching and integration of the test signal, improve the utilization efficiency of the pins or ports of the first processor (CPLD), and reduce the logic resource consumption of the first processor (CPLD), Therefore, the simultaneous detection of multiple riser cards to be tested can be realized, and the performance detection efficiency of the multiple riser cards to be tested can be improved.

In order to further detect other paths of the riser card to be tested, in an optional embodiment, as shown in FIG. 7 , the test motherboard further includes a second processor.

The second processor is used for outputting the second test signal, so that the second test signal reaches the short-circuit board through the adapter card to be tested;

a short circuit board, used for outputting a second return flow signal according to the second output signal of the riser card to be tested, so that the second return flow signal reaches the first processor through the riser card to be measured;

The first processor is further configured to perform signal analysis on the second return flow signal to obtain a performance test result of the IIC path of the riser card to be tested.

Optionally, the second processor may be an MCU or any other processor. Optionally, the second test signal output by the second processor may be used to directly or indirectly indicate the IIC address information.

The first processor is a CPLD, the adapter card to be tested is a PCI-E riser card, and the second processor is an MCU for illustration, as shown in FIG. 7 . The MCU can be used as the master device (master side) of the IIC, and the CPLD can be used as the slave device (slave side) of the IIC. The MCU sends different IIC address information to the PCI-E riser card to test the connectivity of the IIC path of the PCI-E riser card. . Exemplarily, different IIC address information reaches the short-circuit board through the PCI-E riser card, the short-circuit board forms corresponding return information according to the IIC address information output by the PCI-E riser card, and reaches the CPLD through the PCI-E riser card. The return information of the address information is analyzed to determine the connectivity of the IIC path in the PCI-E riser card. Exemplarily, if the CPLD determines that the return information of the IIC address information is incorrect, it is determined that the IIC path in the PCI-E riser card is faulty.

Optionally, as shown in Figure 8, the output end of the second processor is connected to the IIC pin of the adapter card to be tested; the 100M signal pin of the adapter card to be tested is connected to the input end of the first processor, The IIC pin and 100M signal pin of the adapter card to be tested are connected to the short circuit board; the IIC pin of the short circuit board is connected to the IIC pin of the adapter card to be tested, and the 100M signal pin of the short circuit board is connected to the The 100M signal pin connection of the riser card.

The adapter card to be tested includes IIC pins and 100M signal pins. Correspondingly, the short circuit board also includes IIC pins and 100M signal pins, so that the short circuit board forms a short circuit with the test motherboard and the adapter card to be tested. The loop is used to detect the connectivity of the IIC path in the riser card to be tested by outputting the second test signal.

Exemplarily, the first processor is a CPLD, the riser card to be tested is a PCI-E riser card, and the second processor is an MCU for illustration, as shown in FIG. 8 . The MCU can be used as the master device (master side) of the IIC, and the CPLD can be used as the slave device (slave side) of the IIC. The MCU sends different IIC address information to the PCI-E riser card to test the connectivity of the IIC path of the PCI-E riser card. . Exemplarily, different IIC address information reaches the short-circuit board through the IIC pin of the PCI-E riser card, and the short-circuit board forms corresponding return information according to the IIC address information output by the IIC pin of the PCI-E riser card. The mega signal pin is output to the 100M signal pin and RESERVE pin of the PCI-E riser card, so that the CPLD receives the 100M signal pin of the PCI-E riser card and the IIC address information output by the RESERVE pin, and the MCU waits for the CPLD Respond according to the received IIC address information. If the CPLD does not respond, it is determined that the IIC path in the PCI-E riser card is faulty.

Optionally, in order to further expand the IIC address information, as shown in Figure 9, the test motherboard also includes an IIC expansion assembly; the input end of the IIC expansion assembly is connected to the output end of the second processor, and the output end of the IIC expansion assembly is connected to the to-be-tested. IIC pin connection of riser card.

The second processor is used for outputting the second test signal, so that the second test signal reaches the short-circuit board through the IIC expansion component and the IIC pin of the riser card to be tested.

Exemplarily, the first processor is a CPLD, the riser card to be tested is a PCI-E riser card, the second processor is an MCU, and the IIC extension component is an IIC switch, as shown in FIG. 9 . The MCU can be used as the master device (master side) of the IIC, and the CPLD can be used as the slave device (slave side) of the IIC. The MCU outputs the IIC address information to the IIC switch. The IIC switch includes 16 address channels, which can output different extended IIC address information. , through the IIC pin of the PCI-E riser card to the short circuit board, the short circuit board forms the corresponding return information according to the IIC address information output by the IIC pin of the PCI-E riser card, and outputs to the PCI through the 100M signal pin of the short circuit board -E Riser card's 100M signal pin and RESERVE pin, so that CPLD receives the IIC address information output by PCI-E Riser's 100M signal pin and RESERVE pin, MCU waits for CPLD to receive IIC address information Respond, if the CPLD does not respond, it is determined that the IIC path in the PCI-E riser card is faulty. After obtaining the judgment result of the IIC path, the MCU can send the judgment result to the CPLD through UART, so that the CPLD can respond to each path. Summarize the judgment results of the PCI-E riser cards to obtain the detection results of the PCI-E riser card.

Optionally, at least one temperature sensor sensor can also be set in the PCI-E riser card, as shown in Figure 10. In this case, the MCU can also directly read the sensor in the PCI-E riser card through the IIC interface of Goldfinger. According to the temperature value and the preset temperature threshold, it is determined whether the sensor in the PCI-E riser card is in normal working state, so as to send the judgment result to the CPLD through UART, so that the CPLD can summarize the judgment results of each channel. Obtain the test result of the PCI-E riser card.

In this embodiment, the short circuit of the IIC path in the riser card to be tested is formed by the short circuit board, which can effectively avoid adding test tools such as cables. By adding the IIC expansion component, the IIC address conflict is avoided as much as possible in the scenario of simultaneous detection of multiple PCI-E riser cards.

In an optional embodiment, as shown in FIG. 11 , the test motherboard further includes a power supply;

The power supply is used to output the third test signal, so that the third test signal can reach the short-circuit board through the voltage pin of the adapter card to be tested;

a short circuit board, used for outputting a third return flow signal according to the third output signal of the voltage pin of the riser card to be tested, so that the third return flow signal reaches the second processor through the wake-up pin of the riser card to be measured;

The second processor is further configured to output the third return flow signal to the first processor;

The first processor is further configured to perform signal analysis on the third return flow signal to obtain a performance test result of the power supply path of the adapter card to be tested.

In this embodiment, the power supply is used to realize the power supply of the test motherboard and the detection of the power supply path of the riser card to be tested.

The first processor is a CPLD, the riser card to be tested is a PCI-E riser card, and the second processor is an MCU, as shown in FIG. 11 . The output voltage signal of the power supply reaches the detection voltage channel of the short-circuit board through the voltage pin of the PCI-E riser card. The detection voltage channel of the short-circuit board obtains the return voltage according to the output voltage of the voltage pin of the PCI-E riser card, and intervenes the return voltage. The wake-up pin to the PCI-E riser is output to the MCU. The MCU detects whether the return voltage of the PCI-ERiser card is normal through the ADC function, and then judges whether the power supply path of the PCI-E riser card is normal, so as to output the detection result to the CPLD through the UART pin.

Optionally, the power supply of the test motherboard can provide power supply of 5V, 3V3, and 12V, that is, the voltage pins include pins corresponding to 5V, 3V3, and 12V respectively; the wake-up pins include at least one of the WAKE pin and the RESET pin. .

Optionally, as shown in Figure 12, the short-circuit board includes a voltage pin and a wake-up pin; the short-circuited voltage pin is connected to the voltage pin of the adapter card to be tested; the wake-up pin of the short-circuit board is connected to the adapter card to be tested. the wake-up pin connection.

Correspondingly, the short-circuit board also includes a voltage pin and a wake-up pin, so that the short-circuit board forms a short-circuit loop with the test motherboard and the adapter card to be tested, and the connection of the power supply path in the adapter card to be tested is detected by outputting the third test signal. sex.

The first processor is a CPLD, the riser card to be tested is a PCI-E riser card, and the second processor is an MCU, as shown in FIG. 12 . The power supply outputs a 5V and/or 3V3 voltage signal to the PCI-E riser card, so that the internal sensors and other devices work normally, and the voltage signal is output to the voltage pin of the short-circuit board through the voltage pin of the PCI-E riser card. The short-circuit board obtains the return voltage according to the output voltage of the voltage pin of the PCI-E riser card, and the return voltage passes through the wake-up pin of the short-circuit board, intervenes into the wake-up pin of the PCI-E riser card and outputs it to the MCU. The MCU detects whether the return voltage of the PCI-E riser card is normal through the ADC function, and then judges whether the power supply path of the PCI-E riser card is normal, so as to output the detection result to the CPLD through the UART pin.

Optionally, LEDs can also be set in the short-circuit board to detect whether power is supplied to eliminate the failure of the short-circuit board not being powered, as shown in FIG. 13 .

In this embodiment, the 3V3 and 3V3_AUX of the PCI-E riser card are short-circuited with the WAKE and RESET signals respectively to form a loop, and the third test signal sent by the power supply of the test motherboard will all be returned to the CPLD of the test motherboard. , which can effectively avoid adding test tools such as cables, and can locate whether the power supply path of the PCI-E riser card is abnormal.

In the case where at least one channel of the riser card to be tested is abnormal, in one optional embodiment, as shown in FIG. 14 , the test mainboard further includes a buzzer, a digital tube, a at least one of the LEDs;

The first processor is further configured to output abnormal performance information through at least one of a buzzer, a digital tube, and an LED when it is determined that the performance of the riser card to be tested is abnormal.

In this embodiment, devices such as digital tubes, buzzers, and LEDs are provided on the test mainboard for alarm functions. The first processor is a CPLD, the adapter card to be tested is a PCI-E riser card, and the second processor Refer to Figure 14. When the CPLD detects that a certain channel of the PCI-E riser card is abnormal, it can output the abnormal information of the PCI-E riser card by controlling the buzzer to sound and the LED to flash. , and at the same time, the digital port number corresponding to the channel of the abnormal PCI-E riser card can be displayed through the digital tube. Optionally, the device for outputting abnormal information may also be a display screen, a liquid crystal screen, a diode, or other devices, which are not limited in this embodiment.

In this embodiment, the abnormal path information of the PCI-E riser card can be output through devices such as a buzzer, a digital tube, and an LED, which can effectively locate the abnormal path and improve the detection efficiency of the PCI-E riser card.

The test method provided in the embodiment of the present application can be applied to the test device shown in FIG. 1 . In one embodiment, as shown in FIG. 15 , a test method is provided, which is described by taking the method applied to the test device in FIG. 1 as an example, including the following steps:

Step 201 , output a test signal to the riser card to be tested through the test motherboard of the test device, so that the test signal reaches the short circuit board of the test device through the riser card to be tested.

In this embodiment, after the test device is powered on, a test signal is output to the adapter card to be tested through the test motherboard in the test device. Exemplarily, if the power supply path of the adapter card to be tested is detected, the output signal is output through the test motherboard. The test signal can be understood as a voltage value; if the IIC path of the riser card to be tested is detected, the test signal output by the test motherboard can be the IIC address information; if other paths of the riser card to be tested are detected, the test board can Output pulse modulated signal. In order to make the signal under test reach the short-circuit board through the adapter card to be tested, the signal output by the test motherboard in this embodiment is determined based on the path included in the adapter card to be tested.

Step 202 , output a return signal through the short-circuit board according to the output signal of the riser card to be tested, so that the return signal reaches the test motherboard after passing through the riser card to be tested.

In this embodiment, the short-circuit board outputs a return signal according to the received output signal of the riser card to be tested, so that the return signal passes through the riser card to be tested and reaches the test motherboard. If it is a voltage value, the short circuit board outputs the return voltage corresponding to the voltage value, and outputs the return voltage to the test motherboard through the adapter card to be tested; if the adapter card to be tested outputs IIC address information, the short circuit board outputs the IIC address The return IIC address information corresponding to the information is output to the test motherboard through the adapter card to be tested; if the adapter card to be tested outputs other signals, such as PWM signals, the short circuit board outputs the corresponding PWM signals. The return PWM signal is output to the test motherboard through the adapter card to be tested.

In step 203, the test mainboard performs signal analysis according to the return flow signal output by the short-circuit board to obtain a performance test result of the adapter card to be tested.

In this embodiment, the test mainboard performs signal analysis according to the received backflow signal. Optionally, the test mainboard can analyze the waveform of the backflow signal, the signal parameters of the backflow signal, or other parameters indicated by the backflow signal, such as voltage values, etc., to determine whether the path corresponding to the return signal is faulty, and obtain the performance test result of the adapter card to be tested. Optionally, in the scenario where the riser card to be tested includes multiple channels, that is, in the scenario where the test mainboard receives the backflow signals corresponding to the multiple channels, the test mainboard performs signal analysis on the backflow signals corresponding to all channels, and if there are any If the backflow signal corresponding to at least one channel is abnormal, that is, at least one channel is faulty, locate the channel and output the prompt information of the channel failure to determine that the performance of the adapter card to be tested is abnormal; if the backflow signal corresponding to all channels does not appear If it is abnormal, that is, all channels are normal, it is determined that the performance of the riser card to be tested is normal.

In the above test method, the test signal is output to the adapter card to be tested through the test motherboard of the test device, so that the test signal reaches the short circuit board of the test device through the adapter card to be tested; The signal outputs a return signal, so that the return signal reaches the test motherboard after passing through the adapter card to be tested; the test motherboard conducts signal analysis according to the return signal output by the short circuit board, and obtains the performance test result of the adapter card to be tested. In this solution, a signal loop is formed by the short circuit board in the test device, and the test main board in the test device can locate whether there is a problem with the passage of the adapter card to be tested according to the backflow signal. The synchronization performance test of the riser card does not require multiple insertions of the server motherboard to test the performance of the riser card to be tested, which reduces the mechanical complexity of the tooling, reduces the loss of the slot slot of the server motherboard, and prolongs the server The lifespan of the motherboard reduces the cost consumption.

It should be understood that, although the steps in the flowcharts involved in the above embodiments are sequentially displayed according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, the execution of these steps is not strictly limited to the order, and these steps may be performed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily executed and completed at the same time, but may be performed at different times The execution order of these steps or phases is not necessarily sequential, but may be performed alternately or alternately with other steps or at least a part of the steps or phases in the other steps.

In one embodiment, a computer device is provided, and the computer device may be a server, and its internal structure diagram may be as shown in FIG. 16 . The computer device includes a processor, memory, and a network interface connected by a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes non-volatile storage media and internal memory. The nonvolatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the execution of the operating system and computer programs in the non-volatile storage medium. The computer equipment's database is used to store test data. The network interface of the computer device is used to communicate with an external terminal through a network connection. The computer program when executed by a processor implements a testing method.

Those skilled in the art can understand that the structure shown in FIG. 16 is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer equipment to which the solution of the present application is applied. Include more or fewer components than shown in the figures, or combine certain components, or have a different arrangement of components.

In one embodiment, a computer device is provided, including a memory and a processor, a computer program is stored in the memory, and the processor implements the following steps when executing the computer program:

Output the test signal to the adapter card to be tested through the test motherboard of the test device, so that the test signal reaches the short circuit board of the test device through the adapter card to be tested;

Output the return signal through the short-circuit board according to the output signal of the riser card to be tested, so that the return signal reaches the test motherboard after passing through the riser card to be tested;

The performance test result of the adapter card to be tested is obtained by analyzing the signal according to the backflow signal output by the short circuit board by the test motherboard.

The implementation principles and technical effects of the computer equipment provided by the above embodiments are similar to those of the above method embodiments, and details are not described herein again.

In one embodiment, a computer-readable storage medium is provided on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

Output the test signal to the adapter card to be tested through the test motherboard of the test device, so that the test signal reaches the short circuit board of the test device through the adapter card to be tested;

Output the return signal through the short-circuit board according to the output signal of the riser card to be tested, so that the return signal reaches the test motherboard after passing through the riser card to be tested;

The performance test result of the adapter card to be tested is obtained by analyzing the signal according to the backflow signal output by the short circuit board by the test motherboard.

The implementation principles and technical effects of the computer-readable storage medium provided by the foregoing embodiments are similar to those of the foregoing method embodiments, and details are not described herein again.

In one embodiment, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the following steps:

Output the test signal to the adapter card to be tested through the test motherboard of the test device, so that the test signal reaches the short circuit board of the test device through the adapter card to be tested;

Output the return signal through the short-circuit board according to the output signal of the riser card to be tested, so that the return signal reaches the test motherboard after passing through the riser card to be tested;

The performance test result of the adapter card to be tested is obtained by analyzing the signal according to the backflow signal output by the short circuit board by the test motherboard.

The implementation principle and technical effect of the computer program product provided by the foregoing embodiments are similar to those of the foregoing method embodiments, and details are not described herein again.

It should be noted that the user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in this application are all Information and data authorized by the user or fully authorized by the parties.

Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be implemented by instructing relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage In the medium, when the computer program is executed, it may include the processes of the above-mentioned method embodiments. Wherein, any reference to a memory, a database or other media used in the various embodiments provided in this application may include at least one of a non-volatile memory and a volatile memory. Non-volatile memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive memory (ReRAM), magnetic variable memory (Magnetoresistive Random Memory) Access Memory, MRAM), Ferroelectric Random Access Memory (FRAM), Phase Change Memory (Phase Change Memory, PCM), graphene memory, etc. Volatile memory may include random access memory (Random Access Memory, RAM) or external cache memory, and the like. By way of illustration and not limitation, the RAM may be in various forms, such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM). The database involved in the various embodiments provided in this application may include at least one of a relational database and a non-relational database. The non-relational database may include a blockchain-based distributed database, etc., but is not limited thereto. The processors involved in the various embodiments provided in this application may be general-purpose processors, central processing units, graphics processors, digital signal processors, programmable logic devices, data processing logic devices based on quantum computing, etc., and are not limited to this.

The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, all It is considered to be the range described in this specification.

The above-mentioned embodiments only represent several embodiments of the present application, and the descriptions thereof are relatively specific and detailed, but should not be construed as a limitation on the scope of the patent of the present application. It should be pointed out that for those skilled in the art, without departing from the concept of the present application, several modifications and improvements can be made, which all belong to the protection scope of the present application. Therefore, the scope of protection of the present application should be determined by the appended claims.

Claims (10)

1. A test device, characterized in that, the test device comprises: a test mainboard and a short circuit board; the test mainboard is connected with an adapter card to be tested, and the adapter card to be tested is connected with the short circuit board; The test motherboard is used for outputting a test signal to the adapter card to be tested, so that the test signal reaches the short circuit board through the adapter card to be tested; The short circuit board is used for outputting a backflow signal according to the output signal of the adapter card to be tested, so that the backflow signal reaches the test motherboard after passing through the adapter card to be tested; The test mainboard is also used for performing signal analysis according to the backflow signal output by the short-circuit board to obtain the performance test result of the adapter card to be tested. 2. The device according to claim 1, wherein the test motherboard comprises a first processor; the first processor, configured to output a first test signal, so that the first test signal reaches the short-circuit board through the riser card to be tested; The short circuit board is used for outputting a first return signal according to the first output signal of the riser card to be tested, so that the first return flow signal reaches the test motherboard through the riser card to be tested; The first processor is further configured to perform signal analysis according to the first return signal, and obtain a performance test result of the channel between the transmitting end and the receiving end of the riser card to be tested. 3 . The device according to claim 2 , wherein the output end of the first processor is connected to the transmitting end of the adapter card to be tested, and the receiving end of the adapter card to be tested is connected to the adapter card to be tested. 4 . the input terminal of the first processor is connected; The transmitting end of the short circuit board is connected to the transmitting end of the adapter card to be tested, and the receiving end of the short circuit board is connected to the receiving end of the adapter card to be tested. 4. The device according to claim 2, wherein the test motherboard further comprises a second processor; the second processor, configured to output a second test signal, so that the second test signal reaches the short-circuit board through the riser card to be tested; The short circuit board is used for outputting a second return signal according to the second output signal of the riser card to be tested, so that the second return flow signal reaches the first processor through the riser card to be measured; The first processor is further configured to perform signal analysis on the second return flow signal to obtain a performance test result of the IIC path of the riser card to be tested. 5. The device according to claim 4, wherein the output end of the second processor is connected with the IIC pin of the adapter card to be tested; the 100M signal lead of the adapter card to be tested The pin is connected to the input end of the first processor, and the IIC pin and the 100M signal pin of the adapter card to be tested are connected to the short circuit board; The IIC pin of the short circuit board is connected with the IIC pin of the adapter card to be tested, and the 100M signal pin of the short circuit board is connected to the 100M signal pin of the adapter card to be tested. 6. The device according to claim 4, wherein the test motherboard further comprises a power supply; The power supply is used to output a third test signal, so that the third test signal reaches the short circuit board through the voltage pin of the adapter card to be tested; The short-circuit board is used to output a third return signal according to the third output signal of the voltage pin of the adapter card to be tested, so that the third return flow signal reaches the wake-up pin of the adapter card to be tested. the second processor; the second processor, further configured to output the third return signal to the first processor; The first processor is further configured to perform signal analysis on the third return flow signal to obtain a performance test result of the power supply path of the riser card to be tested. 7. The device according to claim 6, wherein the short-circuit board comprises a voltage pin and a wake-up pin; the short-circuited voltage pin is connected with the voltage pin of the adapter card to be tested; the The wake-up pin of the short-circuit board is connected to the wake-up pin of the adapter card to be tested. 8. A test method, characterized in that, applied to the test device according to any one of claims 1-7, the method comprising: Output a test signal to the adapter card to be tested through the test motherboard of the test device, so that the test signal reaches the short circuit board of the test device through the adapter card to be tested; Output a backflow signal through the short-circuit board according to the output signal of the riser card to be tested, so that the return flow signal reaches the test motherboard after passing through the riser card to be tested; The performance test result of the adapter card to be tested is obtained by performing signal analysis on the test main board according to the backflow signal output by the short circuit board. 9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein the processor implements the steps of the method of claim 8 when the processor executes the computer program. 10. A computer-readable storage medium on which a computer program is stored, characterized in that, when the computer program is executed by a processor, the steps of the method of claim 8 are implemented.

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