CN114488638A - Array substrate capable of avoiding active layer opening over-etching and manufacturing method thereof - Google Patents

Abstract

The invention relates to the technical field of liquid crystal display, in particular to an array substrate capable of reducing the contact resistance of the CH hole and a manufacturing method thereof. The array substrate capable of reducing the contact resistance of the CH hole comprises a substrate, and a gate is formed on the upper end of the substrate, The upper end of the substrate and the upper end of the gate are formed with a gate insulating layer, the upper end of the gate insulating layer and the gate on the right side are formed with an active layer, and the upper end of the gate insulating layer and the upper end of the active layer are formed. Both are formed with an etch stop layer. The invention can reduce the contact resistance of the CH hole in the array substrate. After the third insulating layer hole is opened on the third insulating layer, an additional pure molybdenum metal layer is added before the pixel electrode layer is formed, and the third insulating layer mask is used to match the negative Type photoresist method, a pure molybdenum metal layer is arranged between the source and drain electrodes and the pixel electrode layer to act as a bridge, thereby reducing the contact resistance between the pixel electrode layer and the source and drain electrodes, thereby ensuring the normal operation of the display screen. show.

Description

Array substrate capable of avoiding over-etching of active layer openings and manufacturing method thereof

technical field

The invention relates to the technical field of liquid crystal display, in particular to an array substrate capable of reducing the contact resistance of a CH hole and a manufacturing method thereof.

Background technique

At present, amorphous metal oxide semiconductors are developing rapidly. Among them, amorphous InGaZnO (IGZO) has become an ideal material for TFT preparation due to its simple preparation process and excellent optoelectronic properties. The prepared TFT has the characteristics of high mobility and high switching ratio, and has the potential to replace a-Si. potential. Compared with a-Si TFT, the carrier mobility of IGZO-TFT can reach 10~30cm2/V·S, which greatly improves the charge-discharge efficiency and response speed of TFT to the pixel electrode. More importantly, the IGZO process has good compatibility with the existing a-Si production line, and has a lower investment cost than low temperature polysilicon (LTPS) with more complex production process and higher equipment investment.

The existing In-Cell technology refers to the method of embedding the touch panel function into the liquid crystal pixel, thereby realizing the integrated design of the touch panel components and the liquid crystal panel. In the Array process, transparent materials such as ITO are used as the film layer of the common electrode and the pixel electrode, and the charge and discharge of the pixel is performed by overlapping the source and drain metal layers through the CH hole. In the actual mass production process, the lap resistance between the ITO and the metal layer often affects the charging and discharging efficiency. In severe cases, it will directly affect the normal display of the display screen, resulting in uneven screen display or other Mura defects. and many more. Most of the existing SD source and drain materials are mainly composed of TiAlTi three-layer composite metal, in which Al is the main conductive film layer, and Ti is mainly used as a buffer layer to improve the contact interface between Al and the inorganic film layer and protect Al from being oxidized. However, in the actual product manufacturing process, it will be found that the contact resistance between Ti and ITO will far exceed the design value, reaching 105Ω, which will cause the above-mentioned problems such as pixel charging and discharging and screen display unevenness. It is because the oxygen atoms of the ITO target in the Sputter process will cause Ti oxidation on the surface of the TiAlTi source and drain metal, forming high-resistance TiOx, which in turn affects the lap resistance. The direct improvement method is to replace the transparent electrode material or source and drain. Extremely metallic material.

At present, the available metals in the market include Mo/Al/Mo, Cu and Ag. However, the cost of Ag is too high. Although Mo and Cu are low in cost, they have poor contact with the inorganic film layer SiOx, especially some inorganic films at high temperatures. The phenomenon of floating film or peeling will appear in the quality of the inorganic film, which greatly limits the choice of film quality of the inorganic film layer, resulting in other types of Issues. Although the Mo/Al/Mo metal layer as a conductive layer has requirements on the inorganic film layer, the contact resistance between Mo and ITO is very small, which conforms to the existing design specification value, which is about 103Ω.

To this end, we introduce an array substrate that can reduce the contact resistance of the CH hole and its fabrication method.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide an array substrate capable of reducing the contact resistance of the CH hole and a manufacturing method thereof, so as to solve the problems raised in the above background art.

In order to achieve the above object, the present invention provides the following technical solutions: an array substrate capable of reducing the contact resistance of the CH hole, comprising a substrate, a gate electrode is formed on the upper end of the substrate, and gate insulation is formed on the upper end of the substrate and the gate electrode. layer, an active layer is formed on the upper end of the gate insulating layer and at the gate on the right side, an etch barrier layer is formed on the upper end of the gate insulating layer and the upper end of the active layer, and the etch barrier layer An etching barrier hole and a power supply jack are etched on the upper end, a source and drain are formed on the upper end of the etching barrier layer, the upper end of the source and drain is covered with a first insulating layer, and the upper end of the first insulating layer is coated with organic flat layer, the organic flat layer is mainly made of organic material, covering the first insulating layer, the organic flat layer hole is formed on the organic flat layer, the touch metal layer is formed on the upper end of the organic flat layer, and the upper end of the organic flat layer is formed A second insulating layer is deposited on the upper end of the touch metal layer and the touch metal layer, a second insulating layer hole is dry-etched on the second insulating layer and located at the touch metal layer, and the upper end of the second insulating layer is located in the second insulating layer. A common electrode layer is deposited at the hole, the common electrode layer is overlapped with the touch metal layer through the second insulating layer hole, and a third insulating layer is deposited on the upper end of the second insulating layer and the upper end of the common electrode layer. A third insulating layer hole is formed on the three insulating layers, a pure molybdenum metal layer is deposited on the upper end of the third insulating layer, and a pixel electrode layer is formed on both the upper end of the third insulating layer and the upper end of the pure molybdenum metal layer.

The gate is a molybdenum aluminum molybdenum layer or a titanium aluminum titanium layer.

The gate insulating layer is a silicon oxide layer.

The active layer is an indium gallium zinc oxide layer.

The etching barrier layer and the first insulating layer are both silicon oxide layers. The etching barrier layer is an insulating layer with a larger dielectric constant, which protects the active layer from being etched by the source-drain etching solution or gas; the first insulating layer is an insulating layer with a larger dielectric constant, which blocks water and oxygen, Avoid its impact on the stability of the device on the top of the substrate.

The touch metal layer is a molybdenum aluminum molybdenum layer.

The second insulating layer and the third insulating layer are both silicon oxide layers or silicon nitride layers. The third insulating layer is an insulating layer with a relatively large dielectric constant, which facilitates the connection between the pixel electrode layer and the source and drain electrodes.

The common electrode layer and the pixel electrode layer are both indium tin oxide layers.

The pure molybdenum metal layer is interposed between the pixel electrode layer and the source and drain electrodes and plays a bridging role, avoiding the problem that the resistance of the third insulating layer is too large due to the direct overlap between the pixel electrode layer and the source and drain electrodes.

A method for manufacturing an array substrate capable of reducing the contact resistance of a CH hole, specifically comprising the following steps:

S1, forming a gate electrode and a gate insulating layer on the substrate in sequence;

S2, forming an active layer at the upper end of the gate insulating layer corresponding to the right gate;

S3, forming an etching barrier layer on the upper end of the gate insulating layer and the upper end of the active layer, and etching out the etching barrier layer hole and the power jack;

S4, forming a source and drain on the upper end of the etching barrier layer;

S5, covering a first insulating layer on the source and drain;

S6, coating an organic flat layer on the upper end of the first insulating layer, and forming organic flat layer holes;

S7, forming a touch metal layer on the upper end of the organic flat layer;

S8, depositing a second insulating layer on the touch metal layer, and forming a second insulating layer hole;

S9, depositing a layer of a common electrode layer on the upper end of the second insulating layer and located at the hole of the second insulating layer, and the common electrode layer is overlapped with the touch metal layer through the second insulating layer hole;

S10, depositing a third insulating layer on the upper end of the common electrode layer, and forming a third insulating layer hole;

S11, depositing a layer of pure molybdenum metal layer on the upper end of the third insulating layer;

S12, coating a layer of negative photoresist layer on the pure molybdenum metal layer, and exposing and developing with the third insulating layer mask;

S13. According to the characteristics of negative photoresist, after exposure through the third insulating layer mask, the photoresist at the position of the third insulating layer hole remains after exposure and development;

S14, wet etching the developed substrate, using aluminate for etching, and etching away the pure molybdenum metal layer not covered by the photoresist;

S15, performing a film stripping process to remove the negative photoresist layer on the remaining pure molybdenum metal layer;

S16, forming a pixel electrode layer on the upper end of the third insulating layer and the upper end of the pure molybdenum metal layer.

Compared with the prior art, the beneficial effects of the present invention are:

1. The array substrate of the present invention can reduce the contact resistance of the CH hole. After the third insulating layer hole is opened on the third insulating layer, before the pixel electrode layer is formed into a film, an additional pure molybdenum metal layer is added, and the third insulating layer mask is used. With the method of negative photoresist, a pure molybdenum metal layer is arranged between the source and drain electrodes and the pixel electrode layer to act as a bridge, thereby reducing the contact resistance between the pixel electrode layer and the source and drain electrodes, thereby ensuring the display screen. the normal display;

2. The present invention can reduce the contact resistance of the CH hole in the manufacturing method of the array substrate. After the third insulating layer hole is opened on the third insulating layer, an additional pure molybdenum metal layer is added before the film formation of the pixel electrode layer. A layer of negative photoresist is coated on the layer, and the third insulating layer mask is used for exposure and development, and then wet etching is performed, which not only effectively improves the resistance problem, but also is very beneficial for mass production.

Description of drawings

FIG. 1 is a schematic structural diagram of an array substrate capable of reducing the contact resistance of CH holes according to the present invention;

FIG. 2 is a schematic structural diagram of step S1 of the manufacturing method of the array substrate capable of reducing the contact resistance of the CH hole according to the present invention;

3 is a schematic structural diagram of step S2 of the manufacturing method of the array substrate capable of reducing the contact resistance of the CH hole according to the present invention;

4 is a schematic structural diagram of step S3 of the manufacturing method of the array substrate capable of reducing the contact resistance of the CH hole according to the present invention;

5 is a schematic structural diagram of step S4 of the manufacturing method of the array substrate capable of reducing the contact resistance of the CH hole according to the present invention;

6 is a schematic structural diagram of step S5 of the manufacturing method of the array substrate capable of reducing the contact resistance of the CH hole according to the present invention;

7 is a schematic structural diagram of step S6 of the manufacturing method of the array substrate capable of reducing the contact resistance of the CH hole according to the present invention;

8 is a schematic structural diagram of step S7 of the manufacturing method of the array substrate capable of reducing the contact resistance of the CH hole according to the present invention;

9 is a schematic structural diagram of step S8 of the manufacturing method of the array substrate capable of reducing the contact resistance of the CH hole according to the present invention;

10 is a schematic structural diagram of step S9 of the manufacturing method of the array substrate capable of reducing the contact resistance of the CH hole according to the present invention;

11 is a schematic structural diagram of step S10 of the manufacturing method of the array substrate capable of reducing the contact resistance of the CH hole according to the present invention;

FIG. 12 is a schematic structural diagram of step S11 of the manufacturing method of the array substrate capable of reducing the contact resistance of the CH hole according to the present invention;

13 is a schematic structural diagram of step S12 of the manufacturing method of the array substrate capable of reducing the contact resistance of the CH hole according to the present invention;

FIG. 14 is a schematic structural diagram of step S13 of the manufacturing method of the array substrate capable of reducing the contact resistance of the CH hole according to the present invention;

15 is a schematic structural diagram of step S14 of the manufacturing method of the array substrate capable of reducing the contact resistance of the CH hole according to the present invention;

16 is a schematic structural diagram of step S15 of the manufacturing method of the array substrate capable of reducing the contact resistance of the CH hole according to the present invention;

FIG. 17 is a schematic structural diagram of step S16 of the manufacturing method of the array substrate capable of reducing the contact resistance of the CH hole according to the present invention.

In the figure: 1. Substrate; 2. Gate; 3. Gate insulating layer; 4. Active layer; 5. Etching barrier layer; 6. Source and drain; 7. First insulating layer; 8. Organic flat layer 9, touch metal layer; 10, second insulating layer; 11, common electrode layer; 12, third insulating layer; 13, pure molybdenum metal layer; 14, pixel electrode layer.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

Referring to FIG. 1, the present invention provides a technical solution: an array substrate that can reduce the contact resistance of the CH hole, comprising a substrate 1, which is a basic component of a display device, and a gate 2 is formed on the upper end of the substrate 1, so The gate 2 is a molybdenum-aluminum-molybdenum layer or a titanium-aluminum-titanium layer, a gate insulating layer 3 is formed on the upper end of the substrate 1 and the upper end of the gate 2, the gate insulating layer 3 is a silicon oxide layer, and the gate insulating layer 3 is a silicon oxide layer. An active layer 4 is formed on the upper end of the gate insulating layer 3 and at the gate 2 on the right side. The active layer 4 is an indium gallium zinc oxide layer. The upper end of the gate insulating layer 3 and the upper end of the active layer 4 are formed. Both are formed with an etching barrier layer 5, the etching barrier layer 5 is a silicon oxide layer, and the etching barrier layer 5 is an insulating layer with a larger dielectric constant, which protects the active layer 4 from being etched by the source and drain 6 Liquid or gas etching, the etching barrier layer 5 is etched with an etching barrier layer hole and a power supply jack, the upper end of the etching barrier layer 5 is formed with a source drain 6, and the upper end of the source drain 6 is covered with a third An insulating layer 7, the first insulating layer 7 is a silicon oxide layer, and the first insulating layer 7 is an insulating layer with a relatively large dielectric constant, which blocks water and oxygen and prevents them from affecting the stability of the devices at the upper end of the substrate 1. Influence, the upper end of the first insulating layer 7 is coated with an organic flat layer 8, the organic flat layer 8 is mainly made of organic material and covers the first insulating layer 7, and the organic flat layer holes are formed on the organic flat layer 8, so A touch metal layer 9 is formed on the upper end of the organic flat layer 8, the touch metal layer 9 is a molybdenum aluminum molybdenum layer, and a second insulating layer 10 is deposited on the upper end of the organic flat layer 8 and the touch metal layer 9. The second insulating layer 10 is a silicon oxide layer or a silicon nitride layer. A second insulating layer hole is dry-etched on the second insulating layer 10 and located at the touch metal layer 9 . The second insulating layer 10 is dry-etched. A common electrode layer 11 is deposited on the upper end and located at the hole of the second insulating layer, the common electrode layer 11 is an indium tin oxide layer, and the common electrode layer 11 is overlapped with the touch metal layer 9 through the second insulating layer hole, so The upper end of the second insulating layer 10 and the upper end of the common electrode layer 11 are both deposited with a third insulating layer 12, the third insulating layer 12 is a silicon oxide layer or a silicon nitride layer, and the third insulating layer 12 has a larger dielectric. The insulating layer of electric constant is convenient for the connection between the pixel electrode layer 14 and the source and drain electrodes 6, a third insulating layer hole is formed on the third insulating layer 12, and a pure molybdenum metal layer 13 is deposited on the upper end of the third insulating layer 12, The pure molybdenum metal layer 13 is interposed between the pixel electrode layer 14 and the source and drain electrodes 6 and acts as a bridge to avoid the direct overlap between the pixel electrode layer 14 and the source and drain electrodes 6 , which may cause the resistance of the third insulating layer 12 to be too large. The problem is that a pixel electrode layer 14 is formed on the upper end of the third insulating layer 12 and the upper end of the pure molybdenum metal layer 13, and the pixel electrode layer 14 is an indium tin oxide layer.

Please refer to FIGS. 2-17 , a method for manufacturing an array substrate capable of reducing the contact resistance of the CH hole, which specifically includes the following steps:

S1, forming a gate 2 and a gate insulating layer 3 on the substrate 1 in sequence;

S2, forming an active layer 4 at the upper end of the gate insulating layer 3 corresponding to the right gate 2;

S3, forming an etching barrier layer 5 on the upper end of the gate insulating layer 3 and the upper end of the active layer 4, and etching out the etching barrier layer hole and the power jack;

S4, forming a source and drain 6 on the upper end of the etching barrier layer 5;

S5, covering a first insulating layer 7 on the source and drain electrodes 6;

S6, coating a layer of organic flat layer 8 on the upper end of the first insulating layer 7, and forming organic flat layer holes;

S7, forming a touch metal layer 9 on the upper end of the organic flat layer 8;

S8, depositing a second insulating layer 10 on the touch metal layer 9, and forming a second insulating layer hole;

S9, depositing a layer of common electrode layer 11 on the upper end of the second insulating layer 10 and at the place where the second insulating layer hole is located, and the common electrode layer 11 is overlapped with the touch metal layer 9 through the second insulating layer hole;

S10, depositing a third insulating layer 12 on the upper end of the common electrode layer 11, and forming a third insulating layer hole;

S11, depositing a layer of pure molybdenum metal layer 13 on the upper end of the third insulating layer 12;

S12, coating a layer of negative photoresist layer on the pure molybdenum metal layer 13, and exposing and developing with the third insulating layer mask;

S13. According to the characteristics of negative photoresist, after exposure through the third insulating layer mask, the photoresist at the position of the third insulating layer hole remains after exposure and development;

S14, wet etching the developed substrate 1, using aluminate for etching, and etching away the pure molybdenum metal layer 13 not covered by the photoresist;

S15, performing a film stripping process to remove the negative photoresist layer on the remaining pure molybdenum metal layer 13;

S16 , forming a pixel electrode layer 14 on the upper end of the third insulating layer 12 and the upper end of the pure molybdenum metal layer 13 .

To sum up, compared with the prior art:

1. The array substrate of the present invention can reduce the contact resistance of the CH hole. After the third insulating layer hole is opened on the third insulating layer 12, before the pixel electrode layer 14 is formed into a film, an additional pure molybdenum metal layer 13 is added to the third insulating layer. In the method of layering a photomask with a negative photoresist, a pure molybdenum metal layer 13 is arranged between the source and drain electrodes 6 and the pixel electrode layer 14 to act as a bridge, thereby reducing the distance between the pixel electrode layer 14 and the source and drain electrodes 6 . Contact resistance, so as to ensure the normal display of the display screen;

2. In the manufacturing method of the array substrate capable of reducing the contact resistance of the CH hole of the present invention, an additional pure molybdenum metal layer 13 is added before the pixel electrode layer 14 is formed after the third insulating layer hole is opened on the third insulating layer 12. The pure molybdenum metal layer 13 is coated with a negative-type photoresist layer, exposed and developed with a third insulating layer mask, and then wet-etched, which not only effectively improves the resistance problem, but also is very beneficial for mass production.

Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, and substitutions can be made in these embodiments without departing from the principle and spirit of the invention and modifications, the scope of the present invention is defined by the appended claims and their equivalents.

Claims (10)

1. An array substrate capable of reducing CH hole contact impedance comprises a substrate (1), and is characterized in that: the organic light-emitting diode display panel is characterized in that a grid electrode (2) is formed at the upper end of a substrate (1), a grid electrode insulating layer (3) is formed at the upper end of the substrate (1) and the upper end of the grid electrode (2), an active layer (4) is formed at the position of the grid electrode (2) and is located at the upper end of the grid electrode (3), an etching barrier layer (5) is formed at the upper end of the grid electrode insulating layer (3) and the upper end of the active layer (4), an etching barrier layer hole and a power jack are etched in the etching barrier layer (5), an active drain electrode (6) is formed at the upper end of the etching barrier layer (5), a first insulating layer (7) covers the upper end of the source drain electrode (6), an organic flat layer (8) is coated at the upper end of the first insulating layer (7), an organic flat layer hole is formed in the organic flat layer (8), a touch metal layer (9) is formed at the upper end of the organic flat layer (8), and a second insulating layer (a touch layer (8) (9) is deposited at the upper end of the touch metal layer 10) The utility model discloses a touch-control metal layer (9) on the first insulating layer (10) and be located the dry etching of touch-control metal layer (9) department and have the second insulating layer hole, second insulating layer (10) upper end and be located second insulating layer hole department deposit and have public electrode layer (11), public electrode layer (11) are through second insulating layer hole and touch-control metal layer (9) overlap joint, second insulating layer (10) upper end and public electrode layer (11) upper end all deposit have third insulating layer (12), be formed with the third insulating layer hole on third insulating layer (12), third insulating layer (12) upper end deposit has pure molybdenum metal layer (13), third insulating layer (12) upper end and pure molybdenum metal layer (13) upper end all are formed with pixel electrode layer (14).

2. The array substrate of claim 1, wherein the array substrate is capable of reducing the contact resistance of the CH hole, and comprises: the grid (2) is a molybdenum aluminum molybdenum layer or a titanium aluminum titanium layer.

3. The array substrate of claim 1, wherein the array substrate is capable of reducing the contact resistance of the CH hole, and comprises: the gate insulating layer (3) is a silicon oxide layer.

4. The array substrate of claim 1, wherein the array substrate is capable of reducing contact resistance of the CH hole, and comprises: the active layer (4) is an indium gallium zinc oxide layer.

5. The array substrate of claim 1, wherein the array substrate is capable of reducing the contact resistance of the CH hole, and comprises: the etching barrier layer (5) and the first insulating layer (7) are both silicon oxide layers.

6. The array substrate of claim 1, wherein the array substrate is capable of reducing the contact resistance of the CH hole, and comprises: the touch metal layer (9) is a molybdenum aluminum molybdenum layer.

7. The array substrate of claim 1, wherein the array substrate is capable of reducing the contact resistance of the CH hole, and comprises: the second insulating layer (10) and the third insulating layer (12) are both silicon oxide layers or silicon nitride layers.

8. The array substrate of claim 1, wherein the array substrate is capable of reducing the contact resistance of the CH hole, and comprises: the common electrode layer (11) and the pixel electrode layer (14) are both indium tin oxide layers.

9. The array substrate of claim 1, wherein the array substrate is capable of reducing the contact resistance of the CH hole, and comprises: the pure molybdenum metal layer (13) is arranged between the pixel electrode layer (14) and the source drain electrode (6).

10. A method for manufacturing an array substrate capable of reducing CH hole contact resistance according to any one of claims 1 to 9, wherein: the method specifically comprises the following steps:

s1, sequentially forming a gate (2) and a gate insulating layer (3) on the substrate (1);

s2, forming an active layer (4) at the position, corresponding to the right side grid (2), of the upper end of the grid insulation layer (3);

s3, forming an etching barrier layer (5) on the upper end of the gate insulating layer (3) and the upper end of the active layer (4), and etching an etching barrier layer hole and a power supply jack;

s4, forming a source drain electrode (6) at the upper end of the etching barrier layer (5);

s5, covering a first insulating layer (7) on the source drain electrode (6);

s6, coating an organic flat layer (8) on the upper end of the first insulating layer (7) and forming an organic flat layer hole;

s7, forming a touch metal layer (9) on the upper end of the organic flat layer (8);

s8, depositing a second insulating layer (10) on the touch metal layer (9) and forming a second insulating layer hole;

s9, depositing a common electrode layer (11) at the upper end of the second insulating layer (10) and at the position of the second insulating layer hole, wherein the common electrode layer (11) is overlapped with the touch metal layer (9) through the second insulating layer hole;

s10, depositing a third insulating layer (12) on the upper end of the common electrode layer (11) and forming a third insulating layer hole;

s11, depositing a pure molybdenum metal layer (13) on the upper end of the third insulating layer (12);

s12, coating a negative photoresist layer on the pure molybdenum metal layer (13), and performing exposure and development by using a third insulating layer photomask;

s13, according to the characteristics of the negative photoresist, after the photoresist at the hole position of the third insulating layer is exposed and developed by the photomask of the third insulating layer, the photoresist at the hole position of the third insulating layer is remained;

s14, wet etching the developed substrate (1), wherein the etching adopts aluminic acid, and the pure molybdenum metal layer (13) which is not covered by the photoresist is etched;

s15, performing a film stripping process to remove the negative photoresist layer on the residual pure molybdenum metal layer (13);

and S16, forming a pixel electrode layer (14) on the upper end of the third insulating layer (12) and the upper end of the pure molybdenum metal layer (13).

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