CN114464670B - A kind of ultra-low specific conductance superjunction MOSFET and preparation method thereof - Google Patents

Abstract

A super-junction MOSFET with ultra-low specific conductance and a preparation method thereof are disclosed, wherein a second conductive type semiconductor base region is arranged at the top of a first conductive type semiconductor doping column region, a groove type polycrystalline silicon gate electrode is arranged above the second conductive type semiconductor column region, all the side faces and the bottom face of the polycrystalline silicon gate electrode are surrounded by a gate dielectric layer, a low-doped semiconductor intermediate layer is arranged between the first conductive type semiconductor doping column region and the second conductive type semiconductor column region, the semiconductor intermediate layer is positioned below the second conductive type semiconductor base region, the top of the semiconductor intermediate layer wraps the corner of the bottom of the gate dielectric layer, and the lateral dimension of the semiconductor intermediate layer is smaller from the top to the bottom and is closer to the bottom. The invention provides a novel structure and a process preparation method thereof, which can reduce the difficulty of a grooving process, obtain lower on-resistance and higher breakdown voltage and reliability, and are particularly suitable for a super junction MOSFET with a cell pitch below 5 mu m.

Description

A kind of ultra-low specific conductance superjunction MOSFET and preparation method thereof

technical field

The invention belongs to the technical field of semiconductors, relates to a super-junction MOSFET, and is an ultra-low specific conductance super-junction MOSFET and a preparation method thereof.

Background technique

Superjunction MOSFETs introduce a high concentration of iso-shaped charges in the withstand voltage layer to satisfy the charge balance, generate a two-dimensional field, and introduce the field optimization from the surface into the body, which increases the withstand voltage of the device and greatly reduces the on-resistance of the device. The structure of the superjunction MOSFET is shown in Figure 1. In order to achieve lower specific on-resistance, the development trend of superjunction devices is to continuously increase the doping concentration of the PN column. However, since the electric field in the drift region of the superjunction MOSFET can be regarded as the superposition of the transverse electric field and the longitudinal electric field, the breakdown voltage of the superjunction device will also be limited by the peak value of the transverse electric field in the case of high concentration doping of the P and N pillars. . As shown in Figure 2, if the lateral electric field peak exceeds the critical breakdown electric field Ec, the device will undergo lateral breakdown. Therefore, when the vertical electric field is optimized, the lateral electric field becomes the bottleneck for improving the withstand voltage of superjunction devices. Limited by the lateral breakdown between the PN columns, increasing the doping concentration of the PN columns requires reducing the lateral dimensions of the PN columns. The current state-of-the-art superjunction devices have cell pitches down to close to 5μm. In this case, if the trench filling process is adopted, the aspect ratio of the trench will reach or even exceed 10:1, and the device fabrication will be more difficult.

SUMMARY OF THE INVENTION

In view of the above problems, in order to improve the withstand voltage performance of the superjunction MOSFET in the lateral electric field, the present invention proposes a new structure and a process preparation method, which can reduce the difficulty of the trenching process and obtain lower on-resistance and higher strike. Breakthrough voltage and reliability are especially suitable for superjunction MOSFETs with cell pitch below 5μm.

The technical scheme of the present invention is: an ultra-low specific conductance superjunction MOSFET, the superjunction MOSFET comprises a PN column structure composed of a first conductive type semiconductor doped column region and a second conductive type semiconductor column region, the first conductive type The top of the semiconductor doped pillar region has a second conductive type semiconductor base region, the top of the second conductive type semiconductor pillar region has a trench type polysilicon gate electrode, and the lower surface of the polysilicon gate electrode is lower than the lower surface of the second conductive type semiconductor base region On the surface, all sides and bottom surfaces of the polysilicon gate electrode are surrounded by a gate dielectric layer, and the top surface and the metallized source electrode are separated by an insulating dielectric layer. The first conductive type semiconductor doped column region and the second conductive type There is a layer of low-doped semiconductor intermediate layer between the semiconductor pillar regions, low doping refers to the doping concentration lower than that of the PN pillar, the semiconductor intermediate layer is located below the second conductive type semiconductor base region, and the semiconductor intermediate layer The top of the top wraps the bottom corner of the gate dielectric layer, and from the top to the bottom of the semiconductor intermediate layer, the closer to the bottom of the second conductive type semiconductor pillar region, the smaller the lateral dimension.

Further, the semiconductor intermediate layer is a low-doped first conductive type semiconductor layer or an intrinsic layer.

Further, the total amount of impurities in the first conductive type semiconductor doped column region and the semiconductor intermediate layer of the first conductive type semiconductor is equal to the total amount of impurities in the second conductive type semiconductor column region.

Further, the cell pitch of the superjunction MOSFET is below 5 μm, the doping concentration of the first conductive type semiconductor pillar region and the second conductive type semiconductor pillar region is greater than or equal to 5e15cm ⁻³ , the lateral dimension is less than or equal to 2 μm, and the semiconductor intermediate layer The doping concentration is more than 2 orders of magnitude lower than the doping concentration of the first conductive type semiconductor column region and the second conductive type semiconductor column region, and the lateral dimension is less than or equal to 0.5 μm.

Further, the first type of conductivity type semiconductor is a P-type semiconductor, and the second type of conductivity type semiconductor is an N-type semiconductor; or the first type of conductivity type semiconductor is an N-type semiconductor, and the second type of conductivity type semiconductor is a P-type semiconductor.

The present invention also provides a method for manufacturing an ultra-low specific conductance super-junction MOSFET, which adopts a trench filling process to manufacture the above-mentioned super-junction MOSFET with a low-doped intermediate layer between the PN columns.

The beneficial effects of the invention are as follows: the super-junction MOSFET introduces high-concentration equal-quantity hetero-shaped charges into the pressure-resistant layer, satisfies the charge balance, generates a two-dimensional field, and optimizes the introduction of the field from the surface into the body, thereby increasing the withstand voltage of the device and greatly reducing the device. on-resistance. However, since the electric field in the drift region of the superjunction MOSFET can be regarded as the superposition of the lateral electric field and the longitudinal electric field, the breakdown voltage of the superjunction device will also be limited by the peak value of the lateral electric field when the P and N pillars are doped with high concentrations. . Aiming at the super junction MOSFET with the cell pitch of less than 5 μm, the invention can reduce the lateral electric field in the drift region of the super junction device and improve the withstand voltage of the device by introducing a low-doped layer or an intrinsic layer between the P column and the N column. The low-doped layer or the intrinsic layer wraps the bottom corner of the trench gate, which is also beneficial to reduce the electric field at the corner and improve the withstand voltage and reliability of the device. The trench gate structure of the present invention is beneficial to reduce the specific on-resistance; the closer to the bottom of the second conductive type semiconductor pillar region, the smaller the lateral size of the intermediate layer is, which is beneficial to reduce the influence of the JFET effect and the specific conductance. On resistance. At the same time, when the new structure of the super-junction MOSFET of the present invention is manufactured by adopting the trenching process, the aspect ratio of the trench is reduced, which reduces the difficulty of preparation.

Description of drawings

FIG. 1 is a schematic structural diagram of a superjunction MOSFET device in the prior art.

FIG. 2 is a schematic diagram of a longitudinal electric field and a transverse electric field of a conventional superjunction MOSFET device.

FIG. 3 is a schematic structural diagram of a superjunction MOSFET device of the present invention.

FIG. 4 is a schematic diagram of the vertical electric field and the lateral electric field of the superjunction MOSFET device of the present invention.

FIG. 5 is a schematic diagram showing the comparison of the lateral electric field of the superjunction MOSFET of the prior art and the superjunction MOSFET of the present invention.

FIG. 6 is a schematic diagram of the fabrication steps of the trench filling process for the superjunction MOSFET device of the present invention, which corresponds to step 1 of Embodiment 1. FIG.

FIG. 7 is a schematic diagram of the fabrication steps of the trench filling process of the superjunction MOSFET device of the present invention, which corresponds to step 2 of Embodiment 1. FIG.

FIG. 8 is a schematic diagram of the fabrication steps of the trench filling process of the superjunction MOSFET device according to the present invention, which corresponds to step 3 of Embodiment 1. FIG.

FIG. 9 is a schematic diagram of the fabrication steps of the trench filling process of the superjunction MOSFET device of the present invention, which corresponds to step 4 of Embodiment 1. FIG.

FIG. 10 is a schematic diagram of the fabrication steps of the trench filling process of the superjunction MOSFET device of the present invention, which corresponds to step 5 of Embodiment 1. FIG.

FIG. 11 is a schematic diagram of the fabrication steps of the trench filling process of the superjunction MOSFET device of the present invention, corresponding to steps 6 and 7 of Embodiment 1. FIG.

FIG. 12 is a schematic diagram of the fabrication steps of the trench filling process of the superjunction MOSFET device of the present invention, which corresponds to step 8 of Embodiment 1. FIG.

FIG. 13 is a schematic diagram of the fabrication steps of the trench filling process for the superjunction MOSFET device of the present invention, which corresponds to steps 9 and 10 of Embodiment 1. FIG.

FIG. 14 is a schematic diagram of the fabrication steps of the trench filling process for the superjunction MOSFET device of the present invention, which corresponds to step 11 of the first embodiment.

FIG. 15 is a schematic diagram of the fabrication steps of the trench filling process of the superjunction MOSFET device of the present invention, which corresponds to step 12 of the first embodiment.

Detailed ways

The lateral electric field limits the withstand voltage of the device only when the lateral dimension of the PN column is small. Therefore, the main thing that needs to be improved is the lateral electric field when the lateral dimension of the PN column is small. The present invention is aimed at superjunction MOSFETs with cell pitch below 5 μm , in order to solve the problem that the lateral electric field of the super-junction MOSFET with extremely small PN column width is too high, an ultra-low specific conductance super-junction MOSFET is proposed. A first conductive type semiconductor doped substrate 2 , a first conductive type semiconductor doped column region 3 and a second conductive type semiconductor column region 5 located on the first conductive type semiconductor doped substrate 2 . The first conductive type semiconductor doped column region 3 and the second conductive type semiconductor column region 5 constitute a PN column structure, and the top of the first conductive type semiconductor doped column region 3 has a second conductive type semiconductor base region 6, and the second conductive type The inner upper surface of the semiconductor base region 6 has a first conductivity type semiconductor doped source region 7 and a second conductivity type semiconductor doped contact region 8, and part of the upper surface of the first conductivity type semiconductor doped source region 7 and the second conductivity type The entire upper surface of the semiconductor doped contact region 8 is in contact with the metallized source electrode 12; the upper surface of the second conductive type semiconductor pillar region 5 has a trench-type polysilicon gate electrode 9, and the lower surface of the polysilicon gate electrode 9 is lower than the second conductive type. The lower surface of the conductive type semiconductor base region 6, the entire side and bottom surfaces of the polysilicon gate electrode 9 are surrounded by the gate dielectric layer 10, the top surface and the metallized source electrode 12 are isolated by the insulating dielectric layer 11, and the gate dielectric layer The side surfaces of 10 are in direct contact with the side surfaces of the first conductivity type semiconductor doped source region 7 and the second conductivity type semiconductor base region 6 , and the lower surface of the polysilicon gate electrode 9 is lower than the lower surface of the second conductivity type semiconductor base region 6 . The present invention has a low-doped semiconductor intermediate layer 4 between the first conductive type semiconductor doping column region 3 and the second conductive type semiconductor column region 5, and the low doping refers to the doping concentration of the PN column. Low, the semiconductor interlayer 4 is located below the second conductive type semiconductor base region 6, and the top of the semiconductor interlayer 4 wraps the bottom corner of the gate dielectric layer 10, the semiconductor interlayer 4 is from the top to the bottom, the closer to the second conductive type semiconductor column The bottom of zone 5, the smaller the lateral dimension.

Further, the semiconductor intermediate layer 4 is a low-doped first conductive type semiconductor layer or an intrinsic layer. The total amount of impurities in the first conductive type semiconductor doped column region 3 and the first conductive type semiconductor intermediate layer 4 is equal to the total amount of impurities in the second conductive type semiconductor column region 5 .

The present invention is especially suitable for the case where the cell pitch of the superjunction MOSFET is below 5 μm, the preferred embodiment: the doping concentration of the first conductive type semiconductor column region 3 and the second conductive type semiconductor column region 5 is greater than or equal to 5e15cm ⁻³ , The lateral dimension is less than or equal to 2 μm, the doping concentration of the semiconductor intermediate layer 4 is more than 2 orders of magnitude lower than the doping concentration of the first conductive type semiconductor column region 3 and the second conductive type semiconductor column region 5, and the lateral dimension is less than or equal to 0.5 μm.

In the present invention, the first type of conductivity type semiconductor is a P-type semiconductor, and the second type of conductivity type semiconductor is an N-type semiconductor; or the first type of conductivity type semiconductor is an N-type semiconductor, and the second type of conductivity type semiconductor is a P-type semiconductor .

The method for manufacturing the ultra-low specific conductance superjunction MOSFET of the present invention adopts the trench filling process to manufacture the superjunction MOSFET with a low-doped intermediate layer between the PN columns. Taking the first type of conductivity type semiconductor as an N-type semiconductor and the second type of conductivity type as a P-type semiconductor as an example, the description is as follows.

Example 1

The trench filling process is adopted, as shown in Figure 6-Figure 15.

1. An N-type epitaxial layer is grown on the N-type heavily doped substrate 2 .

2. The silicon wafer is etched through processes such as gluing, exposure, development, and etching to form a deep groove in the N-type epitaxial layer, and the width of the deep groove is greater than the width of the P-pillar. By adjusting the etching process parameters, the bottom of the trench is in a circular arc shape.

3. Epitaxially form a low-doped N region along the bottom and sidewalls of the trench, that is, the N- region, and ion-implant P-type impurities into the bottom of the trench at 0 degrees to compensate for the low-doped N region at the bottom of the trench to obtain a low-doped N region. Intermediate layer 4.

4. The P-type semiconductor pillar region 5 is epitaxially formed in the N- region, and the surface is planarized by chemical mechanical planarization CMP. At this time, the N-type epitaxial layers on both sides of the P-type semiconductor pillar region 5 become the N-type semiconductor doped pillar region 3, and a P pillar and an N pillar are obtained.

5. A gate trench is formed on the P-type semiconductor pillar region 5 by processes such as growing a hard mask, coating photoresist 13, exposing, developing, and etching.

6. A pre-oxide layer is grown in the gate trench, and the gate dielectric layer 10 is thermally grown after etching.

7. A polysilicon gate is deposited in the gate trench, and the excess polysilicon and oxide layer on the surface of the silicon wafer are removed to form a polysilicon gate electrode 9. At this time, all sides and bottom surfaces of the polysilicon gate electrode 9 are surrounded by the gate dielectric layer 10.

8. A P-type semiconductor base region 6, that is, a Pbody region, is formed over the N-type semiconductor doped pillar region 3 by self-aligned implantation.

9. A heavily doped N-type semiconductor doped source region 7 is formed on the P-type semiconductor base region 6 by photolithography and ion implantation.

10. An insulating dielectric layer 11 is deposited on the surface of the device, a contact hole is formed by etching over the P-type semiconductor base region 6 and ion implantation is performed, and a heavily doped P-type semiconductor doped contact region 8 is formed on the P-type semiconductor base region 6 .

11. The metallized source electrode 12 is formed by sputtering a conductive metal and a front side metal layer in the contact hole and on the surface of the insulating layer.

12. The substrate is thinned, and the backside metal layer is sputtered or evaporated to form a metallized drain electrode 1 .

As a preferred manner, the low doping is doping with an impurity concentration level of 5e13 cm ^-3 and below, and the heavy doping is doping with an impurity concentration level greater than 1e18 cm ^-3 .

In the above process flow, the width of the deep groove etching is larger than the width of the actually formed P pillar. Therefore, the aspect ratio of the trench is reduced, the difficulty of etching and the difficulty of epitaxial filling are reduced, and it is beneficial to the manufacture of extremely small-sized devices while improving the performance of the device.

The working principle of the present invention will be described in detail below with reference to Embodiment 1. In most areas of the superjunction withstand voltage layer, the lines of electric force emitted by the ionized donor of the N-column all point to the ionized acceptor of the P-column. In this region, the longitudinal component of the charge field is zero and only the lateral component; only when the N-column is close to the Pbody In the part of the region, a part of the ionized donor lines of electric force directed to the Pbody region, also in the part of the P column close to the N+ substrate, a part of the ionized acceptor is affected by the bottom N+ drain region, resulting in a longitudinal component of the charge field. Therefore, electric field peaks will be generated at the interface between the N pillar and the Pbody region and the interface between the P pillar and the N+ drain region, and the electric field peak is determined by the longitudinal component of the electric field. Meanwhile, the electric field peak appears at the junction due to the interaction between the N-pillar and the P-pillar, which is generated by the transverse electric field component. Judging the breakdown condition of the device is that the integral of the ionization rate along any line of electric force is 1, then the breakdown of the device may occur at the position with the largest longitudinal electric field or the position with the largest transverse electric field. Therefore, in the case of higher concentration doping of the P and N pillars, the breakdown voltage of the superjunction device is also limited by the peak lateral electric field. Studies have shown that to ensure that no lateral breakdown occurs, the widths of the N-column region and the P-column region need to satisfy the following formulas respectively:

为半导体介电常数，Ec表示电场。where _ND and W _N are the _doping concentration and width of the N _- column region, respectively, NA and WP are the doping concentration and width of the N-column region, respectively, q is the elemental charge,

is the semiconductor dielectric constant, and Ec represents the electric field.

It can be seen that in order to increase the doping concentration, the widths of the P and N columns must be reduced. For example, to increase the doping concentration of the N column to more than 5e13cm ^-3 , it is necessary to reduce its width to less than 2μm. For 600V superjunction devices, the P/N column depth is usually more than 30μm, so the aspect ratio of the trench will reach more than 15:1. This creates great technological difficulties for trenching and epitaxial filling.

Based on the superjunction MOSFET device, the present invention introduces a low-doped N-region or an intrinsic region between the P-column and the N-column. From the technical point of view, the width of the etched deep groove is larger than the width of the actually formed P column, thus reducing the aspect ratio of the trench and reducing the difficulty of etching and epitaxial filling. From the structure of the device, the mutual depletion of the PN pillars of the device of the present invention optimizes the lateral electric field of the device from a triangular distribution to a trapezoidal distribution due to the existence of the intermediate layer. As shown in FIG. 5 , when the critical breakdown electric field is the same, the integral area of the lateral electric field of the structure of the present invention is larger, which can improve the lateral breakdown voltage of the device. At the same time, according to Poisson's equation, the larger the electric field slope, the higher the doping concentration, and the N-column region of the present invention can adopt a higher doping concentration, which is beneficial to reduce the on-resistance of the device. When the total amount of impurities in the low-doped N-region and the N-column region as the intermediate layer is equal to the total amount of impurities in the P-column, the drift region can be fully depleted, and the vertical breakdown voltage of the device is not affected. Table 1 is a comparison of the basic electrical parameters of the existing super-junction MOSFET and the improved super-junction MOSFET of the present invention. It can be seen that under the same threshold voltage, the present invention has higher breakdown voltage and lower on-resistance.

Table 1

threshold voltage Breakdown voltage BV/V On-resistance Ron/mΩ*cm² conventional structure 3.84 710 12.0 The new structure of the present invention 3.84 722 10.6

When the superjunction MOSFET is in forward conduction, a high voltage is applied to the drain, and the PN column is in a reverse biased state. The expansion of the depletion region will squeeze a part of the current channel, causing the on-resistance of the device to increase. This is the JFET that exists in the superjunction MOSFET. effect. For superjunction devices with a cell pitch smaller than 5 μm, the effect of this effect is more serious due to the extremely small width of the PN pillars. In particular, the closer to the bottom region of the PN column, the greater the reverse voltage difference between the PN columns, the greater the width of the depletion region, and the greater the resistance of this region. In the new structure proposed by the present invention, the lateral dimension of the low-doped N-region near the bottom of the P-pillar is smaller, which is beneficial to reduce the width of the depletion region at the bottom of the PN-pillar and improve the influence of the JFET effect.

The embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above-mentioned specific embodiments. The above-mentioned specific embodiments are only illustrative rather than restrictive. Under the inspiration of the present invention, many modifications can be made without departing from the spirit of the present invention and the protection scope of the claims, which all belong to the protection of the present invention.

Claims (8)

1. A super-junction MOSFET with ultra-low specific conductance is characterized in that the super-junction MOSFET comprises a PN column structure formed by a first conduction type semiconductor doping column region (3) and a second conduction type semiconductor column region (5), the top of the first conduction type semiconductor doping column region (3) is provided with a second conduction type semiconductor base region (6), a groove type polycrystalline silicon gate electrode (9) is arranged above the second conduction type semiconductor column region (5), the lower surface of the polycrystalline silicon gate electrode (9) is lower than the lower surface of the second conduction type semiconductor base region (6), all side surfaces and the bottom surface of the polycrystalline silicon gate electrode (9) are surrounded by a gate dielectric layer (10), the top surface and a metalized source electrode (12) are isolated by an insulating dielectric layer (11), a low-doped semiconductor intermediate layer (4) is arranged between the first conduction type semiconductor doping column region (3) and the second conduction type semiconductor column region (5), the low doping means that the doping concentration is lower than that of the PN column, the semiconductor intermediate layer (4) is located below the second conductive type semiconductor base region (6), the top of the semiconductor intermediate layer (4) wraps the corner of the bottom of the gate dielectric layer (10), and the lateral size of the semiconductor intermediate layer (4) is smaller from top to bottom and is closer to the bottom of the second conductive type semiconductor column region (5).

2. The super-junction MOSFET with ultra-low specific conductivity according to claim 1, wherein the semiconductor intermediate layer (4) is a low-doped first conductivity type semiconductor layer or an intrinsic layer.

3. An ultra-low-conductivity superjunction MOSFET according to claim 2, wherein the total amount of impurities in the first conductivity type semiconductor doped column region (3) and the semiconductor interlayer (4) of the first conductivity type semiconductor is equal to the total amount of impurities in the second conductivity type semiconductor column region (5).

4. The super-junction MOSFET of claim 1, wherein the cell pitch of the super-junction MOSFET is less than 5 μm, and the doping concentration of the first conductivity type semiconductor pillar region (3) and the second conductivity type semiconductor pillar region (5) is 5e15cm or more^-3The lateral dimension is less than or equal to 2 mu m, the doping concentration of the semiconductor intermediate layer (4) is more than 2 orders of magnitude lower than the doping concentrations of the first conduction type semiconductor column region (3) and the second conduction type semiconductor column region (5), and the lateral dimension is less than or equal to 0.5 mu m.

5. The super junction MOSFET of claim 1, wherein the first type of conductivity semiconductor is a P-type semiconductor and the second type of conductivity semiconductor is an N-type semiconductor; or the first type conductivity semiconductor is an N-type semiconductor, and the second type conductivity semiconductor is a P-type semiconductor.

6. A manufacturing method of a super-junction MOSFET with ultra-low specific conductance is characterized in that a trenching filling process is adopted to manufacture the super-junction MOSFET with the low-doped middle layer between the PN columns according to any one of claims 1 to 5.

7. The manufacturing method of the super-junction MOSFET with ultra-low specific conductance as claimed in claim 6, wherein the trench filling process is used for preparing the super-junction MOSFET with the semiconductor intermediate layer (4), and comprises the following steps:

1) the super junction MOSFET is provided with a heavily doped first conduction type semiconductor doped substrate (2), and a first conduction type epitaxial layer is grown on the first conduction type semiconductor doped substrate (2);

2) etching the first conductive type epitaxial layer to form a deep groove, wherein the width of the deep groove is larger than that of the second conductive type semiconductor column region (5), and the bottom of the groove is arc-shaped by adjusting etching process parameters;

3) epitaxially forming a low-doped first conductive type region along the bottom and the side wall of the groove, and implanting second conductive type impurities into the bottom of the groove at 0 ℃ to compensate the low-doped first conductive type region at the bottom of the groove to obtain a low-doped middle layer (4);

4) epitaxially depositing to form a second conductive type semiconductor column region (5), and performing surface planarization by CMP;

5) forming a gate trench over the second conductivity type semiconductor pillar region (5);

6) growing a pre-oxidation layer in the grid groove, and thermally growing a grid dielectric layer (10) after etching;

7) depositing a polysilicon gate in the gate trench, and removing redundant polysilicon and an oxide layer on the surface of the silicon wafer to form a polysilicon gate electrode (9);

8) forming a second conductive type semiconductor base region (6) on the top of the first conductive type semiconductor doped column region (3) by adopting self-alignment injection;

9) forming a heavily doped first conductive type semiconductor doping source region (7) on the second conductive type semiconductor base region (6) through photoetching and ion implantation;

10) depositing an insulating medium layer (11) on the surface of the device, etching to form a contact hole, performing ion implantation, and forming a heavily doped second conductive type semiconductor doped contact region (8) adjacent to the first conductive type semiconductor doped source region (7);

11) sputtering conductive metal and a front metal layer in the contact hole and on the surface of the insulating layer of the device to form a metalized source electrode (12);

12) and thinning the substrate, and sputtering or evaporating the back metal layer to form the metalized drain electrode (1).

8. The method of claim 7, wherein the low doping is an impurity concentration of 5e13cm^-3And a heavy doping with an impurity concentration order of magnitude greater than 1e18cm^-3Doping of (3).

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