CN114461567A - Data processing equipment - Google Patents
Data processing equipment Download PDFInfo
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- CN114461567A CN114461567A CN202210198064.1A CN202210198064A CN114461567A CN 114461567 A CN114461567 A CN 114461567A CN 202210198064 A CN202210198064 A CN 202210198064A CN 114461567 A CN114461567 A CN 114461567A
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- 238000006243 chemical reaction Methods 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 6
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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Abstract
The invention discloses a data processing device, which aims to save the number of pins on a logic processing chip, wherein a plurality of parallel-serial chips can be connected through a first serial port of the logic processing chip, and a plurality of serial-parallel chips are connected through a second serial port, so that input data of a plurality of input interfaces provided by the parallel-serial chips can be input into the logic processing chip through the first serial port, the logic processing chip can also output a large amount of data to a specified output interface through the second serial port, and the parallel-serial chips and the serial-parallel chips have the characteristics of small volume and low cost, so that the cost is saved and the volume of the data processing device is controlled while the IO number of the data processing device is expanded.
Description
Technical Field
The invention relates to the field of chips, in particular to data processing equipment.
Background
In the big data era, various data processing devices (e.g., Programmable Logic Controllers (PLCs) and the like) exist, and at present, many data processing devices have a great demand for input interfaces and output interfaces, but the number of the input interfaces and the output interfaces that can be provided by a Logic processing chip (used for performing Logic processing on data) in the data processing device is limited, and how to extend the number of the input/output interfaces IO of the data processing device with low cost and small space is an urgent technical problem to be solved.
Therefore, how to provide a solution to the above technical problems is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide data processing equipment, and the parallel-serial chip and the serial-parallel chip have the characteristics of small volume and low cost, so that the cost is saved and the volume of the data processing equipment is controlled while the IO number of the data processing equipment is expanded.
To solve the above technical problem, the present invention provides a data processing apparatus, comprising:
the main control device is used for sending the data to be processed to the logic processing chip;
the logic processing chip is connected with the main control device and used for providing a plurality of input interfaces and a plurality of output interfaces, carrying out specified logic processing on the data to be processed and then sending the data to the specified output interfaces, and carrying out specified logic processing on the data received from the input interfaces and then sending the data to the specified main control device or the specified output interfaces;
the parallel-serial chips are connected in series with each other, and one ends of the parallel-serial chips are connected with the first serial port of the logic processing chip, and are used for converting parallel data input from a plurality of input interfaces provided by the parallel-serial chips into serial data and then sending the serial data to the logic processing chip;
and the serial-parallel conversion chips are connected in series with each other, and one ends of the serial-parallel conversion chips are connected with the second serial port of the logic processing chip and are used for converting the serial data sent by the logic processing chip into parallel data and outputting the parallel data through a plurality of output interfaces provided by the logic processing chip.
Preferably, the data processing apparatus further comprises:
and the level setting circuit is connected with the input interface provided by the parallel-serial chip closest to the logic processing chip and is used for setting the level combination of each connected input interface as a preset combination so as to determine the total number of the input interfaces provided by the parallel-serial chip and the total number of the output interfaces provided by the serial-parallel chip through the preset combination.
Preferably, the level setting circuit includes a level pull-up circuit and a level pull-down circuit.
Preferably, the master control device is an ARM processor.
Preferably, the logic processing chip is a field programmable gate array FPGA or a complex programmable logic device CPLD.
Preferably, the first serial port and the second serial port are of the same type.
Preferably, the first serial port and the second serial port are both serial peripheral interface SPI interfaces.
Preferably, the data processing device is a programmable logic controller PLC.
The invention provides a data processing device, in order to save the number of pins on a logic processing chip, a plurality of parallel-serial chips can be connected through a first serial port of the logic processing chip, and a plurality of serial-parallel chips are connected through a second serial port, so that input data of a plurality of input interfaces provided by the parallel-serial chips can be input into the logic processing chip through the first serial port, the logic processing chip can also output a large amount of data to a specified output interface through the second serial port, and the parallel-serial chips and the serial-parallel chips have the characteristics of small volume and low cost, so that the cost is saved and the volume of the data processing device is controlled while the IO number of the data processing device is expanded.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a data processing apparatus according to the present invention;
FIG. 2 is a schematic diagram of another data processing apparatus according to the present invention;
FIG. 3 is a schematic diagram of a parallel-serial chip according to the present invention;
fig. 4 is a schematic wiring diagram of a serial-to-parallel chip according to the present invention.
Detailed Description
The core of the invention is to provide a data processing device, because the parallel-serial chip and the serial-parallel chip have the characteristics of small volume and low cost, the application expands the IO number of the data processing device, saves the cost and controls the volume of the data processing device.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a data processing apparatus provided in the present invention, the data processing apparatus including:
the main control device 1 is used for sending data to be processed to the logic processing chip 2;
the logic processing chip 2 is connected with the main control device 1 and is used for providing a plurality of input interfaces and a plurality of output interfaces, carrying out appointed logic processing on data to be processed and then sending the data to the appointed output interfaces, carrying out appointed logic processing on the data received from the input interfaces and then sending the data to the appointed main control device 1 or the output interfaces;
the plurality of parallel-serial chips 3 are connected in series with each other, and one end of each parallel-serial chip is connected with the first serial port of the logic processing chip 2, and are used for converting parallel data input from a plurality of input interfaces provided by the plurality of parallel-serial chips into serial data and then sending the serial data to the logic processing chip 2;
and the serial-parallel chips 4 are connected in series with each other, and one ends of the serial-parallel chips are connected with the second serial port of the logic processing chip 2, and are used for converting the serial data sent by the logic processing chip 2 into parallel data and outputting the parallel data through a plurality of output interfaces provided by the serial-parallel chips.
In particular, in view of the technical problems in the background art as described above, in combination with the limited number of pins on the logic processing chip 2, therefore, the serial port is selected to be externally connected with the parallel-serial chip 3 and the serial-parallel chip 4, so that too many pins of the logic processing chip 2 are not occupied, a large amount of expansion of the IO interface can be completed, wherein, the data of a plurality of input interfaces provided by the parallel-serial chip 3 are parallel data, that is, the data of each input interface is independent, thus, it is equivalent to extending the input interface of the data processing device, and for the serial-parallel chip 4, the data processing device can receive serial data output by the logic processing chip 2, convert the serial data into parallel data and output the parallel data through a plurality of output interfaces provided by the logic processing chip, wherein the data of each output interface is independent, which is equivalent to the expansion of the output interface of the data processing device.
Specifically, the number of the parallel-serial chips 3 and the number of the serial-parallel chips 4 may be set independently, for example, 8 chips are set, and the embodiment of the present invention is not limited herein.
It is worth mentioning that the IO interface provided by the logic processing chip 2 may be a high-speed IO interface, and the IO interfaces provided by the parallel-serial chip 3 and the serial-parallel chip 4 may be low-speed IO interfaces, so that most of interface requirements can be met and stability is high.
The invention provides a data processing device, in order to save the number of pins on a logic processing chip, a plurality of parallel-serial chips can be connected through a first serial port of the logic processing chip, and a plurality of serial-parallel chips are connected through a second serial port, so that input data of a plurality of input interfaces provided by the parallel-serial chips can be input into the logic processing chip through the first serial port, the logic processing chip can also output a large amount of data to a specified output interface through the second serial port, and the parallel-serial chips and the serial-parallel chips have the characteristics of small volume and low cost, so that the cost is saved and the volume of the data processing device is controlled while the IO number of the data processing device is expanded.
For better explaining the embodiments of the present invention, please refer to fig. 2 to 4, fig. 2 is a schematic structural diagram of another data processing apparatus provided by the present invention; fig. 3 is a schematic wiring diagram of a parallel-serial chip 3 according to the present invention; fig. 4 is a schematic wiring diagram of a serial-to-parallel chip 4 provided by the present invention, based on the above embodiment:
as a preferred embodiment, the data processing apparatus further comprises:
and the level setting circuit 5 is connected with the input interface provided by the parallel-serial chip 3 closest to the logic processing chip 2 and is used for setting the level combination of the connected input interfaces to be a preset combination so as to determine the total number of the input interfaces provided by the parallel-serial chip 3 and the total number of the output interfaces provided by the serial-parallel chip 4 through the preset combination.
Specifically, in order to facilitate different data processing devices to know the number of IO interfaces expanded by the serial-to-parallel chip 4 and the parallel-to-serial chip 3, in the embodiment of the present invention, the level setting circuit 5 may further set the level combination of the input interfaces provided by the parallel-to-serial chip 3 closest to the logic processing chip 2 to be a preset combination, so that the logic processing chip 2 may determine the total number of the input interfaces provided by the parallel-to-serial chip 3 and the total number of the output interfaces provided by the serial-to-parallel chip 4 through the preset combination of the first several bits of the received serial data.
In fig. 3, the definition of each pin is as follows:
CLK: inputting a clock; CLK INH: data output enable; SH/LD: a data load bit; and (2) SER: inputting in series; a to H: inputting in parallel: and (3) QH: serially outputting; ' QH: the serial output is reversed.
In fig. 4, the definition of each pin is as follows:
SRCLK: inputting a clock; RCLK: a data latch clock; OE: outputting an enable; SRCLR: a reset pin; and (2) SER: inputting in series; QA to QH: and (3) parallel output: QH: serially outputting; ' QH: the serial output is reversed.
As a preferred embodiment, the level setting circuit 5 includes a level pull-up circuit and a level pull-down circuit.
Specifically, the level pull-up circuit and the level pull-down circuit have the advantages of small size, simple structure, low cost and the like.
Of course, the level setting circuit 5 may be in various types other than the form of the level pull-up circuit and the level pull-down circuit, and the embodiment of the present invention is not limited herein.
As a preferred embodiment, the master control device 1 is an ARM processor.
Specifically, the ARM processor has the advantages of being strong in processing capacity, small in size, low in cost and the like.
Of course, the master control apparatus 1 may be of various types other than the ARM processor, and the embodiment of the present invention is not limited herein.
As a preferred embodiment, the logic processing chip 2 is an FPGA (Field Programmable Gate Array) or a CPLD (Complex Programmable logic device).
Specifically, both the FPGA and the CPLD have the advantages of strong processing capability, small size, low cost, and the like.
Of course, the logic processing chip 2 may be of other types besides the FPGA and the CPLD, and the embodiment of the present invention is not limited herein.
In a preferred embodiment, the first serial port and the second serial port are of the same type.
Specifically, the first serial port and the second serial port are set to be of the same type, so that the working efficiency can be improved.
Of course, the first serial port and the second serial port may be set to different types, and the embodiment of the present invention is not limited herein.
As a preferred embodiment, the first Serial port and the second Serial port are both SPI (Serial Peripheral Interface) interfaces.
Specifically, the SPI interface has the advantages of high transmission speed, high stability and the like.
Of course, the first serial port and the second serial port may be of other types besides the SPI interface, such as an I2C interface, and the embodiment of the present invention is not limited herein.
In a preferred embodiment, the data processing device is a programmable logic controller PLC.
Specifically, the PLC has advantages of a strong data processing capability and a long life.
Of course, the data processing device may be of other types besides the PLC, and the embodiment of the present invention is not limited herein.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. A data processing apparatus, characterized by comprising:
the main control device is used for sending the data to be processed to the logic processing chip;
the logic processing chip is connected with the main control device and used for providing a plurality of input interfaces and a plurality of output interfaces, carrying out specified logic processing on the data to be processed and then sending the data to the specified output interfaces, and carrying out specified logic processing on the data received from the input interfaces and then sending the data to the specified main control device or the specified output interfaces;
the parallel-serial conversion chip is used for converting parallel data input from a plurality of input interfaces provided by the parallel-serial conversion chip into serial data and then sending the serial data to the logic processing chip;
and the serial-parallel conversion chips are connected in series with each other, and one ends of the serial-parallel conversion chips are connected with the second serial port of the logic processing chip and are used for converting the serial data sent by the logic processing chip into parallel data and outputting the parallel data through a plurality of output interfaces provided by the logic processing chip.
2. The data processing apparatus of claim 1, further comprising:
and the level setting circuit is connected with the input interface provided by the parallel-serial chip closest to the logic processing chip and is used for setting the level combination of each connected input interface as a preset combination so as to determine the total number of the input interfaces provided by the parallel-serial chip and the total number of the output interfaces provided by the serial-parallel chip through the preset combination.
3. The data processing device of claim 2, wherein the level setting circuit comprises a level pull-up circuit and a level pull-down circuit.
4. The data processing apparatus of claim 1, wherein the master device is an ARM processor.
5. The data processing device of claim 1, wherein the logic processing chip is a Field Programmable Gate Array (FPGA) or a Complex Programmable Logic Device (CPLD).
6. The data processing device of claim 1, wherein the first serial port and the second serial port are of the same type.
7. The data processing device of claim 6, wherein the first serial port and the second serial port are both SPI interfaces.
8. A data processing device as claimed in any one of claims 1 to 7, characterized in that the data processing device is a programmable logic controller, PLC.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210198064.1A CN114461567B (en) | 2022-03-01 | 2022-03-01 | Data processing equipment |
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| CN202210198064.1A CN114461567B (en) | 2022-03-01 | 2022-03-01 | Data processing equipment |
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| JPH1075183A (en) * | 1996-08-29 | 1998-03-17 | Nippon Telegr & Teleph Corp <Ntt> | Serial-parallel data conversion circuit |
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| CN213581791U (en) * | 2020-10-28 | 2021-06-29 | 北京宏光星宇科技发展有限公司 | Circuit for simulating SPI interface to expand input and output interfaces |
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2022
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