CN114449774B - Manufacturing process of conductive circuit - Google Patents
Manufacturing process of conductive circuit Download PDFInfo
- Publication number
- CN114449774B CN114449774B CN202210213231.5A CN202210213231A CN114449774B CN 114449774 B CN114449774 B CN 114449774B CN 202210213231 A CN202210213231 A CN 202210213231A CN 114449774 B CN114449774 B CN 114449774B
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- CN
- China
- Prior art keywords
- layer
- conductive
- area
- substrate
- waste
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000002699 waste material Substances 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000002955 isolation Methods 0.000 claims abstract description 23
- 238000005520 cutting process Methods 0.000 claims abstract description 16
- 238000003825 pressing Methods 0.000 claims abstract description 3
- 239000010410 layer Substances 0.000 claims description 79
- 238000000034 method Methods 0.000 claims description 9
- 239000007822 coupling agent Substances 0.000 claims description 8
- 238000007599 discharging Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 8
- 239000011259 mixed solution Substances 0.000 claims description 6
- 239000003960 organic solvent Substances 0.000 claims description 6
- 238000007639 printing Methods 0.000 claims description 4
- 239000012964 benzotriazole Substances 0.000 claims description 3
- 239000011241 protective layer Substances 0.000 claims description 3
- 230000003014 reinforcing effect Effects 0.000 claims description 3
- 238000005507 spraying Methods 0.000 claims description 3
- 238000005476 soldering Methods 0.000 claims description 2
- 125000003354 benzotriazolyl group Chemical group N1N=NC2=C1C=CC=C2* 0.000 claims 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 239000011889 copper foil Substances 0.000 description 5
- 229920000139 polyethylene terephthalate Polymers 0.000 description 5
- 239000005020 polyethylene terephthalate Substances 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 239000011888 foil Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- QRUDEWIWKLJBPS-UHFFFAOYSA-N benzotriazole Chemical compound C1=CC=C2N[N][N]C2=C1 QRUDEWIWKLJBPS-UHFFFAOYSA-N 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 239000003921 oil Substances 0.000 description 2
- -1 polyethylene terephthalate Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 150000004841 phenylimidazoles Chemical class 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000003755 preservative agent Substances 0.000 description 1
- 239000003223 protective agent Substances 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
The invention provides a manufacturing process of a conductive circuit, which comprises the following steps: a1, providing a substrate, and planning a wiring area and a waste discharge area on the surface of the substrate; a2, covering an isolation layer on the surface of the waste discharge area of the substrate; a3, pressing the conductive layer on the surface of the substrate; a4, cutting out the conductive layer into a circuit positioned on the surface of the wiring area and waste positioned on the surface of the waste discharge area through die cutting; and A5, removing waste materials to obtain the conductive line positioned in the wiring area. The isolating layer is covered on the surface of the waste discharge area, so that the binding force of the conducting layer in the waste discharge area is smaller than that in the wiring area, the conducting layer is disconnected after die cutting, waste materials can be uniformly discharged in a negative pressure sucking and removing mode due to the difference of the binding force, the waste discharge is easy and high in efficiency, a circuit positioned on the surface of the wiring area cannot be influenced, and the precision is well ensured.
Description
Technical Field
The invention relates to a manufacturing process of a conductive circuit.
Background
The integrated circuit (INTEGRATED CIRCUIT) is a microelectronic device or component. The components such as transistors, resistors, capacitors, inductors and the like required in a circuit and wiring are interconnected together by adopting a certain process and are manufactured on a small or a few small semiconductor wafers or dielectric substrates to form a microstructure with required circuit functions, such as a circuit board, an RFID tag and the like. Before the electronic components are assembled, the conductive traces need to be laid out. In the prior art, the manufacturing process of the conductive circuit comprises wet etching, printing, electroplating, vacuum plating, die cutting and the like. In the die-cutting preparation process, the whole conducting layer (such as a copper foil layer) is die-cut into a circuit pattern, and then waste is discharged in a waste discharge mode, but the defects of difficult waste discharge, poor precision and the like are common.
Disclosure of Invention
Therefore, the invention provides a manufacturing process of a conductive circuit based on a die cutting process, which can well solve the problems of difficult waste discharge and poor precision.
In order to achieve the above purpose, the technical scheme provided by the invention is as follows:
a manufacturing process of a conductive circuit comprises the following steps:
A1, providing a substrate, and planning a wiring area and a waste discharge area on the surface of the substrate;
a2, covering an isolation layer on the surface of the waste discharge area of the substrate;
A3, pressing the conductive layer on the surface of the substrate;
a4, cutting out the conductive layer into a circuit positioned on the surface of the wiring area and waste positioned on the surface of the waste discharge area through die cutting;
and A5, removing waste materials to obtain the conductive line positioned in the wiring area.
Further, in step A2, the surface of the wiring area of the substrate is an exposed surface, and in step A3, the conductive layer is directly pressed onto the surface of the wiring area of the substrate and the surface of the isolation layer located in the waste discharging area.
Further, in step A2, a coupling agent layer is covered on the wiring area of the substrate, and in step A3, the conductive layer is pressed on the surface of the coupling agent layer in the wiring area and the surface of the isolation layer in the waste disposal area.
Further, the isolation layer is an OSP layer, specifically, the OSP is Organic Solderability Preservatives, which is an organic solder mask, also called copper-protecting agent.
Further, the OSP layer is made of benzotriazole.
In the step A2, the OSP material is dissolved in an organic solvent to obtain a mixed solution, the mixed solution is covered on the surface of the waste discharge area in a printing or spraying mode, and the organic solvent is volatilized and dried to obtain the isolation layer.
Further, the conductive layer in the step A3 is a conductive film layer of copper foil, aluminum foil or other conductive film materials, and a reinforcing layer is added at the bottom of the conductive film layer.
Further, in step A5, the waste is removed by suction under negative pressure.
Further, step A5 is followed by step A6 of covering the conductive trace in the wiring area with a protective layer.
The technical scheme provided by the invention has the following beneficial effects:
The isolating layer is covered on the surface of the waste discharge area, so that the binding force of the conducting layer in the waste discharge area is smaller than that in the wiring area, the conducting layer is disconnected after die cutting, waste materials can be uniformly discharged in a negative pressure sucking and removing mode due to the difference of the binding force, the waste discharge is easy and high in efficiency, a circuit positioned on the surface of the wiring area cannot be influenced, and the precision is well ensured.
Drawings
FIG. 1 is a flow chart of a process for manufacturing a conductive line according to a first embodiment;
FIG. 2 is a schematic view showing the appearance of a substrate according to the first embodiment;
FIG. 3 is a partial sectional view showing the structure of the product obtained in the step A2 in the first embodiment;
FIG. 4 is a partial sectional view showing the structure of the product obtained in the step A3 in the first embodiment;
FIG. 5 is a partial sectional view showing the structure of the product obtained in the step A4 in the first embodiment;
Fig. 6 is a partial sectional view showing the structure of the product obtained in step A5 in the first embodiment.
Detailed Description
For further illustration of the various embodiments, the invention is provided with the accompanying drawings. The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate embodiments and together with the description, serve to explain the principles of the embodiments. With reference to these matters, one of ordinary skill in the art will understand other possible embodiments and advantages of the present invention. The components in the figures are not drawn to scale and like reference numerals are generally used to designate like components.
The invention will now be further described with reference to the drawings and detailed description.
Example 1
Referring to fig. 1, the present embodiment provides a process for manufacturing a conductive line, including the following steps:
a1, as shown in FIG. 2, providing a substrate 10, and planning a wiring area 101 and a waste discharge area 102 on the surface of the substrate 10; in the figure, the ring positions are set as wiring areas 101, and the remaining positions are waste discharge areas 102.
A2, covering an isolation layer 20 on the surface of the waste discharge area 102 of the substrate 10, as shown in FIG. 3;
Specifically, in this embodiment, the surface of the wiring area 101 of the substrate 10 is exposed, so as to form an exposed surface;
A3, as shown in FIG. 4, a conductive layer 30 (specifically, a copper foil layer in the present embodiment) is laminated on the surface of the substrate 10;
Specifically, the conductive layer 30 is directly pressed onto the surface of the wiring area 101 of the substrate 10 and the surface of the isolation layer 20 located in the waste discharging area 102.
A4, as shown in fig. 5, cutting out the conductive layer 30 by die cutting to form a line 31 on the surface of the wiring area 101 and a scrap 32 on the surface of the scrap discharging area 102; specifically, the die cutting can be selected from laser cutting, cutting die cutting and the like in the prior art.
Thus, the surface of the waste discharging area 102 is covered with the isolation layer 20, so that the bonding force of the conductive layer 30 in the waste discharging area 102 is smaller than that in the wiring area 101.
A5, as shown in FIG. 6, the waste 32 is discharged to obtain a conductive line in the wiring area 101, and the line 31 is the conductive line.
Due to the difference of binding force, the waste 32 is discharged more easily, the circuit 31 on the surface of the wiring area 101 is not affected, and the precision is well ensured. Specifically, in step A5, the waste 32 is uniformly removed by negative pressure suction, so that the efficiency is higher. Of course, other means of discharging waste are possible.
Specifically, in the present embodiment, the substrate 10 is a structure that can form adhesion with the conductive layer 30 during the lamination process, such as a PET substrate. Of course, if the substrate 10 is difficult to directly form an adhesive structure with the conductive layer 30, such as a ceramic substrate, a layer of adhesive may be added on the surface of the substrate 10 or the bottom of the conductive layer 30 to facilitate press-bonding.
Further, in step A3, if a conductive film layer is used as the conductive layer, for example, a copper foil, an aluminum foil or other conductive film material with a thickness of 18 μm, the strength is obviously insufficient, and the conductive film layer is basically broken by pulling by hand; therefore, in this case, a reinforcing layer, such as a PET layer having a thickness of 10 μm, may be added to the bottom of the conductive film layer, i.e., aluminum foil (or copper foil) and PET are processed by a composite process to increase strength.
Specifically, the isolation layer 20 is an OSP layer, specifically, in step A2, the OSP material is dissolved in an organic solvent to obtain a mixed solution, and then the mixed solution is covered on the surface of the waste discharge area by printing or spraying, and the organic solvent is volatilized and dried to obtain the isolation layer. The OSP layer can be formed to have a nano-scale thickness, generally 0.2-0.5 microns, and the solvent is solid after volatilization, so that the formed circuit is clearer.
Meanwhile, after the conductive circuit is formed, the residual OSP layer can be volatilized or sublimated and removed through the subsequent normal baking or reflow soldering heating process, and no additional removing step is needed; after removal, no isolation is performed, and a resin layer can be added on the circuit 31 for secondary lamination or glue can be applied for protection and reinforcement. More preferably, the OSP layer is made of benzotriazole, can sublimate at 98-100 ℃, is easier to remove, and has lower removal temperature, especially lower than the long-term use temperature of the common material PET (polyethylene terephthalate) of the RFID tag, and the long-term use temperature is lower than 120 ℃. Of course, in other embodiments, other layers such as alkyl imidazoles or phenyl imidazoles may be used for the OSP layer. Besides the OSP layer, other silicon oil layers such as silicon oil layers made of materials can be adopted, and isolation can be realized; but has poor effect, i.e. after step A5, an additional step of removing the isolation layer is required to remove it.
Further, step A5 is followed by step A6 of covering the conductive trace in the wiring area with a protective layer. In this way, the line 31 can be effectively protected. Of course, this is not limiting in other embodiments.
Example two
The manufacturing process of the conductive circuit provided in the present embodiment is substantially the same as that provided in the first embodiment, and is different in that: in step A2 of the present embodiment, a coupling agent layer is further covered on the wiring area of the substrate, and in step A3, the conductive layer is pressed onto the surface of the coupling agent layer in the wiring area and the surface of the isolation layer in the waste disposal area. In the embodiment, the coupling agent layer is additionally arranged in the wiring area, and the coupling agent can further promote the combination of the conductive layer and the surface of the wiring area, so that the combination is firmer.
While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (5)
1. The manufacturing process of the conductive circuit is characterized by comprising the following steps of:
A1, providing a substrate, and planning a wiring area and a waste discharge area on the surface of the substrate;
a2, covering an isolation layer on the surface of the waste discharge area of the substrate; the isolation layer is an OSP layer, the material of the OSP layer is benzotriazole, and the thickness of the isolation layer is 0.2-0.5 microns;
In the step A2, the OSP material is dissolved in an organic solvent to obtain a mixed solution, the mixed solution is covered on the surface of a waste discharge area in a printing or spraying mode, and the organic solvent is volatilized and dried to obtain the isolation layer;
A3, pressing the conductive layer on the surface of the substrate;
a4, cutting out the conductive layer into a circuit positioned on the surface of the wiring area and waste positioned on the surface of the waste discharge area through die cutting;
A5, removing waste materials on the isolation layer in a negative pressure sucking mode to obtain a conductive line positioned in a wiring area; after the conductive lines are formed, the isolation layer is volatilized or sublimated by baking or reflow soldering.
2. The process for manufacturing a conductive line according to claim 1, wherein: in step A2, the surface of the wiring area of the substrate is an exposed surface, and in step A3, the conductive layer is directly pressed onto the surface of the wiring area of the substrate and the surface of the isolation layer located in the waste discharging area.
3. The process for manufacturing a conductive line according to claim 1, wherein: in step A2, a coupling agent layer is covered on the wiring area of the substrate, and in step A3, the conductive layer is pressed on the surface of the coupling agent layer in the wiring area and the surface of the isolation layer in the waste discharging area.
4. The process for manufacturing a conductive line according to claim 1, wherein: step A5 is followed by step A6 of covering the conductive trace in the routing area with a protective layer.
5. The process for manufacturing a conductive line according to claim 1, wherein: in the step A3, the conductive layer is a conductive film layer, and a reinforcing layer is additionally arranged at the bottom of the conductive film layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210213231.5A CN114449774B (en) | 2022-02-28 | 2022-02-28 | Manufacturing process of conductive circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210213231.5A CN114449774B (en) | 2022-02-28 | 2022-02-28 | Manufacturing process of conductive circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114449774A CN114449774A (en) | 2022-05-06 |
| CN114449774B true CN114449774B (en) | 2024-07-30 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210213231.5A Active CN114449774B (en) | 2022-02-28 | 2022-02-28 | Manufacturing process of conductive circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114449774B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016120610A (en) * | 2014-12-24 | 2016-07-07 | サトーホールディングス株式会社 | Manufacturing apparatus and manufacturing method for perforated label continuum |
| CN112188745A (en) * | 2020-09-30 | 2021-01-05 | 深圳光韵达激光应用技术有限公司 | Die-cutting conductor circuit manufacturing process |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004335907A (en) * | 2003-05-12 | 2004-11-25 | Fuchigami Micro:Kk | Flexible embedding circuit board and manufacturing method thereof |
| CN101794186A (en) * | 2010-03-22 | 2010-08-04 | 牧东光电（苏州）有限公司 | Processing method for induction layers of capacitive touch panel |
| KR101125356B1 (en) * | 2011-03-25 | 2012-04-02 | 엘지이노텍 주식회사 | The printed circuit board and the method for manufacturing the same |
| WO2013133269A1 (en) * | 2012-03-09 | 2013-09-12 | 三井金属鉱業株式会社 | Method for manufacturing printed wiring board and copper foil for laser processing |
| CN103687344B (en) * | 2012-09-26 | 2016-08-24 | 宏启胜精密电子(秦皇岛)有限公司 | Circuit board manufacturing method |
| CN107911949A (en) * | 2017-11-06 | 2018-04-13 | 王国清 | A kind of wiring thin film board manufacturing method |
| JP2021111744A (en) * | 2020-01-15 | 2021-08-02 | 日本特殊陶業株式会社 | Manufacturing method for conductive layer, manufacturing method for wiring board and manufacturing method for heater device |
| CN111647362B (en) * | 2020-07-10 | 2024-11-08 | 捷邦精密科技股份有限公司 | Conductive double-sided adhesive component for electronic circuit board and production process thereof |
| CN113199556B (en) * | 2021-04-19 | 2023-03-21 | 麦格磁电科技（珠海）有限公司 | Multilayer material die cutting processing method |
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2022
- 2022-02-28 CN CN202210213231.5A patent/CN114449774B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016120610A (en) * | 2014-12-24 | 2016-07-07 | サトーホールディングス株式会社 | Manufacturing apparatus and manufacturing method for perforated label continuum |
| CN112188745A (en) * | 2020-09-30 | 2021-01-05 | 深圳光韵达激光应用技术有限公司 | Die-cutting conductor circuit manufacturing process |
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| CN114449774A (en) | 2022-05-06 |
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