CN114448442A - Analog-to-digital converter and analog-to-digital conversion method - Google Patents

Abstract

The present application discloses an analog-to-digital converter and an analog-to-digital conversion method. The analog-to-digital converter includes: an analog adder, which performs a subtraction operation on the analog input signal and the feedback signal to obtain an error signal; an integrator, which performs an integrating operation on the error signal to obtain an integrated signal; The sum of the integral signals is quantized to output an N-bit quantized signal; the delta modulator converts the N-bit quantized signal into an M-bit output signal according to historical values, where M and N are both non-zero natural numbers, and M is greater than N; and a digital-to-analog converter, connected between the delta modulator and the analog adder, for converting the M-bit output signal into an analog feedback signal and then sending it to the analog adder. The analog-to-digital converter can take into account the requirements of device stability and high signal-to-noise ratio at the same time.

Description

Analog-to-digital converter and analog-to-digital conversion method

technical field

The present invention relates to the technical field of electronic circuits, and more particularly, to an analog-to-digital converter and an analog-to-digital conversion method.

Background technique

With the rapid development of digital electronic technology, the application of various digital devices, especially various processors, has become more and more extensive, and has penetrated into almost all fields of the national economy. The processor can only process digital signals, and the result of the processing is still a digital quantity. The variables in nature are often analog quantities that change continuously, such as force, displacement, velocity, etc. These analog quantities must first be converted into voltage or current signals by sensors, and then converted into digital quantities before they can be sent to the processor for processing, which requires an analog-to-digital converter, that is, an analog-to-digital converter (ADC). The analog-to-digital converter has a very important position, and the improvement of the analog-to-digital converter has been the focus of the signal processing field for decades.

Traditional linear pulse code modulation (PCM) ADCs are limited by the manufacturing process and cannot achieve very high resolution. However, the ADC based on Delta-Sigma modulation technology can achieve high resolution (greater than 16 bits) under the existing process, and at the same time, it is easy to implement due to its simple structure. Low cost and high performance make Delta-Sigma modulation technology widely used.

Traditional Delta-Sigma modulators can have multiple integrators. If two integrators are connected in series, it is called a second-order Delta-Sigma modulator. Modulators of different orders have different effects on noise-shaping. The higher the order, the better the noise-shaping effect. However, the higher the order, the more difficult it is to design, and the overall stability of the modulator decreases.

Multi-bit analog-to-digital converter quantization and multi-bit digital-to-analog converter feedback can improve the signal-to-noise ratio of the signal within the bandwidth, thereby avoiding the complexity of using too many orders. However, the linearity of the design of the multi-bit analog-to-digital converter quantizer and the multi-bit feedback digital-to-analog converter also directly affects the performance of the whole system.

Therefore, it is desirable to provide an improved analog-to-digital switching device to reduce the order of the modulator, maintain the stability of the device, and meet the requirements of high signal-to-noise ratio design.

SUMMARY OF THE INVENTION

In view of the above problems, the purpose of the present invention is to provide an analog-to-digital converter and an analog-to-digital conversion method, so as to take into account the requirements of stability and high signal-to-noise ratio at the same time.

According to an aspect of the present invention, an analog-to-digital converter is provided, comprising:

An analog adder that performs a subtraction operation on the analog input signal and the feedback signal to obtain an error signal;

an integrator, which performs an integral operation on the error signal to obtain an integral signal;

a quantizer, which performs quantization processing on the sum of the analog input signal and the integral signal to output a quantized signal of N bits;

a delta modulator, converting the N-bit quantized signal into an M-bit output signal according to historical values, where M and N are both non-zero natural numbers, and M is greater than N; and

A digital-to-analog converter, connected between the delta modulator and the analog adder, is used for converting the M-bit output signal into an analog feedback signal and then sending it to the analog adder.

Optionally, the delta modulator includes:

A storage module for storing the M-bit output signal obtained in at least one historical period, and storing the N-bit quantized signal of at least one historical period, and according to the M-bit output signal obtained in at least one historical period and the N-bit quantized signal in the current cycle, determine the boundary of the N-bit quantized signal in the current cycle, and obtain the incremental boundary value in the current cycle, and the historical cycle is in the current cycle. the period before the current period;

a data processing module, performing quantization processing on the boundary value obtained by the storage module; and

The accumulation module is used to accumulate the N-bit quantized signal in the current cycle, the N-bit quantized signal of at least one historical period and the boundary value after quantization processing to obtain the M-bit quantized signal. output signal. Optionally, the delta modulator further includes:

A quantization out-of-bounds processing module, connected to the accumulation module, for judging whether the M-bit output signal is out-of-bounds after the accumulation module performs accumulation, and if it is out-of-bounds, then the M-bit output signal is subjected to out-of-bounds processing Then, it is fed back to the accumulating module, and the accumulating module outputs the M-bit output signal, and if the limit is not exceeded, the M-bit output signal is output.

Optionally, the integrator includes at least one integration module to perform at least one integration operation on the error signal,

When the number of the integration modules is multiple, the integration modules are sequentially connected in series to perform multiple integration operations on the error signal, thereby obtaining the integration signal.

Optionally, the integrator includes two integration modules, thereby forming a second-order modulator structure, where N is 4 and M is 12.

According to a second aspect of the present invention, an analog-to-digital conversion method is provided, comprising:

perform a subtraction operation on the analog input signal and the feedback signal to obtain an error signal;

performing an integral operation on the error signal to obtain an integral signal;

quantizing the sum of the analog input signal and the integral signal to output a quantized signal of N bits;

Converting the N-bit quantized signal into an M-bit output signal according to historical values, where both M and N are non-zero natural numbers, and M is greater than N; and

The M-bit output signal is converted into an analog feedback signal.

Optionally, converting the N-bit quantized signal into an M-bit output signal according to historical values includes:

According to the M-bit output signal obtained in at least one historical period and the N-bit quantized signal in the current period, determine the boundary of the N-bit quantized signal in the current period, and obtain the current period Boundary value of medium increment, the historical period is the period before the current period;

Judging the boundary of the N-bit quantized signal in the current cycle, and performing quantization processing on the boundary value; and

Accumulate the N-bit quantized signal in the current cycle, the N-bit quantized signal of at least one historical cycle, and the quantized boundary value to obtain the M-bit output signal.

Optionally, also include:

After the accumulation is performed, it is judged whether the output signal of the M bits is out of bounds, and if it is out of bounds, the output signal of the M bits is subjected to out-of-bounds processing, and then the quantization signal of the N bits in the current cycle is re-executed. and the step of accumulating the boundary value after the quantization process to obtain the M-bit output signal, and if the boundary value is not exceeded, the M-bit output signal is output.

Optionally, multiple integral operations are performed on the error signal to obtain the integral signal.

Optionally, two integral operations are performed on the error signal, N is set to 4, and M is set to 12.

The analog-to-digital converter and the analog-to-digital conversion method provided by the invention utilize the incremental modulator to predict the fine resolution within the N-bit unit quantization step size, and feed it back to the analog-to-digital converter, thereby improving the analog-to-digital converter. The overall performance index of the device, while ensuring the high performance of the device, simplifies the circuit, ensures the stability of the device, and meets the requirements of high signal-to-noise ratio design.

Description of drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

Fig. 1 shows the structural schematic diagram of the traditional Delta-Sigma modulator;

Figure 2 shows a schematic diagram of a conventional 1st-order 1-BIT Delta-Sigma modulator;

Figure 3 shows a schematic diagram of a conventional second-order 1-BIT Delta-Sigma modulator;

Figure 4 shows a schematic diagram of a conventional 3rd order 5-BIT Delta-Sigma modulator;

5 shows a schematic diagram of an analog-to-digital converter according to an embodiment of the present invention;

6 shows a block diagram of a delta modulator according to an embodiment of the present invention;

7 shows a schematic diagram of quantization of an analog-to-digital converter according to an embodiment of the present invention;

8 shows a flowchart of an analog-to-digital conversion method according to an embodiment of the present invention;

FIG. 9 shows a flowchart of a delta modulation process according to an embodiment of the present invention.

Detailed ways

The present invention will be described in more detail below with reference to the accompanying drawings. In the various figures, like elements are designated by like reference numerals. For the sake of clarity, various parts in the figures have not been drawn to scale. Additionally, some well-known parts may not be shown in the drawings.

It should be understood that A and B are connected/coupled in the embodiments of the present application, indicating that A and B can be connected in series or in parallel, or A and B pass through other devices, which are not limited in the embodiments of the present application.

The analog-to-digital converter is a converter that converts the analog quantity after being compared with the standard quantity (or reference quantity) into a discrete signal represented by a binary value, referred to as ADC or A/D converter.

An important parameter of the analog-to-digital converter is the conversion accuracy, which is usually expressed in the number of bits (BIT) of the output digital signal. The more bits of the digital signal that the converter can output accurately, the stronger the ability of the converter to distinguish the input signal, and the better the performance of the converter. Analog-to-digital conversion usually goes through four processes of sampling, holding, quantization and encoding. Among them, quantization divides the analog signal range into many discrete magnitudes and determines the magnitude of the input signal.

The analog-to-digital converter based on Delta-Sigma modulation technology can achieve high resolution under the traditional process. Therefore, the Delta-Sigma modulator is an important part of the analog-to-digital converter.

Figure 1 shows a schematic diagram of the structure of a traditional Delta-Sigma modulator. Figure 1 is a schematic diagram of the structure of a traditional Delta-Sigma modulator. The Delta-Sigma modulator 100 includes an analog adder 102 , an integrator 106 , a quantizer 108 , a feedback circuit 104 and a digital filter 110 . The quantizer 108 converts the analog signal Vin into a 1-bit digital stream, which is generally implemented by using a latched comparator; the feedback circuit 104 converts the 1-bit digital stream into an analog signal.

The role of the Delta-Sigma modulator is to convert the input analog signal Vin into serial data consisting of -1 and 1. After the output serial data is amplified by the feedback circuit 104, the difference is made with the input analog signal Vin, the error signal is sent to the integrator 106 for integration and accumulation, and the output of the integrator 106 is sent to the quantizer 108 to generate a new 1-bit data stream. When the sampling frequency is large enough, the average value of the 1-bit data stream output by the Delta-Sigma modulator 100 is equal to the average value of the input signal, that is, the 1-bit digital stream y(n) contains all the information of the input signal.

Figure 2 shows a schematic diagram of a conventional 1st order 1-BIT Delta-Sigma modulator. The first-order 1-BIT Delta-Sigma modulator 200 shown in FIG. 2 is similar to the Delta-Sigma modulator 100 shown in FIG. 1 , and the Delta-Sigma modulator 200 includes an analog adder 202 , an integrator 206 , and a quantizer 208 , the feedback circuit 204 and the digital filter 210. Specifically, the quantizer 108 is implemented by a latched comparator, which is a 1-BIT analog-to-digital converter, and the feedback circuit 204 is a 1-BIT analog-to-digital converter.

A traditional Delta-Sigma modulator may include multiple integrators (one in Figure 2), such as two integrators connected in series, it is called a second-order Delta-Sigma modulator. Modulators of different orders have different effects on noise-shaping. The higher the order, the better the noise-shaping effect. However, the higher the order, the more difficult the circuit design is, and the overall stability of the modulator decreases. Figure 3 shows a schematic diagram of a conventional 2nd order 1-BIT Delta-Sigma modulator. The Delta-Sigma modulator 300 includes a first analog adder 301 , a second analog adder 302 , a first integrator 305 , a second integrator 306 , a quantizer 308 , a feedback circuit 304 and a digital filter 310 .

At the same time, the tradition of 1-BIT's Delta-Sigma modulator is to use 1-BITADC and 1-DAC as a feedback path. Of course, multi-bit (Multi-Bit) ADCs and DACs can also be selected for quantization and feedback. Figure 4 shows a schematic diagram of a traditional third-order 5-BITDelta-Sigma modulator. The third-order 5-BITDelta-Sigma modulator 400 includes a first analog adder 401 , a second analog adder 403 , a second analog adder 405 , a first integrator 402 , a second integrator 404 , and a second integrator 406 , quantizer 407 and feedback circuit 408 .

However, the inventor of the present application found that the linearity of the design of the multi-bit ADC quantizer and the multi-bit feedback DAC will directly affect the performance of the entire system. To this end, an improved analog-to-digital converter and an analog-to-digital conversion method are provided to take into account the requirements of device stability and high signal-to-noise ratio.

Embodiments of the analog-to-digital converter and the analog-to-digital conversion method provided by the present application will be described below with reference to the accompanying drawings.

FIG. 5 shows a schematic diagram of an analog-to-digital converter according to an embodiment of the present invention. 6 shows a block diagram of a delta modulator according to an embodiment of the present invention. FIG. 7 shows a schematic diagram of quantization of an analog-to-digital converter according to an embodiment of the present invention.

As shown in FIG. 5 , the analog-to-digital converter 500 includes an analog adder 510 , an integrator 520 , a quantizer 530 , a delta modulator 540 , and a digital-to-analog converter 550 .

The input terminal of the analog adder 510 receives the analog input signal and the feedback signal, and is used for performing a subtraction operation on the analog input signal and the feedback signal to obtain an error signal.

The integrator 520 is connected to the output end of the analog adder 510, and is used for integrating the error signal to obtain an integrated signal. Optionally, the integrator 520 includes a plurality of integration modules 521, and the integration modules 521 are connected in series to perform multiple integration operations on the error signal to obtain an integration signal. For example, the integrator 520 includes two integrator modules 521 to form a second order modulator structure.

The quantizer 530 performs quantization processing on the sum of the analog input signal and the integrated signal to output an N-bit quantized signal. For example, the quantizer 530 is connected to the output of the analog adder 511, the input of the analog adder 511 is connected to the output of the integrator 520 and the analog input signal, respectively, and the quantizer 530 combines the sum of the analog input signal and the integrated signal with the reference The levels are compared to output an N-bit quantized signal, and the reference level is, for example, a reference ground level, that is, a zero level.

The delta modulator 540 is connected to the output end of the quantizer 530, and converts the N-bit quantized signal into an M-bit output signal according to historical values, where M and N are both non-zero natural numbers, and M is greater than N. That is, the high N-BIT of the digital-to-analog converter 550 is the value quantized by the quantizer 530 (ie the ADC quantized value), and the low M-N Bit is the quantized value obtained by the adaptive prediction by the delta modulator 540 (ie the DAC quantized value) ), therefore within the quantization interval of the analog-to-digital converter, a more refined output signal can be output. For details, please refer to the quantization schematic diagram shown in FIG. 7 , wherein the ADC quantization value refers to the quantization value output by the quantizer 530, and the DAC quantization value refers to the quantization value output by the quantizer 530. Quantization value predicted by delta modulator 540.

In some exemplary embodiments, integrator 520 includes two integrator modules 521, thereby forming a second order modulator structure. Experiments show that in the second-order modulator structure, if N is set to 4 and M is set to 12, a good performance index can be obtained, taking into account the good stability of the device and a high signal-to-noise ratio.

One end of the digital-to-analog converter 550 is connected to the output of the delta modulator 540 , and the other end is connected to the analog adder 510 for converting the M-bit output signal into an analog feedback signal and then sending it to the analog adder 510 .

As an example, as shown in FIG. 6 , the delta modulator 540 includes: a storage module 541 , a data processing module 542 and an accumulation module 543 .

The storage module 541 is used to store the M-bit output signal obtained in at least one historical period, and store the N-bit quantized signal of at least one historical period, and the storage module 541 stores the M-bit output signal in each historical period in the current period. As the historical value, according to the M-bit output signal obtained in at least one historical period and the N-bit quantized signal in the current period, determine the boundary of the N-bit quantized signal in the current period, and obtain the incremental boundary in the current period value, the historical period is the period before the current period. Increment refers to M-N bits of data predicted based on historical data.

The data processing module 542 is configured to perform quantization processing on the boundary value obtained by the storage module.

The accumulation module 543 is configured to accumulate the N-bit quantized signal in the current cycle, the N-bit quantized signal of at least one historical cycle and the boundary value after quantization processing to obtain an M-bit output signal.

In this example, the delta modulator 540 further includes a quantization out-of-bounds processing module 544, and the quantization out-of-bounds processing module 544 is connected to the accumulation module 543 for determining whether the M-bit output signal is out of bounds after the accumulation module 543 performs accumulation. , the M-bit output signal is fed back to the accumulating module 543 after being out-of-bounds processing, and the accumulating module 543 outputs the M-bit output signal.

Some examples of the analog-to-digital converter of the embodiment of the present invention are described above, however, the embodiment of the present invention is not limited thereto, and there may also be extensions and modifications in other manners.

For example, the aforementioned analog-to-digital converter may be a discrete device, or may be used as a circuit unit. In other implementations, the aforementioned ramp signal generating circuit may be packaged in a device.

At the same time, those of ordinary skill in the art can realize that, with regard to the structures and methods of each example described in conjunction with the embodiments disclosed herein, different configuration methods or adjustment methods can be used to implement each structure or a reasonable deformation of the structure to achieve all the structures and methods. described functionality, but such an implementation should not be considered beyond the scope of this application. Moreover, it should be understood that the connection relationships between the enlarged components in the foregoing embodiments of the present application are schematic examples, and do not impose any limitations on the embodiments of the present application.

FIG. 8 shows a flowchart of an analog-to-digital conversion method according to an embodiment of the present invention. This flowchart shown in Figure 8 is only an example and should not unduly limit the scope of the claims. Numerous variations, substitutions and modifications will be apparent to those skilled in the art. For example, the various steps shown in FIG. 8 may be added, removed, replaced, rearranged and repeated.

In step S101, a subtraction operation is performed on the analog input signal and the feedback signal to obtain an error signal.

In step S102, integral operation is performed on the error signal to obtain an integral signal. Optionally, multiple integral operations are performed on the error signal to obtain an integral signal.

In step S103, a quantization process is performed on the sum of the analog input signal and the integrated signal to output an N-bit quantized signal.

In step S104, the N-bit quantized signal is converted into an M-bit output signal according to the historical value, where both M and N are non-zero natural numbers, and M is greater than N. This step may be referred to as a "delta modulation process".

Optionally, two integral operations are performed on the error signal, N is set to 4, and M is set to 12.

In step S105, the M-bit output signal is converted into an analog feedback signal.

FIG. 9 shows a flowchart of a delta modulation process according to an embodiment of the present invention.

In step S1041, according to the M-bit output signal obtained in at least one historical period, and the N-bit quantized signal in the current period, determine the boundary of the N-bit quantized signal in the current period, and obtain the incremental value of the current period. Boundary value, the historical period is the period before the current period. In this example, if N is set to 4 and M is set to 12, the N-bit quantized signal in the current cycle can be divided into unit amount, 2x unit amount, 4x unit amount and 8x unit amount.

In step S1042, quantization processing is performed on the boundary value of the increment. Increment refers to M-N bits of data predicted based on historical data.

In step S1043, the N-bit quantized signal in the current cycle, the N-bit quantized signal of at least one historical cycle, and the boundary value after quantization processing are accumulated to obtain an M-bit output signal.

In step S1044, optionally, after the accumulation is performed, it is determined whether the output signal of M bits is out of bounds, if it is out of bounds, then step S1043 is repeatedly executed after the output signal of M bits is out of bounds to output the output signal of M bits , if not out of bounds, the output signal of M bits is output.

It should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any relationship between these entities or operations. any such actual relationship or sequence exists. Moreover, the terms "comprising", "comprising" or any other variation thereof are intended to encompass non-exclusive inclusion such that a process, method, article or device comprising a list of elements includes not only those elements, but also includes not explicitly listed or other elements inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element.

Embodiments in accordance with the present invention are described above, but these embodiments do not exhaust all the details and do not limit the invention to only the specific embodiments described. Obviously, many modifications and variations are possible in light of the above description. This specification selects and specifically describes these embodiments in order to better explain the principle and practical application of the present invention, so that those skilled in the art can make good use of the present invention and modifications based on the present invention. The present invention is to be limited only by the claims and their full scope and equivalents.

Claims (10)

1. an analog-to-digital converter, is characterized in that, comprises: An analog adder that performs a subtraction operation on the analog input signal and the feedback signal to obtain an error signal; an integrator, which performs an integral operation on the error signal to obtain an integral signal; a quantizer, performing quantization processing on the sum of the analog input signal and the integral signal to output a quantized signal of N bits; a delta modulator, converting the N-bit quantized signal into an M-bit output signal according to historical values, where M and N are both non-zero natural numbers, and M is greater than N; and A digital-to-analog converter, connected between the delta modulator and the analog adder, is used for converting the M-bit output signal into an analog feedback signal and then sending it to the analog adder. 2. The analog-to-digital converter of claim 1, wherein the delta modulator comprises: A storage module for storing the M-bit output signal obtained in at least one historical period, and storing the N-bit quantized signal of at least one historical period, and according to the M-bit output signal obtained in at least one historical period and the N-bit quantized signal in the current cycle, determine the boundary of the N-bit quantized signal in the current cycle, and obtain the incremental boundary value in the current cycle, and the historical cycle is in the current cycle. the period before the current period; a data processing module, performing quantization processing on the boundary value obtained by the storage module; and The accumulation module is used to accumulate the N-bit quantized signal in the current cycle, the N-bit quantized signal of at least one historical period and the boundary value after quantization processing to obtain the M-bit quantized signal. output signal. 3. The analog-to-digital converter according to claim 2, wherein the delta modulator further comprises: A quantization out-of-bounds processing module, connected to the accumulation module, for judging whether the M-bit output signal is out-of-bounds after the accumulation module performs accumulation, and if it is out-of-bounds, then the M-bit output signal is subjected to out-of-bounds processing Then, it is fed back to the accumulating module, and the accumulating module outputs the M-bit output signal, and if the limit is not exceeded, the M-bit output signal is output. 4. The analog-to-digital converter according to claim 1, wherein the integrator comprises at least one integration module to perform at least one integration operation on the error signal, When the number of the integration modules is multiple, the integration modules are sequentially connected in series to perform multiple integration operations on the error signal, thereby obtaining the integration signal. 5 . The analog-to-digital converter according to claim 1 , wherein the integrator comprises two integrating modules, thereby forming a second-order modulator structure, wherein N is 4 and M is 12. 6 . 6. an analog-to-digital conversion method, is characterized in that, comprises: perform a subtraction operation on the analog input signal and the feedback signal to obtain an error signal; performing an integral operation on the error signal to obtain an integral signal; quantizing the sum of the analog input signal and the integral signal to output a quantized signal of N bits; Converting the N-bit quantized signal into an M-bit output signal according to historical values, where both M and N are non-zero natural numbers, and M is greater than N; and The M-bit output signal is converted into an analog feedback signal. 7. analog-to-digital conversion method according to claim 6, is characterized in that, according to historical value, the quantization signal of described N position is converted into the output signal of M position comprises: According to the M-bit output signal obtained in at least one historical period and the N-bit quantized signal in the current period, determine the boundary of the N-bit quantized signal in the current period, and obtain the current period Boundary value of medium increment, the historical period is the period before the current period; quantizing the boundary value; and Accumulate the N-bit quantized signal in the current cycle, the N-bit quantized signal of at least one historical cycle, and the quantized boundary value to obtain the M-bit output signal. 8. analog-to-digital conversion method according to claim 7, is characterized in that, also comprises: After the accumulation is performed, it is judged whether the output signal of the M bits is out of bounds, and if it is out of bounds, the output signal of the M bits is subjected to out-of-bounds processing, and then the quantization signal of the N bits in the current cycle is re-executed. and the step of accumulating the boundary value after the quantization process to obtain the M-bit output signal, and if the boundary value is not exceeded, the M-bit output signal is output. 9 . The analog-to-digital conversion method according to claim 6 , wherein the integrated signal is obtained by performing multiple integration operations on the error signal. 10 . 10 . The analog-to-digital conversion method according to claim 6 , wherein two integral operations are performed on the error signal, N is set to 4, and M is set to 12. 11 .

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