CN114447898B - Current limiting circuit and electric equipment with same - Google Patents
Current limiting circuit and electric equipment with same Download PDFInfo
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- CN114447898B CN114447898B CN202210093609.2A CN202210093609A CN114447898B CN 114447898 B CN114447898 B CN 114447898B CN 202210093609 A CN202210093609 A CN 202210093609A CN 114447898 B CN114447898 B CN 114447898B
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- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
- H02H9/025—Current limitation using field effect transistors
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Abstract
The invention discloses a current limiting circuit and electric equipment with the same, wherein the current limiting circuit comprises a current input end, a mirror image circuit and an adjusting circuit which are connected in sequence; the mirror circuit comprises a first field effect transistor and a second field effect transistor, wherein the grid electrodes of the first field effect transistor and the second field effect transistor are connected with each other; the input side of the regulating circuit is connected with the source electrode of the second field effect transistor and the reference voltage, the output side of the regulating circuit is connected with the grid electrode of the first field effect transistor, and the regulating circuit is configured to control the level of the grid electrode of the first field effect transistor according to the output of the source electrode of the second field effect transistor and the reference voltage; the current limiting circuit further comprises a compensation circuit connected with the grid electrode of the second field effect transistor and configured to output a compensation voltage, wherein the value of the compensation voltage is equal to the value of the reference voltage. The current limiting circuit provided by the invention can control errors in the current limiting process, and achieves the technical effects of considering the common applicability of cost, structure and current limiting.
Description
Technical Field
The invention relates to the technical field of electronic information, in particular to a current limiting circuit and electric equipment with the same.
Background
In the prior art, the circuit and the device for realizing current limitation and overcurrent protection often copy the current of the power tube through the sampling tube and output the current to the comparator, and control the power tube and the sampling tube by using the comparison result of the comparator and the reference voltage so as to play the effects of overcurrent protection and current limitation. However, due to the existence of the reference voltage, the voltage difference between the grid electrode and the source electrode of the sampling tube and the power tube is often caused, the generated voltage difference easily causes the system to be out of order, and in the extreme case, the error is about 30%, so that the expected effect cannot be achieved. If the power tube and the sampling tube are replaced by the P-channel transistor, although the deviation can be improved to a certain extent, in order to realize the basic function, a mask layer and a high-low voltage conversion circuit are needed to be added for the P-channel transistor, so that the cost and the complexity of the circuit are increased, and the current limiting problem of the power tube when the power tube works in a linear region cannot be solved even if the circuit system is adjusted.
Disclosure of Invention
One of the purposes of the present invention is to provide a current limiting circuit, which solves the technical problems of large error, complex structure, high cost and difficult current limiting for the power tube working in the linear region in the prior art.
It is an object of the present invention to provide a powered device having a current limiting circuit.
In order to achieve one of the above objects, an embodiment of the present invention provides a current limiting circuit, including a current input terminal, a mirror circuit, and a regulating circuit connected in sequence; the mirror circuit comprises a first field effect transistor and a second field effect transistor, wherein grid electrodes of the first field effect transistor and the second field effect transistor are connected with each other; the input side of the regulating circuit is connected with the source electrode of the second field effect transistor and the reference voltage, the output side of the regulating circuit is connected with the grid electrode of the first field effect transistor, and the regulating circuit is configured to control the level of the grid electrode of the first field effect transistor according to the output of the source electrode of the second field effect transistor and the reference voltage; the current limiting circuit further comprises a compensation circuit connected to the gate of the second field effect transistor and configured to output a compensation voltage, wherein the value of the compensation voltage is equal to the value of the reference voltage.
As a further improvement of an embodiment of the present invention, the mirror circuit further includes a high-level terminal and a ground-level terminal, the high-level terminal is connected to the drain of the first fet and the drain of the second fet, and the ground-level terminal is connected to the source of the first fet, the source of the second fet, and the adjusting circuit; the adjusting circuit is configured to selectively pull the level of the gate of the first field effect transistor low according to the output of the source of the second field effect transistor and the reference voltage.
As a further improvement of an embodiment of the present invention, the adjusting circuit includes a first comparator, where a non-inverting input end of the first comparator is connected to a source electrode of the second field effect transistor, an inverting input end of the first comparator is connected to the reference voltage, and an output end of the first comparator is connected to a gate electrode of the first field effect transistor; the first comparator is configured to control the level of the first field effect transistor gate according to the comparison result of the output value of the source electrode of the second field effect transistor and the value of the reference voltage.
As a further improvement of an embodiment of the present invention, the adjusting circuit includes a first sense resistor and a third field effect transistor; one end of the first sensing resistor is grounded, and the other end of the first sensing resistor is connected with the non-inverting input end of the first comparator; and the grid electrode of the third field effect transistor is connected with the output end of the first comparator, the source electrode of the third field effect transistor is grounded, and the drain electrode of the third field effect transistor is connected with the grid electrode of the first field effect transistor.
As a further improvement of an embodiment of the present invention, the current limiting circuit further includes a reference voltage source, one end of which is grounded, and the other end of which is connected to the inverting input terminal of the first comparator.
As a further improvement of an embodiment of the present invention, the compensation circuit includes a compensation current source and a compensation resistor, the compensation current source is connected to the gate of the second field effect transistor, and the gate of the first field effect transistor is connected to the gate of the second field effect transistor through the compensation resistor; the compensation current source is configured to output a compensation current having a value equal to a ratio of a value of the reference voltage to a resistance value of the compensation resistor.
As a further improvement of an embodiment of the present invention, the compensation circuit includes a first mirror branch, a second mirror branch, and a reference circuit connected to the first mirror branch; the reference circuit comprises a fourth field effect transistor, a second comparator and a reference resistor, and the fourth field effect transistor is connected in series with the first mirror image branch; the output end of the second comparator is connected with the grid electrode of the fourth field effect transistor, and the non-inverting input end of the second comparator is connected with the reference voltage; one end of the reference resistor is connected with the source electrode of the fourth field effect transistor and the inverting input end of the second comparator, and the other end of the reference resistor is grounded; the compensation circuit further comprises a second induction resistor connected in series with the second mirror branch, wherein one end of the second induction resistor which is not grounded is connected with the input side of the regulating circuit and is configured to provide reference voltage for the regulating circuit.
As a further improvement of an embodiment of the present invention, the compensation circuit further includes a third mirror branch and a compensation resistor; one end of the compensation resistor is connected with the grid electrode of the first field effect transistor, and the other end of the compensation resistor is respectively connected with the third mirror image branch and the grid electrode of the second field effect transistor.
As a further improvement of an embodiment of the present invention, the adjusting circuit includes a first comparator, a first sensing resistor and a third field effect transistor, where a non-inverting input end of the first comparator is connected to a source electrode of the second field effect transistor, an inverting input end of the first comparator is connected to the second mirror branch, and an output end of the first comparator is connected to a gate electrode of the third field effect transistor; one end of the first sensing resistor is grounded, and the other end of the first sensing resistor is connected with the non-inverting input end of the first comparator; one end of the second sensing resistor, which is not grounded, is connected with the inverting input end of the first comparator; and the grid electrode of the third field effect transistor is connected with the output end of the first comparator, the source electrode of the third field effect transistor is grounded, and the drain electrode of the third field effect transistor is connected with the grid electrode of the first field effect transistor.
In order to achieve one of the above objects, an embodiment of the present invention provides an electric device, including the current limiting circuit according to any one of the above technical solutions.
Compared with the prior art, the current limiting circuit provided by the invention inputs the compensation voltage equal to the reference voltage to the grid electrode of the second field effect transistor for sampling by arranging the compensation circuit, so that the dynamic balance of the grid voltages of the first field effect transistor and the second field effect transistor is kept, and the currents on the two branches of the mirror circuit are always arranged in proportion or equal to control the error in the current limiting process, and meanwhile, the common applicability of cost, structure and power transistor current limiting is also considered.
Drawings
FIG. 1 is a schematic diagram of a circuit structure of a current limiting circuit according to an embodiment of the invention;
fig. 2 is a schematic circuit diagram of a current limiting circuit according to another embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to specific embodiments shown in the drawings. These embodiments are not intended to limit the invention and structural, methodological, or functional modifications of these embodiments that may be made by one of ordinary skill in the art are included within the scope of the invention.
It should be noted that the term "comprises," "comprising," or any other variation thereof is intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Furthermore, the terms "first," "second," "third," "fourth," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the working process of electric equipment, the output current is possibly too large rapidly due to the conditions of suddenly reduced downstream equivalent impedance or sudden short-circuit fault and the like, and the damage of an upstream power supply or a downstream load is further influenced, so that the current is limited in a reasonable range, particularly, a current limiting circuit or an overcurrent circuit is configured, so that the current limiting circuit or the overcurrent circuit is suitable for the working condition with higher precision requirement, and meanwhile, the cost, the circuit complexity and the compensation error or compensation effect are balanced, so that the current limiting circuit is also one of the technical problems to be solved in the technical field.
The invention provides electric equipment, which comprises a current limiting circuit, wherein the current in the circuit is limited by adjusting the on-off or opening of a field effect transistor, so that the current is maintained in a stable range, and the damage of an internal power supply device and/or other functional devices of the electric equipment caused by overlarge current is prevented.
The electric equipment can be electronic equipment such as a computer, a mobile phone, an upper computer and the like, can also be necessary equipment in an electric loop such as a power supply, an ammeter and the like, and can also be any other electric equipment which utilizes external or internal electric energy to realize functions and effects. Of course, the above-mentioned consumers can also be interpreted as separately provided current limiting means provided with a current limiting circuit, to be selectively connected in the circuit to give the relevant system a current limiting function.
An embodiment of the present invention provides a current limiting circuit as shown in fig. 1, which may be disposed in any of the electrical devices described above. The current limiting circuit comprises a current input end 1, a mirror image circuit 2 and a regulating circuit 3 which are connected in sequence. The current input end 1 is used for introducing input current so that the back-end component is enough to utilize the input current to at least carry out limit adjustment and overcurrent judgment; the mirror circuit 2 is used for copying or copying the input current according to a certain proportion and outputting the input current to the regulating circuit 3; the adjusting circuit 3 is configured to determine whether the current from the mirror circuit 2 meets a condition according to a preset operation relationship, and output at least one of an adjusting signal or an indicating signal when the current meets the condition, so as to adjust the magnitude of the input current and/or indicate that the current circuit is in an overcurrent state.
The mirror circuit 2 comprises a first field effect transistor 21 and a second field effect transistor 22 with mutually connected gates, the input side of the regulating circuit 3 is connected with the source electrode of the second field effect transistor 22 and the reference voltage Vref, and the output side is connected with the gate electrode of the first field effect transistor 21, and the regulating circuit 3 is further configured to control the level of the gate electrode of the first field effect transistor 21 according to the output of the source electrode of the second field effect transistor 22 and the reference voltage Vref. For example, when the operational relationship between the output level or the output current of the source electrode of the second field effect transistor 22 and the reference voltage Vref accords with a preset relationship, the gate electrode of the first field effect transistor 21 is used to control the gate electrode to turn off or limit the opening of the second field effect transistor 22, and/or when the operational relationship between the output level or the output current of the source electrode of the second field effect transistor 22 and the reference voltage Vref does not accord with a preset relationship, the normal conduction of the first field effect transistor 21 is restored, so that a current limiting circuit with restorability is formed.
It is to be understood that any description of "connected" in this disclosure, including those described above, may be interpreted as having both a direct connection and an indirect connection, where the indirect connection may include establishing a connection between other electronic components and may include obtaining an equivalent signal or achieving an equivalent effect by connecting other electronic components. For example, the gates of the first fet 21 and the second fet 22 may be directly connected, or may establish a connection relationship through other components, for example, the connection between the adjusting circuit 3 and the reference voltage Vref may be directly connected, or may be connected to other circuits to obtain an equivalent reference voltage Vref signal or value.
Further, the current limiting circuit further includes a compensation circuit 4 for compensating the level influence of the reference voltage Vref on the second fet 22, balancing the mirror relationship between the first fet 21 and the second fet 22, and improving the precision of circuit operation and current limitation. Specifically, the compensation circuit 4 is connected to the gate of the second field-effect transistor 22 and configured to output a compensation voltage Voffset, and further, the value of the compensation voltage Voffset is configured to be equal to the value of the reference voltage Vref. In this way, by raising the gate level of the second fet 22, the abnormal situation that the voltage of the gate to the source of the second fet 22 is not proportional to the voltage of the gate to the source of the first fet 21 due to the source level of the second fet 22 being raised by the reference voltage Vref provided in the regulator circuit 3 is compensated.
The first fet 21 and the second fet 22 may be specifically configured as LDMOS (Laterally Diffused Metal-Oxide Semiconductor) in one embodiment, and compared to a general transistor, the LDMOS has advantages of gain, linearity, switching performance, heat dissipation performance, and number of stages reduction, and based on the properties of high voltage and high frequency high power devices, the LDMOS can be better compatible with CMOS processes and be suitable for building a radio frequency power circuit. The first fet 21 and the second fet may be configured as any one of an NLDMOS (N-doped Metal-Oxide Semiconductor, N-type Laterally Diffused Metal oxide semiconductor) or a PLDMOS (P-doped Metal-Oxide Semiconductor, P-type Laterally Diffused Metal oxide semiconductor).
In one embodiment, the current input terminal 1 may directly input the upstream power supply signal to the mirror circuit 2, or may input the on signal to the mirror circuit 2 to initialize the mirror circuit 2 to receive the upstream power supply signal, in the latter embodiment, the current input terminal 1 may be configured to be connected to the gate of the first fet 21, and the input on signal may control the first fet 21 to be turned on during the initialization stage to receive the input current from the drain thereof.
Further, the mirror circuit 2 further includes a high-level terminal 23 and a ground-level terminal 24, the high-level terminal 23 is connected to the drain of the first fet 21 and the drain of the second fet 22, and the ground-level terminal 24 is connected to the source of the first fet 21, the source of the second fet 22, and the adjusting circuit. In this way, the first fet 21 and the second fet 22 may be configured as NLDMOS, and the gates of the two NLDMOS are controlled by the current input terminal so as to be connected to the high level terminal 23 and the ground level terminal 24 through the source and the drain, thereby obtaining the input current and performing subsequent overcurrent judgment and current limiting control.
Based on this, the adjusting circuit 3 may be further configured to selectively pull down the gate level of the first fet 21 according to the source output of the second fet 22 and the reference voltage Vref. The above-mentioned judging process may be that the arithmetic unit is connected to the source electrode of the second field effect transistor 22 and the reference voltage Vref, so as to output the high-low level according to the preset judging rule, or simply comparing the two items of data, judging and outputting. The level pulling-down process may be to pull the level to any one of preset low levels to adjust the opening, or directly pull the level to the ground to directly turn off the first fet 21.
In a specific embodiment, the adjusting circuit 3 may be configured to include a first comparator 31, wherein a non-inverting input terminal of the first comparator 31 is connected to the source of the second fet 22, an inverting input terminal of the first comparator 31 is connected to the reference voltage Vref, and an output terminal of the first comparator 31 is connected to the gate of the first fet 21. In this way, the first comparator 31 is used to determine whether the source output of the second fet 22 is greater than the reference voltage Vref, and when it is determined that the source output is greater than or less than the reference voltage Vref, the first fet 21 is controlled to perform different actions according to different output signals. Further, the first comparator 31 may be configured to control the level of the gate of the first fet 21 according to the comparison result of the output value of the source of the second fet 22 and the value of the reference voltage Vref. For example, specifically, when the source output value is determined to be greater than the reference voltage Vref, the first fet 21 may be controlled to be turned off, and when the source output value is determined to be equal to or less than the reference voltage Vref, the first fet 21 may be controlled to be turned on. It will be appreciated that the connection between the first comparator 31 and the gate of the first fet 21 may be direct connection or indirect connection.
Preferably, the adjusting circuit 3 includes a first sensing resistor 32 and a third fet 33, wherein one end of the first sensing resistor 32 is grounded, the other end of the first sensing resistor 32 is connected to the non-inverting input end of the first comparator 31, the gate of the third fet 33 is connected to the output end of the first comparator 31, the source of the third fet 33 is grounded, and the drain of the third fet 33 is connected to the gate of the first fet 21. Thus, under the action of the first sensing resistor 32, the source output of the second fet 22 (i.e., the non-inverting input of the first comparator 31) is formed into a voltage signal with respect to ground, and the value of the voltage signal is compared with the value of the reference voltage Vref by the first comparator 31, when the voltage signal is greater than the reference voltage Vref, the output high level controls the third fet 33 to turn on, the gate level of the first fet 21 is pulled to ground, and when the voltage signal is less than or equal to the ground, the output low level controls the third fet 33 to turn off, so that the upstream circuit operates normally.
In this embodiment, the current limiting circuit further includes a reference voltage source 34, where one end of the reference voltage source 34 is grounded, and the other end of the reference voltage source 34 is connected to the inverting input terminal of the first comparator 31. In this way, by controlling the magnitude of the value of the output voltage signal from the reference voltage source 34, the current limiting circuit is made to be adequate for devices under various operating conditions or precision requirements.
In the embodiment shown in fig. 1, the compensation circuit 4 may include a compensation current source 40 and a compensation resistor 41, thereby forming a compensation voltage in conformity with the reference voltage Vref. Specifically, the compensation current source 40 is connected to the gate of the second field effect transistor 22, and the gate of the first field effect transistor 21 is connected to the gate of the second field effect transistor 22 through the compensation resistor 41; the compensation current source 40 is correspondingly configured to output a compensation current, and the value of the compensation current is equal to the ratio of the value of the reference voltage Vref to the organization of the compensation resistor 41, so that the compensation voltage with the same value as the reference voltage Vref is equivalently input to the gate of the second field effect transistor 22. In this way, the source level of the second fet 22 is pulled up due to the presence of the first sense resistor 32, and an error approximately equal to the reference voltage Vref appears, so that the voltage of the gate to the source of the second fet 22 is smaller than the voltage of the gate to the source of the first fet 21, and thus, the gate voltage of the second fet 22 can be increased by the above-mentioned arrangement of the compensation circuit 4, so that the voltage difference between the second fet 22 and the first fet 21 is balanced, and the over-current protection (OCP, over Current Protection) error is reduced.
Another embodiment of the invention provides a current limiting circuit as shown in fig. 2, which may have the same or similar current input 1, mirror circuit 2 and regulating circuit 3 as the previous embodiment, wherein the mirror circuit 2 may likewise comprise a first field effect transistor 21 and a second field effect transistor 22, and the current limiting circuit may comprise a compensating circuit 4. In a specific embodiment, the mirror circuit 2 may further include a high level terminal 23 and a ground level terminal 24.
As for the compensation circuit 4 part in this embodiment, it may be specifically configured to include a first mirror branch 421, a second mirror branch 422, and a reference circuit 44 connected to the first mirror branch 421, so that the first mirror branch 421 mirrors the reference signal generated by the reference circuit 44 to the second mirror branch 422, forming the input of the adjusting circuit 3 (or specifically, the first comparator 31).
The reference circuit 44 may specifically include a fourth fet 441, a second comparator 442, and a reference resistor 443, where the fourth fet 441 is connected in series to the first mirror circuit 421, and preferably connected in series through the drain and the source of the fourth fet 441. The output end of the second comparator 442 is connected to the gate of the fourth fet 441, the non-inverting input end is connected to the reference voltage Vref, meanwhile, one end of the reference resistor 443 is connected to the source of the fourth fet 441 and the inverting input end of the second comparator 442, and the other end of the reference resistor 443 is grounded. In this way, the second comparator 442 can selectively turn on the fourth fet 441 according to the relationship between the voltage on the reference resistor 443 and the reference voltage Vref to regulate the voltage on the first mirror branch 421 to stabilize, form the regulated reference voltage, and use the regulated reference voltage as the input of the regulating circuit 3 through the mirror relationship between the first mirror branch 421 and the second mirror branch 422.
In a specific implementation manner of the foregoing embodiment, the compensation circuit 4 may further include a second sensing resistor 45 connected in series to the second mirror circuit 422, where a non-grounded end of the second sensing resistor 45 is connected to the input side of the adjusting circuit 3 and configured to provide the reference voltage Vref or the adjusted reference voltage to the adjusting circuit 3.
Further, the compensation circuit 4 may further include a third mirror branch 423 and a compensation resistor 41, similar to the previous embodiment, between the gate of the first fet 21 and the gate of the second fet 22, a connection relationship may also be established between the gate of the first fet 21 and the gate of the second fet 22 through the compensation resistor 41, in other words, one end of the compensation resistor 41 is connected to the gate of the first fet 21, and the other end of the compensation resistor 41 is connected to the gate of the third mirror branch 423 and the gate of the second fet 22, respectively, so that the reference voltage formed on the first mirror branch 421 is directly used as the compensation voltage to compensate the gate voltage of the second fet 22.
Specifically, in this embodiment, when the reference resistor 443 has a resistance value R0, the compensation resistor 41 has a resistance value R1, the first sense resistor 32 has a resistance value R2, and the second sense resistor 45 has a resistance value R3, the gate voltage of the second fet 22 has a voltage deviation Δv from the gate voltage of the first fet 21 in a state where current limitation is normally performed, and the voltage deviation satisfies at least:
in the case that the first mirror branch 421, the second mirror branch 422 and the third mirror branch 423 form an equal proportion mirror image, the voltages on the compensation resistor 41 and the second sensing resistor 45 are equal, so that the first comparator 31 can control the first sensing resistor 32 to make the upper voltage equal to the upper voltage of the second sensing resistor 45, and it is ensured that the first fet 21 and the second fet 22 can form a mirror image according to a preset proportion. When the current copied by the second FET 22 generates voltage higher than that generated by the first sense resistor 32
When the resistance of the second sensing resistor 45 is consistent with the resistance of the compensation resistor 41, that is, higher than the voltage deviation Δv, the third fet 33 is turned on, and the gate voltage of the first fet 21 is pulled down, so that the current of the upstream circuit system is always maintained within the preset overcurrent protection range.
Based on the above principle, in terms of circuit structure, similarly to the previous embodiment, the adjusting circuit 3 may also include a first comparator 31, a first sensing resistor 32 and a third fet 33, wherein the non-inverting input terminal of the first comparator 31 is connected to the source of the second fet 22, the inverting input terminal of the first comparator 31 is connected to the second mirror branch 422, and the output terminal of the first comparator 31 is connected to the gate of the third fet 33. One end of the first sensing resistor 32 is grounded, and the other end of the first sensing resistor is connected to the non-inverting input end of the first comparator 31. The non-grounded end of the second sensing resistor 45 is connected to the inverting input terminal of the first comparator 31. The gate of the third fet 33 is connected to the output of the first comparator 31, the source of the third fet 33 is grounded, and the drain of the third fet 33 is connected to the gate of the first fet 21. In this way, one end of the first sense resistor 32 and one end of the second sense resistor 45 are respectively used as inputs to control the on/off of the third fet 33, so as to affect the level of the first fet 21.
It should be noted that, although the mirror scaling factor of the mirror circuit 2 formed by the first fet 21 and the second fet 22 is not limited in this embodiment, and may be a complete replica or a proportional mirror (for example, k:1 from the first fet 21 to the second fet 22), the three mirror branches should be specifically configured to be completely replicated to unify the current outputs of the three branches, so as to achieve the technical effect expected in another embodiment of the present invention. In terms of circuit configuration, the first, second and third mirror branches 421, 422 and 423 may be specifically configured to implement mirror replication through fifth, sixth and seventh field- effect transistors 4210, 4220 and 4230, respectively, having the same channel ratio parameter W/L. Specifically, the fifth field effect transistor 4210, the sixth field effect transistor 4220 and the seventh field effect transistor 4230 may be configured as P-channel field effect transistors, where the source electrode is connected to the high level, the gate electrodes are connected to each other, and the drain electrodes respectively extend, so as to form the first mirror branch 421, the second mirror branch 422 and the third mirror branch 423 in sequence.
It is also emphasized that fourth fet 441 and third fet 33 may be configured as common N-channel fets for functional and cost balance considerations. In another embodiment shown in fig. 2, the reference voltage Vref coupled to the non-inverting input of the second comparator 442 may be configured to be provided by a separately provided reference voltage source similar to the embodiment shown in fig. 1, although other implementations are not excluded.
In summary, in the current limiting circuit provided by the invention, the compensation circuit 4 is arranged to input the compensation voltage equal to the reference voltage to the gate of the second field effect transistor 22 for sampling, so that the dynamic balance of the gate voltages of the first field effect transistor 21 and the second field effect transistor 22 is maintained, and the currents on the two branches of the mirror circuit 2 are always arranged in proportion or equal to control the error in the current limiting process, and meanwhile, the common applicability of cost, structure and power tube current limiting is considered.
It should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is for clarity only, and that the skilled artisan should recognize that the embodiments may be combined as appropriate to form other embodiments that will be understood by those skilled in the art.
The above list of detailed descriptions is only specific to practical embodiments of the present invention, and they are not intended to limit the scope of the present invention, and all equivalent embodiments or modifications that do not depart from the spirit of the present invention should be included in the scope of the present invention.
Claims (10)
1. The current limiting circuit is characterized by comprising a current input end, a mirror image circuit and an adjusting circuit which are connected in sequence;
the mirror circuit comprises a first field effect transistor and a second field effect transistor, wherein grid electrodes of the first field effect transistor and the second field effect transistor are connected with each other;
the input side of the regulating circuit is connected with the source electrode of the second field effect transistor and the reference voltage, the output side of the regulating circuit is connected with the grid electrode of the first field effect transistor, and the regulating circuit is configured to control the level of the grid electrode of the first field effect transistor according to the output of the source electrode of the second field effect transistor and the reference voltage; the mirror circuit further comprises a high-level end and a ground level end, wherein the high-level end is connected with the drain electrode of the first field effect transistor and the drain electrode of the second field effect transistor, and the ground level end is connected with the source electrode of the first field effect transistor, the source electrode of the second field effect transistor and the regulating circuit;
the current limiting circuit further comprises a compensation circuit connected to the gate of the second field effect transistor and configured to output a compensation voltage, wherein the value of the compensation voltage is equal to the value of the reference voltage.
2. The current limiting circuit of claim 1, wherein the regulation circuit is configured to selectively pull the level of the gate of the first field effect transistor low based on the output of the source of the second field effect transistor and the reference voltage.
3. The current limiting circuit of claim 1, wherein the regulation circuit comprises a first comparator having a non-inverting input connected to the source of the second fet, an inverting input connected to the reference voltage, and an output connected to the gate of the first fet; the first comparator is configured to control the level of the first field effect transistor gate according to the comparison result of the output value of the source electrode of the second field effect transistor and the value of the reference voltage.
4. A current limiting circuit according to claim 3, wherein the regulation circuit comprises a first sense resistor and a third field effect transistor; one end of the first sensing resistor is grounded, and the other end of the first sensing resistor is connected with the non-inverting input end of the first comparator; and the grid electrode of the third field effect transistor is connected with the output end of the first comparator, the source electrode of the third field effect transistor is grounded, and the drain electrode of the third field effect transistor is connected with the grid electrode of the first field effect transistor.
5. A current limiting circuit according to claim 3, further comprising a reference voltage source connected at one end to ground and at the other end to the inverting input of the first comparator.
6. The current limiting circuit of claim 1, wherein the compensation circuit comprises a compensation current source and a compensation resistor, the compensation current source is connected to the gate of the second field effect transistor, and the gate of the first field effect transistor is connected to the gate of the second field effect transistor through the compensation resistor; the compensation current source is configured to output a compensation current having a value equal to a ratio of a value of the reference voltage to a resistance value of the compensation resistor.
7. The current limiting circuit of claim 1, wherein the compensation circuit comprises a first mirror leg, a second mirror leg, and a reference circuit connected to the first mirror leg;
the reference circuit comprises a fourth field effect transistor, a second comparator and a reference resistor, and the fourth field effect transistor is connected in series with the first mirror image branch; the output end of the second comparator is connected with the grid electrode of the fourth field effect transistor, and the non-inverting input end of the second comparator is connected with the reference voltage; one end of the reference resistor is connected with the source electrode of the fourth field effect transistor and the inverting input end of the second comparator, and the other end of the reference resistor is grounded;
the compensation circuit further comprises a second induction resistor connected in series with the second mirror branch, wherein one end of the second induction resistor which is not grounded is connected with the input side of the regulating circuit and is configured to provide reference voltage for the regulating circuit.
8. The current limiting circuit of claim 7, wherein the compensation circuit further comprises a third mirror leg and a compensation resistor; one end of the compensation resistor is connected with the grid electrode of the first field effect transistor, and the other end of the compensation resistor is respectively connected with the third mirror image branch and the grid electrode of the second field effect transistor.
9. The current limiting circuit of claim 7, wherein the regulation circuit comprises a first comparator, a first sense resistor, and a third field effect transistor, wherein a non-inverting input terminal of the first comparator is connected to a source of the second field effect transistor, an inverting input terminal is connected to the second mirror branch, and an output terminal is connected to a gate of the third field effect transistor; one end of the first sensing resistor is grounded, and the other end of the first sensing resistor is connected with the non-inverting input end of the first comparator; one end of the second sensing resistor, which is not grounded, is connected with the inverting input end of the first comparator; and the grid electrode of the third field effect transistor is connected with the output end of the first comparator, the source electrode of the third field effect transistor is grounded, and the drain electrode of the third field effect transistor is connected with the grid electrode of the first field effect transistor.
10. A powered device comprising a current limiting circuit as claimed in any one of claims 1-9.
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| CN107765751A (en) * | 2017-11-29 | 2018-03-06 | 成都锐成芯微科技股份有限公司 | Common mode feedback circuit and signal processing circuit |
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| CN105680431B (en) * | 2016-03-25 | 2018-07-20 | 中国电子科技集团公司第五十八研究所 | A kind of adjustable current-limiting protection circuit |
| CN105846493B (en) * | 2016-04-19 | 2018-08-28 | 无锡中感微电子股份有限公司 | Over-current detection, protection circuit and battery |
| CN206195635U (en) * | 2016-10-10 | 2017-05-24 | 上海晶丰明源半导体股份有限公司 | Controller and adopt switching power supply of this controller |
| US10168363B1 (en) * | 2018-03-14 | 2019-01-01 | STMicroelectronics Design & Application S.R.O. | Current sensor with extended voltage range |
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| CN107765751A (en) * | 2017-11-29 | 2018-03-06 | 成都锐成芯微科技股份有限公司 | Common mode feedback circuit and signal processing circuit |
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