CN114446334A - Stacked memory and method of making the same - Google Patents

Abstract

The application discloses a stacked memory and a manufacturing method thereof, comprising the following steps: the memory device comprises a plurality of memory bare chips, a plurality of storage circuit chips and a plurality of control modules, wherein each memory bare chip is provided with independent fusing information, the fusing information is obtained by fusing a preset number of fuses arranged in the memory bare chip according to a fusing arrangement combination mode of the fuses, and the fusing arrangement combination mode of the preset number of fuses in each memory bare chip is sequentially determined according to the manufacturing process of the stacked memory; each memory die may be individually selected and controlled by a signal that includes fuse information. On the basis of removing the logic bare chip, in the manufacturing process of the stacked memory, a fusing arrangement combination mode is determined for each memory bare chip in sequence to obtain independent fusing information, so that each memory bare chip can be independently selected and controlled by a signal containing the fusing information, and each memory bare chip does not need a through silicon via to distinguish memory partitions, so that the effects of reducing the through silicon vias and saving the cost can be achieved.

Description

Stacked memory and method of making the same

technical field

The present application relates to the technical field of semiconductor manufacturing, and in particular, to a stacked memory and a manufacturing method thereof.

Background technique

At present, in the manufacturing scheme of stacked memory, a memory die (Memory Die) including a memory array and a logic die (Control Die) including peripheral circuits are respectively fabricated, and by combining multiple memory die and logic die In a stacked package, the stacked dies are electrically connected to each other through through-silicon vias (TSVs, Thru Silicon Vias).

Since the TSVs need to occupy a certain position on the die, in order to increase the chip density of the memory, the number of TSVs needs to be reduced. However, the current stacked bare chips use the TSVs to distinguish the storage partitions. These through-silicon vias are essential in groups of stacked memory partitions called banks, which can be accessed independently for read and write operations.

SUMMARY OF THE INVENTION

The purpose of the present application is to propose a stacked memory and a manufacturing method thereof in view of the above-mentioned shortcomings of the prior art, and the purpose is achieved through the following technical solutions.

A first aspect of the present application proposes a stacked memory, including:

Multiple storage dies;

Each storage die in the plurality of storage die has independent fusing information, and the fusing information is obtained by fusing a preset number of fuses set in the storage die according to the fusing arrangement and combination of the fuses, And the fuse arrangement and combination of the fuses in each memory die are sequentially determined according to the stacked memory manufacturing process;

Wherein, each of the memory dies is individually selected and controlled by a signal containing fusing information.

A second aspect of the present application provides a method for manufacturing a stacked memory, the method comprising:

Provides multiple storage dies;

stacking each memory die of the plurality of memory dies together in sequence extending in a vertical direction through through-silicon vias;

For each memory die, determine a fuse arrangement and combination for the memory die according to the stacking order, and blow the fuses in the memory die according to the fuse arrangement and combination to obtain the fuse of the memory die. information.

A third aspect of the present application provides an electronic device including the stacked memory as described in the first aspect.

Based on the above-mentioned stacked memory and its manufacturing method, in the prior art, each group of stacked partitions is selected and controlled by the logic die signal, that is to say, the prior art distinguishes the selection and control along the vertical direction However, in the present application, on the basis of removing the logic die, in the manufacturing process of the stacked memory, a certain number of fusing arrangements and combinations of fuses are sequentially determined for each memory die, so as to fuse the memory according to the determined fusing arrangement and combination. The fuses in the die can obtain an independent fuse information, so that each memory die can be independently selected and controlled by the signal containing the fuse information, that is, the application is to distinguish the selection and control along the horizontal direction, so that each memory chip can be selected and controlled independently. There is no need for through-silicon vias to distinguish storage partitions on a single storage die, so that the effects of reducing through-silicon vias and saving costs can be achieved, and it is convenient to increase the storage density of the memory. In addition, because the logic die is removed, the chip thickness can also be reduced.

Description of drawings

The drawings described herein are used to provide further understanding of the present application and constitute a part of the present application. The schematic embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation of the present application. In the attached image:

FIG. 1 is a schematic structural diagram of a stacked memory in a related art shown in this application;

FIG. 2 is a schematic structural diagram of a stacked memory according to an exemplary embodiment of the present application;

FIG. 3 is a flowchart of an embodiment of a method for manufacturing a stacked memory according to an exemplary embodiment of the present application.

Detailed ways

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not to scale, some details have been exaggerated for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships are only exemplary, and in practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art should Regions/layers with different shapes, sizes, relative positions can be additionally designed as desired.

In the context of this disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. element. In addition, if a layer/element is "on" another layer/element in one orientation, then when the orientation is reversed, the layer/element can be "under" the other layer/element.

Referring to the prior art stacked memory shown in FIG. 1, it includes memory dies and logic dies that are sequentially stacked and packaged in a vertical direction, the dies are electrically connected to each other through through-silicon vias, and the memory dies provide memory processing Functions are used to store data, and the logic die provides to perform standard memory access coordination functions such as page table translation, address mapping, write grouping, etc.

In some embodiments, as also shown in FIG. 1 , the stacked memory further includes a processing unit and a packaging substrate stacked with the die.

Wherein, the processing unit is a programmable processing unit or a reprogrammable processing unit. In some embodiments, the reprogrammable processing unit contains logic circuitry that can be dynamically programmed to perform various functions or to execute certain instructions. In one embodiment, the reprogrammable processing unit may be configured to execute instructions including memory processing functions that control the memory die. Additionally, reprogrammable processing units may include, but are not limited to, field programmable gate arrays, application specific integrated circuits, programmable array logic, and the like. The package substrate can be configured to communicate between other components or dies and external to the overall system.

In terms of storage, each memory die in Figure 1 is divided into n memory partitions, each partition includes several memory banks, and each partition is stacked on top of each other by extending through silicon vias in a vertical direction , each group of stacked partitions may be referred to as a vault, and processing units can independently access each vault for read and write operations through a logical die.

However, the current contradiction is: in order to improve the storage density of the memory, the number of TSVs needs to be reduced, but the storage partitions of the storage die need to be distinguished by TSVs, which cannot be reduced.

It should be noted that the above-mentioned FIG. 1 only exemplarily shows one logic die, but the actual product does not limit the number of logic die.

In order to solve the above-mentioned technical problems, in order to reduce the number of TSVs on the stacked die, by removing the logic die, only the storage die is used to extend and stack sequentially in the vertical direction, and for each memory die, according to the stacking order, The storage die determines the fusing arrangement and combination of the fuses, and blows the fuses in the storage die according to the fusing arrangement and combination, so as to obtain the fusing information of the storage die. Signals for fuse information are individually selected and controlled.

Referring to FIG. 2 , a stacked memory according to an exemplary embodiment of the present application includes: n storage dies, and each of the n storage dies has independent fusing information.

The fusing information is obtained by fusing the preset number of fuses set in the storage die according to the fuse arrangement and combination, and the fuse arrangement and combination of the preset number of fuses in each storage die is based on the stacking The memory manufacturing process is sequentially determined, and each memory die can be individually selected and controlled by a signal containing the blowdown information. For example, the signal may be generated and controlled by a processing unit.

In order to make the fusing information of each storage die unique, the number of fuses set in the storage die may be determined according to the number of the storage die. For example, if the number of storage die is 4, then the number of fuses set in each memory die needs to be at least 2, that is, the fuse arrangement and combination are 00, 01, 10, and 11, and one storage die corresponds to one A combination of fusing arrangements, where 0 means no fusing, and 1 means fusing.

In some embodiments, each memory die includes a Memory Array and a Control Peripheral Circuitry.

Exemplarily, starting from the first storage die at the top, and extending downward in the vertical direction, the second storage die, the third storage die...the nth storage die are stacked together, thereby According to the stacking order, determine a fuse arrangement and combination 1 for the first memory die, obtain fuse information 1, determine a fuse arrangement and combination 2 for the second memory die, and obtain fuse information 2, and so on, as The n-th storage die determines a fusing arrangement and combination mode n, and obtains fusing information 3 .

Based on the above description, by comparing the stacked memory conceived in the present application with the prior art, each group of stacked partitions in the prior art is selected and controlled by the logic die signal, that is, the prior art is along the The selection and control are distinguished in the vertical direction, while in the present application, on the basis of removing the logic die, in the manufacturing process of the stacked memory, the fuse arrangement and combination of a certain number of fuses are sequentially determined for each memory die. The fuse arrangement and combination of the fuses in the memory die are blown to obtain an independent fuse information, so that each memory die can be independently selected and controlled by the signal containing the fuse information, so that no silicon is required on each memory die. Through-holes are used to distinguish storage partitions, which can reduce through-silicon holes and save costs, which is convenient for improving the storage density of the memory. In addition, because the logic die is removed, the chip thickness can also be reduced.

It should be noted that the fuse information of each storage die is blown in the storage die according to a correspondingly determined fuse arrangement and combination during the stacking process.

Exemplarily, the fuse set in the storage die can be an electric fuse, and certainly can also be a metal fuse, which is not limited in this application.

In some embodiments, in order to enable the n memory dies to communicate with each other, through silicon vias may be provided at the same position on each of the n memory dies.

The provided through-silicon vias are used to electrically connect the n storage dies.

It should be noted that, since the present application does not need to distinguish storage partitions by TSVs compared to the prior art, the number of TSVs on each storage die in the present application is much smaller than that of the stacked bare chips in the prior art. The number of TSVs on the chip.

In an example, under the condition that both the prior art and the present application use the same number of storage die stacking with the same storage capacity, since the prior art needs to use through-silicon vias to distinguish storage partitions, usually each storage The bare chips need to make through silicon vias of more than 1000ea for electrical connection, and the present application does not need to use the through silicon vias to distinguish the storage partitions, and each stacked storage die only needs to make through silicon vias of 200ea to 400ea.

In some embodiments, the stacked memory may further include a switch selection circuit (Switch) electrically connected to each memory die for sending a signal to the memory die according to the fusing information of the memory die contained in the signal. on the corresponding storage die.

The signal may be generated by the processing unit according to actual requirements and sent to the switch selection circuit, or may be generated by the processing unit according to a control instruction generated by an external controller and sent to the switch selection circuit.

The signal may be a row active command (Row Active command), or may also be a column active command (Column Active command).

Exemplarily, the switch selection circuit may be constituted by a pass gate structure, or may be constituted by a logic circuit device (Logic).

Based on the above-mentioned structure of the stacked memory shown in FIG. 2 , the manufacturing method of the stacked memory proposed in the present application will be described in detail below with specific embodiments.

FIG. 3 is a flowchart of an embodiment of a method for manufacturing a stacked memory according to an exemplary embodiment of the present application. As shown in FIG. 3 , the method for manufacturing a stacked memory includes the following steps:

Step 301: Provide multiple storage dies.

Wherein, each memory die includes a memory array and a peripheral driving circuit, and each memory die is an effective die that has passed the test.

Step 302 : Stack each of the plurality of memory dies in sequence along a vertical direction through through-silicon vias.

Step 303: For each storage die, determine a fuse arrangement and combination for the memory die according to the stacking order, and blow the fuses in the memory die according to the fuse arrangement and combination to obtain the memory die. fusing information of the chip.

Wherein, the fusing information of each storage die is achieved in the storage die by fusing the fuses therein according to the determined fusing arrangement and combination.

For the process from step 301 to step 303, reference may be made to the relevant description of the embodiment shown in FIG. 2, and details are not repeated here.

So far, the manufacturing process of a stacked memory shown in the embodiment shown in FIG. 3 is completed, and a stacked memory requiring a small number of TSVs can be formed through the above process, which provides a prerequisite for increasing the chip density of the memory.

The present application also proposes an electronic device, which includes the stacked memory as described in FIG. 2 above.

Exemplarily, the stacked memory may be dynamic random access memory (DRAM), thyristor random access memory (TRAM), static random access memory (SRAM), non-volatile memory (such as read only memory, flash memory) memory, ferroelectric random access memory, magnetoresistive random access memory, etc.).

In some embodiments, electronic devices may include smart phones, computers, tablet computers, wearable smart devices, artificial intelligence devices, and power banks.

In the above description, technical details such as patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as those described above. Additionally, although the various embodiments have been described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

Embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims (9)

1. A stacked memory comprising a plurality of storage dies, characterized in that, Each storage die in the plurality of storage die has independent fusing information, and the fusing information is obtained by fusing a preset number of fuses set in the storage die according to the fusing arrangement and combination of the fuses, And the fuse arrangement and combination of the preset number of fuses in each memory die are sequentially determined according to the stacked memory manufacturing process; Wherein, each of the memory dies is individually selected and controlled by a signal containing fusing information. 2 . The memory according to claim 1 , wherein the fuse in the memory die is an electric fuse and/or a metal fuse. 3 . 3 . The memory according to claim 1 , wherein through silicon vias are provided at the same position on each of the plurality of storage dies; 3 . The through silicon vias are used to electrically connect the plurality of memory dies. 4. The memory of claim 1, further comprising: A switch selection circuit electrically connected to each memory die is configured to send the signal to the memory die corresponding to the fuse information according to the fuse information of the memory die contained in the signal. 5 . The memory according to claim 4 , wherein the switch selection circuit is composed of a turn-on gate structure or a logic circuit. 6 . 6. The memory according to claim 1, wherein the signal is a row activation command or a column activation command. 7. A method for manufacturing a stacked memory, wherein the method comprises: Provides multiple storage dies; stacking each memory die of the plurality of memory dies together in sequence extending in a vertical direction through through-silicon vias; For each memory die, determine a fuse arrangement and combination for the memory die according to the stacking order, and blow the fuses in the memory die according to the fuse arrangement and combination to obtain the fuse of the memory die. information. 8. An electronic device comprising the stacked memory according to any one of claims 1 to 6. 9. The electronic device according to claim 8, comprising a smart phone, a computer, a tablet computer, a wearable smart device, an artificial intelligence device, and a power bank.

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