CN114424143A - Host power delivery from dual port peripheral - Google Patents

Abstract

Apparatus and method for distributing power to a host computer (112). A first serial cable (145) establishes a first data link (146) and a first power transfer link (148) between the first serial port of the peripheral device (110) and the host computer. A second serial cable establishes a second data link (146) and a second power transfer link (148) between the second port of the peripheral device and an external power supply unit (PSU). The peripheral controller circuit (114) detects available power from the external PSU at a level suitable for use by the host device, notifies the host computer of the available power from the external PSU, and interconnects the first serial port and the second serial port to The available power is flowed to the host device via the first power transfer link and the second power transfer link. The peripheral device may take the form of a solid state drive (SSD) (110) having non-volatile memory (118), such as flash memory.

Description

Host Power Delivery from Dual Port Peripherals

SUMMARY OF THE INVENTION

Various embodiments of the present disclosure generally relate to providing electrical power to a host device from a peripheral device, such as, but not limited to, a dual-port data storage device.

In some embodiments, the peripheral device is connected to the host device using a first serial cable to establish a first data link and a first power transfer link with a first serial port of the peripheral device. The peripheral is connected to an external power supply unit (PSU) using a second serial cable to establish a second data link and a second power delivery link with a second serial port of the peripheral. The controller circuit of the peripheral device uses the second data transfer link to detect available power from the external PSU at a level suitable for use by the host device. The controller circuit transmits an indication of available power from the external PSU to the host device via the first data link and interconnects the first serial port and the second serial port in response to a request from the host via the first data link A device-to-peripheral request for available power to flow regulated power to the host device via the first power transfer link and the second power transfer link.

These and other features and advantages that characterize various embodiments can be appreciated in view of the following detailed discussion and accompanying drawings.

Description of drawings

Figure 1 provides a functional block representation of a data storage device to provide an exemplary operating environment for various embodiments of the present disclosure.

2 illustrates the storage device of FIG. 1 operably coupled to a host device in accordance with some embodiments.

3 illustrates a system in which a host device receives electrical power from the storage device of FIG. 2 in accordance with some embodiments.

FIG. 4 shows a power flow configuration of a related art memory device.

5 illustrates a power flow configuration for the storage device of FIG. 3 in accordance with some embodiments.

FIG. 6 is a sequence flow diagram illustrating activation of powering of the host in FIG. 3 .

FIG. 7 is a sequence flow diagram illustrating the deactivation of the power supply of the host in FIG. 3 .

8 illustrates a circuit adapted to charge a battery in accordance with some embodiments.

9 is a functional block diagram of an external power supply unit (PSU) with which various embodiments may be advantageously practiced.

10 is a functional block diagram of a solid state drive (SSD) type data storage device in which various embodiments may be advantageously practiced.

11 is a functional block diagram of a hard disk drive (HDD) or hybrid data storage device in which various embodiments may be advantageously practiced.

Detailed ways

The present disclosure generally relates to the distribution of electrical power among elements in a computer system.

Peripherals, sometimes referred to as computer peripherals, are a class of devices that are separate from the core computer (also referred to as host devices) but provide enhanced functionality. Peripheral devices may include input devices, output devices, storage devices, and the like. A suitable wired or wireless interface is usually provided to enable bidirectional communication between the peripheral device and the host device. The peripheral device may be inside or outside the housing of the host device.

The so-called "Thunderbolt" interface describes a type of interconnection mechanism that is particularly suitable for coupling a host and peripheral devices. The current generation of Thunderbolt connectors are sometimes referred to as Thunderbolt 3 and/or Type-C serial cables, and operate according to the well-known USB (Universal Serial Bus) 3.0 standard. Thunderbolt, sometimes referred to as TBT or TBT3, combines PCIe (Peripheral Computer Interface Express) and DisplayPort (Display Port) (DP) into four serial lanes (each with a maximum transfer rate of 10Gbits/sec). The interface accommodates the transfer of DC power and can support multiplexing of up to six (6) connected devices via a hub or daisy-chain connection.

Since a TBT connection accommodates both data flow and power flow, it should be possible, at least in theory, to supply electrical power from any device in the TBT chain to any other device. In practice, it has been found that peripheral devices such as data storage devices tend to have insufficient power output capabilities to meet the consumption requirements of the host device (such as for supporting host battery charging operations, etc.).

Accordingly, various embodiments of the present disclosure generally relate to apparatuses and methods for distributing electrical power among elements in a computer system, including but not necessarily limited to devices coupled in TBT chains. As explained below, some embodiments provide a dual-port peripheral device (such as a storage device) configured to couple to a host device using a selected port (eg, port A) of the peripheral device. An external power source may be coupled to another selected port (eg, port B) of the peripheral device. This allows electrical power to be directed from an external source to the host through the peripheral device.

The peripheral device's controller is configured to detect the presence of a power source on port B of the device. Once the power is verified to be in a form acceptable to the host, the controller interconnects the power to the power rail of port A and notifies the host that the power is available (if the host chooses to receive it). Different scenarios are envisaged; for example, the host may currently supply power at a first voltage level on the cable interconnecting the host to port A of the peripheral. As a result of negotiation between the host and the peripheral, power at the second voltage may be supplied from the peripheral to the host via the cable in a specified power profile.

When the external source is disconnected, the link remains in place, but the power flow is readjusted to a lower profile. In this way, the peripheral can operate as a smart docking station to adaptively supply/receive both power and data over a single serial cable between the peripheral and the host, and the system automatically switches between different power distributions Toggle thus becomes available.

These and other features and aspects of various embodiments will be understood beginning with a review of FIG. 1 , which generally illustrates an exemplary data storage device 100 . Device 100 is presented to provide the illustrated environment in which various embodiments may be advantageously practiced. The various embodiments described herein are not limited to data storage applications, and can be easily extended to substantially any other type of computer peripheral device, or any other application in which a dual port device can be interfaced to a host device.

The storage device 100 includes a controller 102 and a memory module 104 . Controller 102 provides top-level control for device 100 and may be configured as one or more programmable microcontrollers (also referred to as controllers or processors) with associated programming (firmware, FW) stored in local memory ). Microcontrollers may be arranged in one or more SOCs (systems on a chip), also known as chipsets.

The memory module 104 may be arranged to include one or more non-volatile memory (NVM) elements of a rotatable magnetic recording disk and a solid state memory array. Although a separate controller 102 is shown in FIG. 1, this is not necessary, as alternative embodiments may incorporate any necessary controller functionality directly into the memory module, or external to the data storage device.

FIG. 2 shows a storage device 110 that generally corresponds to the storage device 100 of FIG. 1 . Although not limiting, for purposes of this discussion, storage device 110 will be contemplated to be a solid state drive (SSD) utilizing NAND flash memory to store and retrieve user data for host device 112 . Therefore, SSD is a computer peripheral of the host computer.

Storage device 110 has various elements mapped to FIG. 1 , including storage microcontroller (CPU) 114 , local storage memory 116 , non-volatile memory (NVM) 118 , and storage power module 120 . Local storage memory 116 may be volatile or non-volatile memory utilized by storage microcontroller 114 and stores various elements such as firmware (FW) 122 and data 124 . Firmware 122 represents programming instructions executed by microcontroller 114 . Data 122 may represent user data, metadata, parameters, etc. useful during data transfer operations between NVM 118 and host 112 .

The microcontroller 114 and memory 116 may be incorporated into an SOC (chipset). In this example, NVM 118 represents flash in a separate flash module that negotiates data transfer operations with the SOC. The storage power module 120 manages the distribution and flow of electrical power within and through the storage device 110 in a manner explained below.

Host device 112 takes the form of a computer and includes host microcontroller (CPU) 134 , host memory 136 , user interface (I/F) 138 , and host power module 140 . As previously mentioned, the host microcontroller 134 may take the form of one or more programmable processors. Host memory 136 stores various programming and data elements for microcontroller 134 , including operating system (OS) 142 and various host applications (apps) 144 .

User I/F 138 may constitute various GUI (graphical user interface) type elements (such as a touch screen, display, mouse, keyboard, etc.) to enable a user to interact with the system. The host power module 140 operates in cooperation with the storage power module 120 of the storage device 110 to transfer power between the respective devices via one or more interfaces 145 . Each interface may include one or more sets of data transmission lines 146 and power transmission lines 148 .

FIG. 3 illustrates a system 150 incorporating storage device 110 and host device 112 from FIG. 2 in accordance with some embodiments. The storage device 110 is characterized as a dual-port device having a first port 152 and a second port 154 (denoted as port A and port B, respectively). Dual port storage device 110 may also have additional ports not shown in FIG. 3 . Port A 152 of the storage device is coupled to host port 156 of host 112 and port B 154 is coupled to external port 158 of external power source 160 . While not limiting, it is contemplated that the various port interconnects 162, 164 are configured according to the TBT3 standard and operate as a power and data transfer capable USB 3.0 interface using a Type-C serial cable. Other interface configurations can be used. As explained below, electrical power from external power source 160 flows through storage device 110 to host 112 via interconnects 162 , 164 , as managed by power management circuitry 168 of storage device 110 .

FIG. 4 shows a related art data storage device 170 to briefly illustrate the limitations of the ability to transfer electrical power to a host in the manner depicted in FIG. 3 . Storage device 170 is coupled to host device 172 , daisy-chained device 174 and device power supply unit (PSU) 176 . These interconnections are performed using a first port (port A) 178 , a second port (port B) 180 and a power jack (input) 182 . PSU 176 may be a cord with a transformer that converts alternating current (AC) power from a wall outlet to an appropriate direct current (DC) level for use by storage device 110 . Other configurations for PSU 176 can be used as desired. Thick arrowed line 184 represents the flow of electrical power from PSU 176 through storage device 170 to daisy-chained device 174 .

As shown in FIG. 4 , a portion of the electrical power 184 is directed to a first power control circuit 186 , which includes a 5V power converter circuit 188 and a control/power logic circuitry (MOS) 190 . This supplies the electrical power used by port A178. Another portion of the electrical power 184 is directed to a second power control circuit 192 having a 5V power conversion circuit 194 and a control/power logic circuitry (MOS) 196 for use by port B 180 . Note that power supplied to port B is forwarded for use by daisy-chained device 174 , which may be a companion storage device with similar power consumption requirements as storage device 170 . It should be understood that power 184 from power jack 182 will also be internally routed to other portions of storage device 170 (such as generally shown in FIG. 2 ), but such details have been omitted for clarity.

The power delivery capability of the storage device 170 is insufficient to meet the power consumption requirements of the host 172 . Without limitation, in one exemplary environment, storage device 172 may only be able to supply about 15 watts (W) of power up port A 178, while host 172 may have a higher minimum power consumption requirement at about On the order of 60W to 100W.

Thus, a separate host PSU 198 is used to implement the operation of the host 172 . Power supplied by the PSU 198 may be used by the host 172 in a variety of ways, including power to run the host's processor and other components during normal operation, power to charge the host's rechargeable battery, and the like. The host PSU 198 may take any number of forms, including cables with transformers to perform AC-DC conversion from wall sockets.

FIG. 5 illustrates a data storage device 200 constructed and operative in accordance with various embodiments of the present disclosure to overcome these and other limitations of the prior art, including those associated with FIG. 4 . Note that device 200 generally corresponds to storage devices 100 and 110 as discussed above. For convenience, the same reference numerals are used for similar components that appear in both Figures 4-5.

Storage device 200 is coupled to host device 172 using port A 178 via a suitable interconnect, such as a Type-C serial cable. The storage device 200 is further coupled to an external power supply unit (EXT PSU) 202 via port B 180 using a second C-type serial cable. Power jack 182 provides no external power connection to storage device 200 . Internal power flow is provided from EXT PSU 202 to storage device 200 through port B 180 , as generally represented by thick arrow line 204 . It should be noted that this power is forwarded to host 172 via port A 178 . This eliminates the need for a separate host PSU 198 as shown in FIG. 4 to provide electrical power to the host 172 . This allows only one Type-C serial cable to connect to the host.

To this end, storage device 200 is configured with additional circuitry not present in FIG. 4 , including power delivery (PD) controller 206 , power logic circuit 208 , and power multiplexer (mux) 210 . Furthermore, the enhanced first power control circuit 212 is equipped with an enhanced voltage converter 214 and MOS logic 216 . Voltage converters may include buck-boost power converters with the capability to output power levels at various voltages, including but not necessarily limited to 5V, 9V, 15V, and 20V.

PD controller 206 may form part of an existing storage device controller (eg, see element 114 in FIG. 2), or may be a separate hardwired or programmable processing circuit. If the PD controller is implemented as one or more programmable processors, appropriate program instructions (firmware) will be supplied in the associated memory to facilitate operation. In general, PD controller 206 operates to manage the distribution of power in and through storage device 200 . To this end, PD controller 206 forms part of power management circuit 168 of FIG. 3 and operates to detect the current power state of storage device 210 and provide various control settings within the device, including to power management circuit 208 and voltage converter 214 input of.

In this arrangement, the power controller 208 is responsible for requesting a new profile definition from the PD controller due to the PSU connection on port B. The PD controller notifies the host of the new available distribution. The arrangement can be switched using an automatic power multiplexer.

If the EXT PSU 202 is disconnected from port B, the multiplexer 210 can automatically switch to direct power from the power jack 182 . The PSU device 176 will provide power during the redefinition of the PD profile to a lower PD profile. The power delivery controller will request a new PD profile definition, the PD controller will notify the host, and the host will switch to the lower available PD profile.

FIG. 6 provides a sequence diagram 220 illustrating various operations of the storage device 200 of FIG. 5 to establish an electrical power supply to the host 172 in accordance with some embodiments. Initially, block 222 depicts the connection of the host 172 to the storage device 200 using port A 178 , and block 224 depicts the connection of the EXT PSU 202 to port B 180 . These connections are envisioned as TBT3 interconnects using suitable cables with data and power transfer capabilities.

At block 226, the PD controller 206 detects the interconnection of the EXT PSU to port B. This can be accomplished in a number of ways, including through the use of voltage sensors and/or decoding logic. Communication is established between the PD controller 206 and the controller of the EXT PSU 202 in order to determine the available power distribution from the PSU. The primary storage controller of storage device 200 may facilitate these and other communications as needed. The available power distribution can be characterized in a number of suitable ways. In some embodiments, available power may be represented in terms of available power output levels (eg, 60W, 80W, 100W) that may be supplied by the PSU, or the like.

Block 228 shows establishing a power delivery contract between the PD controller and the PSU. As used herein, a power delivery contract represents an agreed set of parameters (terms) according to which power will be supplied via port B (eg, power distribution). This may include voltage level, total power level, power characteristics, minimum duration for which power will be provided, etc. In some cases, the PD controller may utilize the circuitry of the storage device to verify the available power, such as by testing the applied power or otherwise characterizing whether it is stable enough for use.

Once the power delivery contract is established, flow passes to block 230 where the power multiplexer 210 is configured to receive external power from the PSU. At block 232, the host 172 is notified of the new available power distribution at port A. In response, the host establishes a power delivery contract with the storage device 200 via the host controller (eg, see controller 134 in FIG. 2 ) to deliver electrical power via port A, block 234 .

As needed, adjust the existing system configuration to enable this transfer; for example, the host may have previously applied a power voltage of 5V on the power bus side of the TBT3 cable (eg, power transfer line 148, Figure 2), and now during the contract period, The storage device will supply 20V to the host on these same lines. Once the system is properly configured, power is delivered to the host via port A at block 236 according to the terms of the delivery contract. The host may use this delivered power in any suitable manner as described above, including charging the host's onboard rechargeable battery.

FIG. 7 shows a sequence diagram 240 illustrating the steps performed to subsequently stop providing electrical power from the storage device 240 to the host. Disconnection of power may be performed as a result of a variety of reasons, including sudden and unplanned user disconnection of the external PSU, as indicated by block 242 . Other disconnection scenarios are envisioned, including expiration of a set time for the PSU to agree to supply power to the storage device.

Upon loss of input power at port B, power multiplexer 210 operates to automatically switch to direct internal power through storage device 200 at block 244 . This may include switching to available power from an external source at power jack 182, or switching to electrical power from an internal power source (eg, an internal battery, ultracapacitor, etc.). In some cases, removal of the external PSU may result in a reversed supply of agreed electrical power from the host via port A to the storage device.

As shown in step 246, the PD controller 206 changes the available power distribution of the system to a new level via the multiplexer based on the change in the available power. At block 248, the host is notified of the new maximum available power distribution that the storage device can supply (block 250). As indicated by block 252, based on this information, the host requests a new distribution and adjusts power settings, including switching to another available power source, reconfiguring the system via port A to a new low level of power to the storage device, and the like. It is contemplated that sufficient local power will be available to ensure uninterrupted, continuous operation of the storage device and host during the entire sequence of both Figures 6-7.

FIG. 8 provides a simplified diagram of power source circuit 260 in some embodiments. The power source circuitry may be implemented in storage device 200, host 172, or both, as desired. Generally, circuit 260 includes charging circuit 262 that receives input electrical power, and charging circuit 262 uses the input electrical power to recharge rechargeable battery 264 . The battery 264 may be used to supply electrical power to at least a portion of the computer system at such times when a detected change in system state occurs. For example, power supplied to the host via port A in Figure 5 can be used to charge the host battery, which can then be configured to begin supplying power for use by the host once the external PSU is disconnected.

FIG. 9 shows a functional block representation of an external power supply unit (PSU), such as EXT PSU 202 in FIG. 5 . Other configurations can be used. PSU 280 includes interface (I/F) circuitry 282 , controller 284 and power source 286 . A PSU may form part of a larger device such as a host, peripheral, smart power supply, etc. It is contemplated that the interface circuit 282 is configured to communicate data commands and responses over the data lines connected to the port B 180 of the storage device 200 .

PSU controller 284 may be a hardware or programmable processor-based processor configured to communicate with storage device 200 via port B as described above to negotiate over an associated interface The electrical power supply of the power transmission line. Power source 286 may take the form of a battery, a voltage converter, a charge storage device, or any other form that may provide electrical power to a storage device. As noted above, PSU 280 may form part of a larger operational peripheral or host device, and may include a transformer that performs AC-DC conversion of the electrical power available to the storage device as needed.

Figures 10 and 11 have been provided to illustrate further details regarding suitable data storage device configurations in accordance with the present discussion. 10 shows a functional block diagram of a solid state drive (SSD) data storage device 300 in accordance with some embodiments.

Controller 302 provides top-level control for device 300 and may correspond to controller 102 of FIG. 1 . Interface circuitry 304 and local buffer memory 306 coordinate the transfer of user data between external host devices and flash memory 308 . Read/write/erase circuitry 310 performs the necessary encoding of incoming write data and directs programming of the appropriate flash memory cells to write the encoded write data to memory 308 .

A power management (MGMT) circuit 312 represents the elements for implementing the power flow of FIG. 5 and operates according to the sequence of FIGS. 6-7 .

11 provides a functional block diagram of a hard disk drive (HDD) or hybrid solid state drive (HSSD) storage device 400 in some embodiments. Controller circuit 402, interface circuit 404, and buffer memory 405 operate as shown in FIG. 10 to coordinate data transfers with the host device. Flash memory 406 provides local non-volatile semiconductor memory for storing data.

Read/write (R/W) channel 408 and preamp/driver (preamp) 410 support the use of data read/write transducer (head) 414 to transfer data to a rotatable recording medium (disk) 412. Head position is controlled using a voice coil motor (VCM) 416 and a closed loop servo control circuit 418 . Data from the host may be stored to flash memory 406 and/or disk 412 as desired. As before, channel 408 encodes data during write operations and restores data during subsequent read operations.

The power management (MGMT) circuit 420 generally corresponds to the circuitry shown in FIG. 5 and operates according to the sequence flows of FIGS. 6 and 7 .

It will now be appreciated that the various embodiments presented herein provide various benefits over the prior art. The dual port peripheral provides the ability to evaluate, verify and present electrical power from an external source through the second port to the host via the first port. While a data storage device provides a particularly suitable environment for the implementation of the various embodiments, basically any form of peripheral device may be used. Furthermore, while the Thunderbolt 3 (TBT3) interface has been conceived to be particularly suitable for implementing these power and data transfers using the USB 3.0 standard, this is merely an example.

It is to be understood that even though the numerous features and advantages of various embodiments of the present disclosure have been set forth in the foregoing description, as well as details of the structure and function of the various embodiments, this detailed description is intended to be illustrative only, and, among other things, Detailed changes may be made in the construction and arrangement of components within the principles of the present disclosure, to the full extent indicated by the broad meanings of the terms of the appended claims.

Claims (20)

1. A method, comprising:

using the first serial cable to establish a first data link and a first power transmission link between a first serial port of the peripheral device and the host device;

using a second serial cable to establish a second data link and a second power transmission link between a second serial port of the peripheral device and an external Power Supply Unit (PSU);

using the second data transmission link to detect available power from the external PSU at a level suitable for use by the host device;

transmitting an indication of the available power from the external PSU to the host device via the first data link; and

interconnecting the first serial port and the second serial port to flow regulated power to the host device via the first power transmission link and the second power transmission link in response to a request for the available power from the host device to the peripheral device via the first data transmission link.

2. The method of claim 1, wherein the peripheral device comprises a controller circuit configured to detect the available power from the external PSU by requesting an available power profile from the external PSU using the second data link, the available power profile indicating a maximum power level that can be supplied by the external PSU using the second serial port.

3. The method of claim 2, wherein the controller circuit establishes a first power delivery contract with the external PSU to supply the maximum power level to the second serial port for at least a minimum selected time period, and establishes a second power delivery contract with a host controller circuit of the host device to supply the maximum power level to the first serial port for at least the minimum selected time period.

4. The method of claim 1, wherein the regulated power is used to recharge a battery of the host device.

5. The method of claim 1, wherein the peripheral device is further configured with a power jack connection to receive power from a wall outlet via an intermediate transformer and a power cable, wherein the power jack connection and the second power transmission link are connected as inputs to a multiplexer (mux) of the peripheral device, and wherein a power management circuit is configured to alternately couple the power jack connection and the second power transmission link to the first data transmission link, respectively, in response to an absence or presence of the request for the available power from the host device, respectively.

6. The method of claim 1, wherein the peripheral device further comprises a buck-boost voltage converter configured to provide output power at a plurality of output voltages in response to the power supplied by the external PSU, and wherein the request from the host device for the available power comprises a request to supply the power at a selected one of the plurality of output voltages.

7. The method of claim 1, wherein the peripheral device comprises a backup power source, and wherein the backup power source supplies power for use by the peripheral device in response to the external PSU being disconnected from the second serial port.

8. The method of claim 7, wherein the backup electrical power source comprises a rechargeable battery of the peripheral device, and wherein a portion of the power supplied by the external PSU to the second serial port is used to recharge the rechargeable battery.

9. The method of claim 1, wherein the peripheral device is characterized as a data storage device comprising a memory controller circuit and a non-volatile memory (NVM), the memory controller circuitry is configured to direct data transfer between the NVM and the host device using the first data transfer link of the first serial cable, wherein the host device powers host controller circuitry using a portion of the power supplied by the external PSU, the host controller circuit generates a data transfer command and sends the data transfer command to the data storage device along the first data transfer link, and wherein the data storage device powers the memory controller circuitry and the NVM using another portion of the power supplied by the external PSU to service the data transfer command.

10. The method of claim 1, wherein the first serial cable and the second serial cable are characterized as cables that transmit data and power according to a USB (universal serial bus) 3.0 standard.

11. An apparatus, the apparatus comprising:

a first serial port configured to establish a first data link and a first power transmission link to a host device;

a second serial port configured to establish a second data link and a second power transmission link to a daisy-chained device; and

power management circuitry operably coupled between the first serial port and the second serial port, the power management circuitry configured to detect an amount of available power from an external Power Supply Unit (PSU) coupled to the second serial port, configured to negotiate a transfer of the available power from the external PSU to the host device, and configured to interconnect the first serial port and the second serial port to initiate a flow of the available power from the external PSU, the flow of available power being along the second power transmission link to the second serial port, through a voltage converter circuit to the first serial port, and along the first power transmission link to the host device.

12. The apparatus of claim 11, wherein a dual port computer peripheral is configured to couple to the host device using the first serial port and a first serial cable, and is configured to couple to the external PSU using the second serial port and a second serial cable.

13. The apparatus of claim 12, wherein the dual port computer peripheral is characterized as a data storage device comprising a memory controller circuit and a non-volatile memory (NVM), the memory controller circuit configured to direct data transfer between the NVM and the host device using the first serial cable.

14. The apparatus of claim 11, wherein the power management circuitry comprises controller circuitry configured to detect the available power from the external PSU by requesting an available power profile from the external PSU using the second data link, the available power profile indicating a maximum power level that can be supplied by the external PSU using the second serial port.

15. The apparatus of claim 11, further comprising a power jack connection configured to receive electrical power from a wall outlet via an intermediate transformer and a power cable, and wherein the power management circuitry comprises a multiplexer (mux) configured to selectively connect each of the power jack connection and the second serial port to the first serial port in response to an input supplied by control logic circuitry.

16. The apparatus of claim 11, wherein the power management circuitry comprises a buck-boost voltage converter configured to increase a voltage of the power supplied by the external PSU from a first lower magnitude to a second higher magnitude, and wherein the power management circuitry is further configured to supply the power to the first serial port at the second higher magnitude.

17. The apparatus of claim 11, wherein the peripheral device comprises a backup power source, and wherein the backup power source is configured to automatically supply power for use by the peripheral device in response to the external PSU being disconnected from the second serial port.

18. The apparatus of claim 11, wherein the first serial port and the second serial port are configured to transmit data and power according to a USB (universal serial bus) 3.0 standard.

19. A system, comprising:

a computer peripheral comprising a peripheral controller circuit, a voltage converter circuit, a first serial port, and a second serial port;

a computer host device including a host controller circuit and a host port connected to the first serial port using a first serial cable to facilitate data transfer along a first data transfer path and power transfer along a first power transfer path;

an external Power Supply Unit (PSU) device including a PSU controller circuit and an external port connected to the second serial port using a second serial cable to facilitate data transfer along a second data transmission path and power transfer along a second power transmission path;

the peripheral controller circuit is configured to negotiate a transfer of available power from the external PSU to the host device in response to detecting the available power from the external PSU at the second serial port, and is configured to interconnect the first serial port and the second serial port to initiate a flow of the available power from the external PSU along the second power transfer link to the second serial port, through the voltage converter circuit to the first serial port, and along the first power transfer link to the host device.

20. The system of claim 19, wherein the computer peripheral device is characterized as a Solid State Drive (SSD) further having flash memory, the peripheral controller circuit further configured to transfer data between the flash memory and the host device using the first data transfer path during the transfer of the available power to the host device along the first power transfer path.

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