[go: up one dir, main page]

CN114420569B - Fan-out type packaging method and packaging structure - Google Patents

Fan-out type packaging method and packaging structure Download PDF

Info

Publication number
CN114420569B
CN114420569B CN202111608147.5A CN202111608147A CN114420569B CN 114420569 B CN114420569 B CN 114420569B CN 202111608147 A CN202111608147 A CN 202111608147A CN 114420569 B CN114420569 B CN 114420569B
Authority
CN
China
Prior art keywords
chip
layer
temporary carrier
forming
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202111608147.5A
Other languages
Chinese (zh)
Other versions
CN114420569A (en
Inventor
李尚轩
郑子企
仇阳阳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nantong Tongfu Microelectronics Co ltd
Original Assignee
Nantong Tongfu Microelectronics Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nantong Tongfu Microelectronics Co ltd filed Critical Nantong Tongfu Microelectronics Co ltd
Priority to CN202111608147.5A priority Critical patent/CN114420569B/en
Publication of CN114420569A publication Critical patent/CN114420569A/en
Application granted granted Critical
Publication of CN114420569B publication Critical patent/CN114420569B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides a fan-out type packaging method and a packaging structure, wherein the method comprises the following steps: providing a chip, a first temporary carrier disc and a second temporary carrier disc; the first surface of the second temporary carrier disc is provided with a first metal seed layer; forming a conductive connecting piece on the first surface of the chip, and fixing the first surface of the chip to a first temporary carrier disc; sequentially forming a second metal seed layer and a metal layer on the second surface of the chip; separating the chip from the first temporary carrier disc; performing hot-press bonding on the metal layer on the second surface of the chip and the first metal seed layer of the second temporary carrier disc; forming a plastic sealing layer on the first surface of the chip, and separating the chip from the second temporary carrier disc; a redistribution layer is formed over the conductive connections of the chip. The packaging method can improve chip offset, is easy to manufacture, can be widely applied to the semiconductor packaging industry, greatly improves the chip production yield, and saves time and material cost.

Description

Fan-out type packaging method and packaging structure
Technical Field
The invention belongs to the technical field of semiconductor packaging, and particularly relates to a fan-out type packaging method and a fan-out type packaging structure.
Background
Currently, in the semiconductor packaging industry, fan-out wafer level packaging is a mature technology applied to many mobile applications, and there are two main ways of respectively using a first wafer and a second wafer. The advantage of the wafer-first process is that the process has a mature process and low cost, but the problems of die chip offset, poor chip/plastic package interface flatness and wafer warpage still exist in the process, resulting in low yield.
At present, when a chip reorganization bonding process is performed in a fan-out type packaging process, a double-sided adhesive tape is attached to a carrier, and qualified chips are picked up and placed on the double-sided adhesive tape, so that due to the limitation of the accuracy of a sticking/mounting machine and the viscosity of the double-sided adhesive tape, the chips can deviate or are washed away by the sealing adhesive tape after being pressed and molded by using epoxy resin sealing adhesive tape, and the subsequent rewiring process and the like can be adversely affected due to the risk, so that the production yield is greatly reduced, and the time and the material cost are wasted.
In view of the above, it is necessary to provide a fan-out type packaging method and a packaging structure which are reasonable in design and can effectively solve the above problems.
Disclosure of Invention
The invention aims to at least solve one of the technical problems in the prior art and provides a fan-out type packaging method and a packaging structure.
One aspect of the present invention provides a fan-out packaging method, the packaging method comprising:
Providing a chip, a first temporary carrier disc and a second temporary carrier disc; the first surface of the second temporary carrier disc is provided with a first metal seed layer;
Forming a conductive connection on a first surface of the chip and fixing the first surface of the chip to the first temporary carrier plate;
sequentially forming a second metal seed layer and a metal layer on the second surface of the chip;
Separating the chip from the first temporary carrier tray;
Performing hot-press bonding on the metal layer on the second surface of the chip and the first metal seed layer of the second temporary carrier disc;
Forming a plastic sealing layer on the first surface of the chip, and separating the chip from the second temporary carrier disc;
and forming a rewiring layer on the conductive connecting piece of the chip.
Optionally, the thermocompression bonding the metal layer on the second surface of the chip and the first metal seed layer of the second temporary carrier disc includes:
and (3) adopting a hot-press welding process, and bonding the metal layer on the second surface of the chip with the surface atoms of the first metal seed layer of the second temporary carrier disc by applying preset pressure and temperature.
Optionally, the metal layer is a tin-silver metal layer, and the first metal seed layer is a titanium-copper seed layer.
Optionally, the fixing the first surface of the chip to the first temporary carrier disc includes: forming a first release layer and an adhesive layer on the first temporary carrier plate, and fixing the conductive connecting piece on the first surface of the chip on the adhesive layer;
The separating the chip from the first temporary carrier tray includes: the first release layer is removed such that the chip is separated from the first temporary carrier disk.
Optionally, the second temporary carrier disc is further provided with a second peeling layer, and the first metal seed layer is arranged on the second peeling layer;
the separating the chip from the second temporary carrier tray includes:
removing the second stripping layer by adopting a carrier disc separation technology, so that the chip is separated from the second temporary carrier disc;
And removing the bonded first metal seed layer by adopting a grinding process.
Optionally, after the separating the chip from the second temporary carrier disc, the method further includes:
and thinning one side of the plastic sealing layer, which is away from the second metal seed layer, so as to expose the conductive bump.
Optionally, the forming a conductive connection on the first surface of the chip includes:
forming a bonding pad on the first surface of the chip;
and forming a conductive bump on the bonding pad by adopting an electroplating process.
Optionally, the forming a redistribution layer on the conductive connection of the chip includes:
Forming a first dielectric layer on the conductive bump and the plastic layer;
and patterning the first dielectric layer, and forming a rewiring layer on the patterned first dielectric layer.
Optionally, after the forming of the redistribution layer on the conductive connection of the chip, the method further includes:
Forming a second dielectric layer on the rerouting layer;
and patterning the second dielectric layer, and forming a solder ball on the patterned second dielectric layer.
In another aspect, the present invention provides a fan-out package structure, which is formed by encapsulating by the above-mentioned encapsulation method.
According to the fan-out type packaging method and the fan-out type packaging structure, the metal layer on the second surface of the chip and the first metal seed layer of the second temporary carrier disc are subjected to hot-press bonding. The metal layer on the second surface of the chip and the first metal seed layer of the second temporary carrier disc are bonded in a hot-pressing mode through a hot-pressing bonding process, wafer-level bonding can be achieved at a low temperature, an electric field (anodic bonding) or a complex pre-bonding cleaning procedure (plasma-assisted direct silicon bonding) is not required, and airtight sealing and electric connection can be achieved in the bonding process; the hot-press bonding process is adopted, so that higher chip accuracy can be obtained when the chip is sealed by the sealing glue, the risk that the chip is offset or washed away by the sealing glue after press forming is reduced, the process flow is simple, no complex procedure is adopted, the production yield is greatly improved, and the time and the material cost are saved; the hot-press bonding process can obtain higher chip accuracy, and is favorable for realizing more complex wiring structures such as 6p6m and the like in the subsequent re-wiring process. The packaging method is easy to manufacture, can be widely applied to the semiconductor packaging industry, greatly improves the chip production yield, and saves the time and the material cost.
Drawings
FIG. 1 is a flow chart of a fan-out package method according to an embodiment of the invention;
Fig. 2 to fig. 9 are schematic views illustrating a packaging process of a fan-out packaging method according to another embodiment of the invention.
Detailed Description
The present invention will be described in further detail below with reference to the drawings and detailed description for the purpose of better understanding of the technical solution of the present invention to those skilled in the art.
As shown in fig. 1, an aspect of the present invention provides a fan-out encapsulation method S100, where the encapsulation method S100 includes:
S110, providing a chip, a first temporary carrier disc and a second temporary carrier disc; the first surface of the second temporary carrier disc is provided with a first metal seed layer.
Specifically, as shown in fig. 2 and 6, a chip 110, a first temporary carrier 120, and a second temporary carrier 130 are provided; wherein a first surface of the second temporary carrier 130 is provided with a first metal seed layer 140.
In the present embodiment, the first temporary carrier 120 is a glass carrier, and the second temporary carrier 130 is a metal carrier. Of course, other than this, those skilled in the art may select the materials of the first temporary carrier plate 120 and the second temporary carrier plate 130 according to actual needs, for example, silicon wafer, glass fiber resin sheet, etc., and the embodiment is not limited specifically.
It should be further noted that, in the present embodiment, the first metal seed layer 140 is a titanium-copper seed layer, specifically, the first metal seed layer 140 is 1k titanium and 2k copper. Of course, other metal materials may be selected to form the first metal seed layer 140 according to actual needs, for example, the material of the first metal seed layer 140 may be selected from copper, nickel, chrome-copper alloy, nickel-vanadium alloy, nickel-gold alloy, aluminum, and other metal materials.
S120, forming a conductive connecting piece on the first surface of the chip, and fixing the first surface of the chip to the first temporary carrier disc.
Specifically, the conductive connection member is formed on the first surface of the chip 110 through an electroplating process, and in this embodiment, the conductive connection member is formed on the front surface of the chip 110.
The process of forming the conductive connection specifically includes: as shown in fig. 2, a pad 111 is formed on a first surface of the chip 110, and then a conductive bump 112 is formed on the pad 111 using an electroplating process. The pads 111 are in one-to-one correspondence with the conductive bumps 112.
In this embodiment, the material of the pad 111 is metal copper, the material of the conductive bump 112 is also metal copper, and the pad 111 and the conductive bump 112 may be made of other metal materials.
It should be further noted that the conductive bump 112 may be formed by sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition, which is not limited in this embodiment.
Illustratively, said securing the first surface of the chip to the first temporary carrier plate comprises:
As shown in fig. 2, a first peeling layer 121 and an adhesive layer 122 are formed on the first temporary carrier plate 120, and the conductive connection member on the first surface of the chip 110 is fixed on the adhesive layer 122, that is, the conductive bump 112 on the front surface of the chip 110 is fixed on the adhesive layer 122.
Fixing the first surface of the chip 110 to the first temporary carrier plate 120 may provide for better formation of the second metal seed layer 150 and the metal layer 160 on the second surface of the chip 110.
S130, sequentially forming a second metal seed layer and a metal layer on the second surface of the chip.
Specifically, as shown in fig. 3, a second metal seed layer 150 is formed on the second surface of the chip 110, that is, on the back surface of the chip 110, by a sputtering process, and then a metal layer 160 is formed on the second metal seed layer 150 by an electroplating process.
In this embodiment, the second metal seed layer 150 is a titanium-copper seed layer, specifically, the second metal seed layer 150 is 1k titanium and 2k copper. Of course, other metal materials may be selected to form the second metal seed layer 150 according to actual needs, for example, the material of the first metal seed layer 140 may be selected from copper, nickel, chrome-copper alloy, nickel-vanadium alloy, nickel-gold alloy, aluminum, and the like. The second metal seed layer 150 may be formed by electroplating, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition, which is not limited in this embodiment.
In this embodiment, the metal layer 160 is a tin-silver metal layer, or may be a metal layer made of other materials, which is not particularly limited. The metal layer 160 may be formed by sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, electron cyclotron resonance chemical vapor deposition, or the like, which is not limited in this embodiment.
S140, separating the chip from the first temporary carrier disc.
Specifically, as shown in fig. 4, the first peeling layer 121 and the adhesive layer 122 are removed using a temporary glass tray separation technique, so that the chip 110 is separated from the first temporary tray 120. Forming the first peeling layer 121 on the first temporary carrier 120 makes it easier and faster to separate when the chip 110 and the first temporary carrier 120 need to be separated.
It should be noted that, as shown in fig. 5, after the above packaging steps are completed, the chips are required to be cut into a plurality of independent chips.
And S150, performing hot-press bonding on the metal layer on the second surface of the chip and the first metal seed layer of the second temporary carrier disc.
Specifically, as shown in fig. 6, the metal layer 160 of the second surface of the plurality of individual chips 110 is bonded to the surface atoms of the first metal seed layer 140 on the second temporary carrier plate 130 by applying a preset pressure and temperature using a thermal pressure welding process. That is, the tin-silver metal layer on the back surface of the individual chip 110 is bonded to the surface atoms of the titanium-copper seed layer on the second temporary carrier plate 130 by applying a predetermined pressure and temperature using a thermocompression bonding process. Thereby forming a stable bond between the chip 110 and the second temporary carrier plate 130, and chip offset can be improved.
It should be noted that, in the present embodiment, the metal layer 160 on the second surface of the plurality of independent chips 110 and the surface atoms of the first metal seed layer 140 on the second temporary carrier 130 are bonded by using an ultrasonic hot pressing process, wherein the pressure and the temperature required in the ultrasonic hot pressing are selected according to the metal proportion in the alloy.
The thermocompression bonding process is a solid state bonding process without an intermediate layer, more specifically diffusion bonding. Under the simultaneous application of pressure and temperature, bonding is formed by surface atom contact, and comprises three stages: interface formation, crystal mismatch regulation, and grain growth.
S160, forming a plastic sealing layer on the first surface of the chip, and separating the chip from the second temporary carrier disc.
Specifically, as shown in fig. 7, after the chip 110 and the second temporary carrier 130 are bonded, a plastic layer 170 is formed on the first surface of the chip 110 by a press molding process, and the chip 110 is encapsulated in the plastic layer 170.
As illustrated in fig. 6 and 7, the second temporary carrier 130 is further provided with a second peeling layer 131, and the first metal seed layer 140 is disposed on the second peeling layer 131.
The separating the chip from the second temporary carrier tray includes:
first, as shown in fig. 8, the second release layer 131 is removed by using a carrier separation technique, so that the chip 110 and the second temporary carrier 130 are better separated, and the separation method may be thermal separation, laser separation, ultraviolet separation, mechanical separation, or the like.
Then, as shown in fig. 8, the bonded first metal seed layer 140 is removed using a grinding process.
The process of removing the second peeling layer 131 and removing the first metal seed layer 140 is not particularly limited in this embodiment, and may be selected as needed.
After the chip 110 is separated from the second temporary carrier plate 130, the plastic layer 170 needs to be thinned to expose the conductive bumps 112 on the chip 110. The plastic layer 170 may be thinned in a grinding process or other processes.
S170, forming a rewiring layer on the conductive connecting piece of the chip.
Specifically, as shown in fig. 9, first, a first dielectric layer 180 is formed on the conductive bump 112 and the plastic layer 170. That is, the first dielectric layer 180 is coated on the surfaces of the conductive bump 112 and the plastic layer 170, and the material of the first dielectric layer 180 is Polyimide (PI), polybenzoxazole (PBO), etc., and the coating method is usually wafer spin coating, which is not limited in particular. The first dielectric layer 180 protects the conductive bump 112.
The first dielectric layer 180 is then patterned using a photolithography process, and a re-wiring layer 190 is formed on the patterned first dielectric layer 180. The method of forming the re-wiring layer 190 is sputtering, electroplating, or the like, and the material of the re-wiring layer 190 is typically titanium or copper, and the deposition method of the re-wiring layer 190 and the metal material are not particularly limited in this embodiment.
Next, a second dielectric layer 200 is formed on the re-wiring layer 190. That is, the second dielectric layer 200 is coated on the surface of the re-wiring layer 190, and a material of the second dielectric layer 200 may be a Photoresist (PSR) or the like, which is not particularly limited in this embodiment. The process of covering the redistribution layer 190 with the second dielectric layer 200 may be a vacuum lamination or a printing process, which is not particularly limited in this embodiment.
Finally, the second dielectric layer 200 is patterned by using a photolithography process, and a plurality of solder balls 210 are formed on the patterned second dielectric layer 200 by ball implantation. The package structure is connected to the outside through a plurality of solder balls 210.
After the solder balls 210 are formed, dicing is performed according to the required package size to form the final package structure.
It should be noted that in the embodiment, the dielectric layer structure is 2 layers, and may be 3 layers, 4 layers, or the like, that is, the present invention may be practically applicable to a plurality of layers, and may be adjusted according to actual design requirements.
In the packaging method, the metal layer on the second surface of the chip and the first metal seed layer of the second temporary carrier disc are bonded in a hot-pressing mode. The metal layer on the second surface of the chip and the first metal seed layer of the second temporary carrier disc are bonded in a hot-pressing mode through a hot-pressing bonding process, wafer-level bonding can be achieved at a low temperature, an electric field (anodic bonding) or a complex pre-bonding cleaning procedure (plasma-assisted direct silicon bonding) is not required, and airtight sealing and electric connection can be achieved in the bonding process; the hot-press bonding process is adopted, so that higher chip accuracy can be obtained when the chip is sealed by the sealing glue, the risk that the chip is offset or washed away by the sealing glue after press forming is reduced, the process flow is simple, no complex procedure is adopted, the production yield is greatly improved, and the time and the material cost are saved; the hot-press bonding process can obtain higher chip accuracy, and is favorable for realizing more complex wiring structures such as 6p6m and the like in the subsequent re-wiring process.
In another aspect, the present invention provides a fan-out package structure, which is formed by encapsulating the fan-out package structure with the above-mentioned encapsulation method, and specific steps of the encapsulation method may be described in the related description, which is not repeated herein. The packaging structure formed by adopting the packaging method not only greatly improves the production yield and saves the time and the material cost, but also can obtain higher chip accuracy.
It is to be understood that the above embodiments are merely illustrative of the application of the principles of the present invention, but not in limitation thereof. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the invention, and are also considered to be within the scope of the invention.

Claims (10)

1. A fan-out packaging method, the packaging method comprising:
Providing a chip, a first temporary carrier disc and a second temporary carrier disc; the first surface of the second temporary carrier disc is provided with a first metal seed layer;
Forming a conductive connection on a first surface of the chip and fixing the first surface of the chip to the first temporary carrier plate;
sequentially forming a second metal seed layer and a metal layer on the second surface of the chip;
Separating the chip from the first temporary carrier tray;
Performing hot-press bonding on the metal layer on the second surface of the chip and the first metal seed layer of the second temporary carrier disc;
Forming a plastic sealing layer on the first surface of the chip, and separating the chip from the second temporary carrier disc;
and forming a rewiring layer on the conductive connecting piece of the chip.
2. The method of claim 1, wherein thermocompression bonding the metal layer of the second surface of the chip with the first metal seed layer of the second temporary carrier plate comprises:
and (3) adopting a hot-press welding process, and bonding the metal layer on the second surface of the chip with the surface atoms of the first metal seed layer of the second temporary carrier disc by applying preset pressure and temperature.
3. The method of claim 2, wherein the metal layer is a tin-silver metal layer and the first metal seed layer is a titanium-copper seed layer.
4. A method according to any one of claims 1 to 3, wherein said fixing the first surface of the chip to the first temporary carrier plate comprises: forming a first release layer and an adhesive layer on the first temporary carrier plate, and fixing the conductive connecting piece on the first surface of the chip on the adhesive layer;
The separating the chip from the first temporary carrier tray includes: the first release layer is removed such that the chip is separated from the first temporary carrier disk.
5. A method according to any one of claims 1 to 3, wherein the second temporary carrier disc is further provided with a second release layer, the first metal seed layer being provided on the second release layer;
the separating the chip from the second temporary carrier tray includes:
removing the second stripping layer by adopting a carrier disc separation technology, so that the chip is separated from the second temporary carrier disc;
And removing the bonded first metal seed layer by adopting a grinding process.
6. A method according to any one of claims 1 to 3, wherein after said separating the chip from the second temporary carrier tray, the method further comprises:
and thinning one side of the plastic sealing layer, which is away from the second metal seed layer, so as to expose the conductive bump.
7. A method according to any one of claims 1 to 3, wherein forming conductive connections on the first surface of the chip comprises:
forming a bonding pad on the first surface of the chip;
and forming a conductive bump on the bonding pad by adopting an electroplating process.
8. The method of claim 7, wherein forming a redistribution layer over the conductive connections of the chip comprises:
Forming a first dielectric layer on the conductive bump and the plastic layer;
and patterning the first dielectric layer, and forming a rewiring layer on the patterned first dielectric layer.
9. The method of claim 8, wherein after forming a redistribution layer on the conductive connections of the chip, the method further comprises:
Forming a second dielectric layer on the rerouting layer;
and patterning the second dielectric layer, and forming a solder ball on the patterned second dielectric layer.
10. A fan-out package structure, characterized in that the packaging method according to any of claims 1 to 9 is used.
CN202111608147.5A 2021-12-23 2021-12-23 Fan-out type packaging method and packaging structure Active CN114420569B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111608147.5A CN114420569B (en) 2021-12-23 2021-12-23 Fan-out type packaging method and packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111608147.5A CN114420569B (en) 2021-12-23 2021-12-23 Fan-out type packaging method and packaging structure

Publications (2)

Publication Number Publication Date
CN114420569A CN114420569A (en) 2022-04-29
CN114420569B true CN114420569B (en) 2024-08-20

Family

ID=81269096

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111608147.5A Active CN114420569B (en) 2021-12-23 2021-12-23 Fan-out type packaging method and packaging structure

Country Status (1)

Country Link
CN (1) CN114420569B (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201834191A (en) * 2016-11-18 2018-09-16 大陸商華為技術有限公司 Chip Package Structure and Method
CN111668113A (en) * 2019-03-08 2020-09-15 矽磐微电子(重庆)有限公司 Semiconductor packaging method and semiconductor packaging assembly

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3686267B2 (en) * 1998-10-28 2005-08-24 株式会社ルネサステクノロジ Manufacturing method of semiconductor device
US6853067B1 (en) * 1999-10-12 2005-02-08 Microassembly Technologies, Inc. Microelectromechanical systems using thermocompression bonding
JP3991624B2 (en) * 2001-06-26 2007-10-17 日亜化学工業株式会社 Surface mount type light emitting device and manufacturing method thereof
CN103681458B (en) * 2012-09-03 2016-06-01 华进半导体封装先导技术研发中心有限公司 A kind of method of three-dimension flexible stack package structure making embedded ultra-thin chip
US9799592B2 (en) * 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells
CN108538737B (en) * 2018-03-22 2019-12-24 江西芯创光电有限公司 Pressing method of carrier plate
CN109003907B (en) * 2018-08-06 2021-10-19 中芯集成电路（宁波）有限公司 Packaging method
US11616046B2 (en) * 2018-11-02 2023-03-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
TW202036812A (en) * 2019-03-26 2020-10-01 新加坡商Ｐｅｐ創新有限公司 Semiconductor device packaging method and semiconductor device capable of improving the parameter stability of the packaged product and increasing the yield

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201834191A (en) * 2016-11-18 2018-09-16 大陸商華為技術有限公司 Chip Package Structure and Method
CN111668113A (en) * 2019-03-08 2020-09-15 矽磐微电子(重庆)有限公司 Semiconductor packaging method and semiconductor packaging assembly

Also Published As

Publication number Publication date
CN114420569A (en) 2022-04-29

Similar Documents

Publication Publication Date Title
TWI841586B (en) Chip packaging method
US11848310B2 (en) Semiconductor device and method of manufacturing thereof
US6841413B2 (en) Thinned die integrated circuit package
CN110729257A (en) Chip packaging method and chip structure
US20220392884A1 (en) Integrated Circuit Package and Method
US7445963B2 (en) Semiconductor package having an interfacial adhesive layer
US11646299B2 (en) Method of manufacturing a semiconductor package including a first sub-package stacked atop a second sub-package
US20220051909A1 (en) Method of manufacturing an electronic device and electronic device manufactured thereby
US11996400B2 (en) Manufacturing method of package on package structure
US20210233890A1 (en) Packaging structures
CN117116899A (en) Wafer-level integrated packaging structure and method for core particles
CN108962766B (en) Package structure and method for forming the same
CN114420569B (en) Fan-out type packaging method and packaging structure
CN117038485A (en) Temporary bonding and underfilling method
CN114649281B (en) A wafer-level fan-out packaging structure and manufacturing method thereof
TWI425580B (en) Process for manufacturing semiconductor chip packaging module
CN112687661A (en) Modular packaging structure and method
TWI880515B (en) Fan-out package assembly preparation method
CN115295434A (en) Fan-out type packaging method and packaging structure
CN116207026A (en) Semiconductor manufacturing apparatus and method of providing support substrate
TW202343692A (en) Packaging method and package structure
TW202410210A (en) Electronic circuit fabrication
TW202349575A (en) Semiconductor device and method for advanced thermal dissipation
CN117276217A (en) Fan-out type packaging structure and fan-out type packaging method
TW202046413A (en) Method for forming a semiconductor package

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant